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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [verilog/] [mor1kx_cfgrs.v] - Blame information for rev 38

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/* ****************************************************************************
  This Source Code Form is subject to the terms of the
  Open Hardware Description License, v. 1.0. If a copy
  of the OHDL was not distributed with this file, You
  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
 
  Description: mor1kx SPRs indicating configuration and version
 
  All registers are read only and configured at synthesis time.
 
  Note that the outputs do not have the usual "_o" prefix on the port names
  as this module is intended to be instantiated without a Verilog-mode
  AUTO_TEMPLATE, and as the module is providing read-only signals, there's
  no confusion about the direction of the ports.
 
  Copyright (C) 2012 Authors
 
  Author(s): Julius Baxter <juliusbaxter@gmail.com>
 
***************************************************************************** */
 
`include "mor1kx-defines.v"
 
module mor1kx_cfgrs
  #(
    parameter FEATURE_SYSCALL            = "ENABLED",
    parameter FEATURE_TRAP               = "ENABLED",
    parameter FEATURE_RANGE              = "ENABLED",
 
    parameter FEATURE_DATACACHE          = "NONE",
    parameter OPTION_DCACHE_BLOCK_WIDTH  = 5,
    parameter OPTION_DCACHE_SET_WIDTH    = 9,
    parameter OPTION_DCACHE_WAYS         = 2,
    parameter FEATURE_DMMU               = "NONE",
    parameter OPTION_DMMU_SET_WIDTH      = 6,
    parameter OPTION_DMMU_WAYS           = 1,
    parameter FEATURE_INSTRUCTIONCACHE   = "NONE",
    parameter OPTION_ICACHE_BLOCK_WIDTH  = 5,
    parameter OPTION_ICACHE_SET_WIDTH    = 9,
    parameter OPTION_ICACHE_WAYS         = 2,
    parameter FEATURE_IMMU               = "NONE",
    parameter OPTION_IMMU_SET_WIDTH      = 6,
    parameter OPTION_IMMU_WAYS           = 1,
    parameter FEATURE_PIC                = "ENABLED",
    parameter FEATURE_TIMER              = "ENABLED",
    parameter FEATURE_DEBUGUNIT          = "NONE",
    parameter FEATURE_PERFCOUNTERS       = "NONE",
    parameter FEATURE_PMU                = "NONE",
    parameter FEATURE_MAC                = "NONE",
    parameter FEATURE_FPU                = "NONE",
 
    parameter OPTION_PIC_TRIGGER         = "LEVEL",
 
    parameter FEATURE_DSX                = "NONE",
    parameter FEATURE_FASTCONTEXTS       = "NONE",
    parameter OPTION_RF_NUM_SHADOW_GPR   = 0,
    parameter FEATURE_OVERFLOW           = "NONE",
 
    parameter FEATURE_DELAYSLOT          = "NONE",
 
    parameter FEATURE_EVBAR              = "NONE",
    parameter FEATURE_AECSR              = "NONE"
    )
   (
    output [31:0] spr_vr,
    output [31:0] spr_vr2,
    output [31:0] spr_upr,
    output [31:0] spr_cpucfgr,
    output [31:0] spr_dmmucfgr,
    output [31:0] spr_immucfgr,
    output [31:0] spr_dccfgr,
    output [31:0] spr_iccfgr,
    output [31:0] spr_dcfgr,
    output [31:0] spr_pccfgr,
    output [31:0] spr_fpcsr,
    output [31:0] spr_avr
    );
 
   assign spr_vr[`OR1K_SPR_VR_REV] = 0;
   assign spr_vr[`OR1K_SPR_VR_UVRP] = 1;
   assign spr_vr[`OR1K_SPR_VR_RESERVED] = 0;
   assign spr_vr[`OR1K_SPR_VR_CFG] = 0;
   assign spr_vr[`OR1K_SPR_VR_VER] = 8'h10;
 
   assign spr_upr[`OR1K_SPR_UPR_UP] = 1;
   assign spr_upr[`OR1K_SPR_UPR_DCP] = (FEATURE_DATACACHE!="NONE");
   assign spr_upr[`OR1K_SPR_UPR_ICP] = (FEATURE_INSTRUCTIONCACHE!="NONE");
   assign spr_upr[`OR1K_SPR_UPR_DMP] = (FEATURE_DMMU!="NONE");
   assign spr_upr[`OR1K_SPR_UPR_IMP] = (FEATURE_IMMU!="NONE");
   assign spr_upr[`OR1K_SPR_UPR_MP] = (FEATURE_MAC!="NONE");
   assign spr_upr[`OR1K_SPR_UPR_DUP] = (FEATURE_DEBUGUNIT!="NONE");
   assign spr_upr[`OR1K_SPR_UPR_PCUP] = (FEATURE_PERFCOUNTERS!="NONE");
   assign spr_upr[`OR1K_SPR_UPR_PICP] = (FEATURE_PIC!="NONE");
   assign spr_upr[`OR1K_SPR_UPR_PMP] = (FEATURE_PMU!="NONE");
   assign spr_upr[`OR1K_SPR_UPR_TTP] = (FEATURE_TIMER!="NONE");
   assign spr_upr[`OR1K_SPR_UPR_RESERVED] = 0;
   assign spr_upr[`OR1K_SPR_UPR_CUP] = 0;
 
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_NSGF] = OPTION_RF_NUM_SHADOW_GPR;
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_CFG] = 0;
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OB32S] = 1;
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OB64S] = 0;
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OF32S] = 0;
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OF64S] = 0;
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OV64S] = 0;
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_ND] = (FEATURE_DELAYSLOT=="NONE");
   /* AVR will always be present in mor1kx */
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_AVRP] = 1;
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_EVBARP] = (FEATURE_EVBAR!="NONE");
   /* ISRs will always be present */
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_ISRP] = 1;
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_AECSRP] = (FEATURE_AECSR!="NONE");
   assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_RESERVED] = 0;
 
   /* Version register 2 */
   /* Implementation ID as per:
      http://opencores.org/or1k/OR1K_CPU_Cores#CPU_ID_Table
      mor1kx breaks up the VR2[23:0] to be 3 8-bit fields
      23:16 - Major version number
      15:8  - Minor version number
      7:0   - Pipeline implementation identifier (set outside of this module)
   */
   assign spr_vr2[`OR1K_SPR_VR2_CPUID] = `MOR1KX_CPUID;
   assign spr_vr2[`OR1K_SPR_VR2_VER] = {`MOR1KX_VERSION_MAJOR,
                                        `MOR1KX_VERSION_MINOR,
                                        8'd0};
 
   /* Currently supporting OR1K version 1.1 rev0 */
   assign spr_avr[`OR1K_SPR_AVR_MAJ] = 8'd1;
   assign spr_avr[`OR1K_SPR_AVR_MIN] = 8'd1;
   assign spr_avr[`OR1K_SPR_AVR_REV] = 8'd0;
   assign spr_avr[`OR1K_SPR_AVR_RESERVED] = 0;
 
   /* Data MMU Configuration Register */
   /* Reserved */
   assign spr_dmmucfgr[31:15] = 0;
   /* Hardware TLB Reload */
   assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_HTR] = 0;
   /* TLB Entry Invalidate Register Implemented */
   assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_TEIRI] = 0;
   /* Protection Register Implemented */
   assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_PRI] = 0;
   /* Control Register Implemented */
   assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_CRI] = 0;
   /* Number of ATB entries */
   assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NAE] = 0;
   /* Number of TLB sets */
   assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NTS] = (FEATURE_DMMU!="NONE") ?
                                                OPTION_DMMU_SET_WIDTH : 0;
   /* Number of TLB ways */
   assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NTW] = (FEATURE_DMMU!="NONE") ?
                                                OPTION_DMMU_WAYS-1 : 0;
 
   /* Instruction MMU Configuration Register */
   /* Reserved */
   assign spr_immucfgr[31:15] = 0;
   /* Hardware TLB Reload */
   assign spr_immucfgr[`OR1K_SPR_IMMUFGR_HTR] = 0;
   /* TLB Entry Invalidate Register Implemented */
   assign spr_immucfgr[`OR1K_SPR_IMMUFGR_TEIRI] = 0;
   /* Protection Register Implemented */
   assign spr_immucfgr[`OR1K_SPR_IMMUFGR_PRI] = 0;
   /* Control Register Implemented */
   assign spr_immucfgr[`OR1K_SPR_IMMUFGR_CRI] = 0;
   /* Number of ATB entries */
   assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NAE] = 0;
   /* Number of TLB sets */
   assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NTS] = (FEATURE_IMMU!="NONE") ?
                                                OPTION_IMMU_SET_WIDTH : 0;
   /* Number of TLB ways */
   assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NTW] = (FEATURE_IMMU!="NONE") ?
                                                OPTION_IMMU_WAYS-1 : 0;
 
   /* Data Cache Configuration register */
   /* Reserved */
   assign spr_dccfgr[31:15] = 0;
   /* Cache Block Write-Back Register Implemented */
   assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBWBRI] = 0;
   /* Cache Block Flush Register Implemented */
   assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBFRI] = (FEATURE_DATACACHE!="NONE");
   /* Cache Block Lock Register Implemented */
   assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBLRI] = 0;
   /* Cache Block Prefetch Register Implemented */
   assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBPRI] = 0;
   /* Cache Block Invalidate Register Implemented */
   assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBIRI] = (FEATURE_DATACACHE!="NONE");
   /* Cache Control Register Implemented */
   assign spr_dccfgr[`OR1K_SPR_DCCFGR_CCRI] = 0;
   /* Cache Write Strategy (0 = write-through, 1 = write-back) */
   assign spr_dccfgr[`OR1K_SPR_DCCFGR_CWS] = 0;
   /* Cache Block Size (0 = 16 bytes, 1 = 32 bytes) */
   assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBS] = (FEATURE_DATACACHE!="NONE") ?
                                             (OPTION_DCACHE_BLOCK_WIDTH == 5 ?
                                              1 : 0) :  0;
  /* Number of Cache Sets */
   assign spr_dccfgr[`OR1K_SPR_DCCFGR_NCS] = (FEATURE_DATACACHE!="NONE") ?
                                             OPTION_DCACHE_SET_WIDTH : 0;
   /* Number of Cache Ways */
   assign spr_dccfgr[`OR1K_SPR_DCCFGR_NCW] = (FEATURE_DATACACHE!="NONE") ?
                                             (OPTION_DCACHE_WAYS == 1) ? 3'd0 :
                                             (OPTION_DCACHE_WAYS == 2) ? 3'd1 :
                                             (OPTION_DCACHE_WAYS == 4) ? 3'd2 :
                                             (OPTION_DCACHE_WAYS == 8) ? 3'd3 :
                                             (OPTION_DCACHE_WAYS == 16) ? 3'd4 :
                                             (OPTION_DCACHE_WAYS == 32) ? 3'd5 :
                                             3'd0 : 3'd0;
 
   /* Instruction Cache Configuration register */
   /* Reserved */
   assign spr_iccfgr[31:13] = 0;
   assign spr_iccfgr[8] = 0;
   /* Cache Block Lock Register Implemented */
   assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBLRI] = 0;
   /* Cache Block Prefetch Register Implemented */
   assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBPRI] = 0;
   /* Cache Block Invalidate Register Implemented */
   assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBIRI] = (FEATURE_INSTRUCTIONCACHE!="NONE");
   /* Cache Control Register Implemented */
   assign spr_iccfgr[`OR1K_SPR_ICCFGR_CCRI] = 0;
   /* Cache Block Size (0 = 16 bytes, 1 = 32 bytes) */
   assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBS] = (FEATURE_INSTRUCTIONCACHE!="NONE") ?
                                             (OPTION_ICACHE_BLOCK_WIDTH == 5 ?
                                              1 : 0) :  0;
  /* Number of Cache Sets */
   assign spr_iccfgr[`OR1K_SPR_ICCFGR_NCS] = (FEATURE_INSTRUCTIONCACHE!="NONE") ?
                                             OPTION_ICACHE_SET_WIDTH : 0;
   /* Number of Cache Ways */
   assign spr_iccfgr[`OR1K_SPR_ICCFGR_NCW] = (FEATURE_INSTRUCTIONCACHE!="NONE") ?
                                             (OPTION_ICACHE_WAYS == 1) ? 3'd0 :
                                             (OPTION_ICACHE_WAYS == 2) ? 3'd1 :
                                             (OPTION_ICACHE_WAYS == 4) ? 3'd2 :
                                             (OPTION_ICACHE_WAYS == 8) ? 3'd3 :
                                             (OPTION_ICACHE_WAYS == 16) ? 3'd4 :
                                             (OPTION_ICACHE_WAYS == 32) ? 3'd5 :
                                             3'd0 : 3'd0;
 
   assign spr_dcfgr = 0;
   assign spr_pccfgr = 0;
   assign spr_fpcsr = 0;
 
endmodule // mor1kx_cfgrs

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [verilog/] [mor1kx_cfgrs.v] - Blame information for rev 38

Line No.	Rev	Author	Line
1	38	alirezamon	`/* ****************************************************************************`
2			`This Source Code Form is subject to the terms of the`
3			`Open Hardware Description License, v. 1.0. If a copy`
4			`of the OHDL was not distributed with this file, You`
5			`can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt`
6
7			`Description: mor1kx SPRs indicating configuration and version`
8
9			`All registers are read only and configured at synthesis time.`
10
11			`Note that the outputs do not have the usual "_o" prefix on the port names`
12			`as this module is intended to be instantiated without a Verilog-mode`
13			`AUTO_TEMPLATE, and as the module is providing read-only signals, there's`
14			`no confusion about the direction of the ports.`
15
16			`Copyright (C) 2012 Authors`
17
18			`Author(s): Julius Baxter <juliusbaxter@gmail.com>`
19
20			`***************************************************************************** */`
21
22			`include "mor1kx-defines.v"
23
24			`module mor1kx_cfgrs`
25			`#(`
26			`parameter FEATURE_SYSCALL = "ENABLED",`
27			`parameter FEATURE_TRAP = "ENABLED",`
28			`parameter FEATURE_RANGE = "ENABLED",`
29
30			`parameter FEATURE_DATACACHE = "NONE",`
31			`parameter OPTION_DCACHE_BLOCK_WIDTH = 5,`
32			`parameter OPTION_DCACHE_SET_WIDTH = 9,`
33			`parameter OPTION_DCACHE_WAYS = 2,`
34			`parameter FEATURE_DMMU = "NONE",`
35			`parameter OPTION_DMMU_SET_WIDTH = 6,`
36			`parameter OPTION_DMMU_WAYS = 1,`
37			`parameter FEATURE_INSTRUCTIONCACHE = "NONE",`
38			`parameter OPTION_ICACHE_BLOCK_WIDTH = 5,`
39			`parameter OPTION_ICACHE_SET_WIDTH = 9,`
40			`parameter OPTION_ICACHE_WAYS = 2,`
41			`parameter FEATURE_IMMU = "NONE",`
42			`parameter OPTION_IMMU_SET_WIDTH = 6,`
43			`parameter OPTION_IMMU_WAYS = 1,`
44			`parameter FEATURE_PIC = "ENABLED",`
45			`parameter FEATURE_TIMER = "ENABLED",`
46			`parameter FEATURE_DEBUGUNIT = "NONE",`
47			`parameter FEATURE_PERFCOUNTERS = "NONE",`
48			`parameter FEATURE_PMU = "NONE",`
49			`parameter FEATURE_MAC = "NONE",`
50			`parameter FEATURE_FPU = "NONE",`
51
52			`parameter OPTION_PIC_TRIGGER = "LEVEL",`
53
54			`parameter FEATURE_DSX = "NONE",`
55			`parameter FEATURE_FASTCONTEXTS = "NONE",`
56			`parameter OPTION_RF_NUM_SHADOW_GPR = 0,`
57			`parameter FEATURE_OVERFLOW = "NONE",`
58
59			`parameter FEATURE_DELAYSLOT = "NONE",`
60
61			`parameter FEATURE_EVBAR = "NONE",`
62			`parameter FEATURE_AECSR = "NONE"`
63			`)`
64			`(`
65			`output [31:0] spr_vr,`
66			`output [31:0] spr_vr2,`
67			`output [31:0] spr_upr,`
68			`output [31:0] spr_cpucfgr,`
69			`output [31:0] spr_dmmucfgr,`
70			`output [31:0] spr_immucfgr,`
71			`output [31:0] spr_dccfgr,`
72			`output [31:0] spr_iccfgr,`
73			`output [31:0] spr_dcfgr,`
74			`output [31:0] spr_pccfgr,`
75			`output [31:0] spr_fpcsr,`
76			`output [31:0] spr_avr`
77			`);`
78
79			assign spr_vr[`OR1K_SPR_VR_REV] = 0;
80			assign spr_vr[`OR1K_SPR_VR_UVRP] = 1;
81			assign spr_vr[`OR1K_SPR_VR_RESERVED] = 0;
82			assign spr_vr[`OR1K_SPR_VR_CFG] = 0;
83			assign spr_vr[`OR1K_SPR_VR_VER] = 8'h10;
84
85			assign spr_upr[`OR1K_SPR_UPR_UP] = 1;
86			assign spr_upr[`OR1K_SPR_UPR_DCP] = (FEATURE_DATACACHE!="NONE");
87			assign spr_upr[`OR1K_SPR_UPR_ICP] = (FEATURE_INSTRUCTIONCACHE!="NONE");
88			assign spr_upr[`OR1K_SPR_UPR_DMP] = (FEATURE_DMMU!="NONE");
89			assign spr_upr[`OR1K_SPR_UPR_IMP] = (FEATURE_IMMU!="NONE");
90			assign spr_upr[`OR1K_SPR_UPR_MP] = (FEATURE_MAC!="NONE");
91			assign spr_upr[`OR1K_SPR_UPR_DUP] = (FEATURE_DEBUGUNIT!="NONE");
92			assign spr_upr[`OR1K_SPR_UPR_PCUP] = (FEATURE_PERFCOUNTERS!="NONE");
93			assign spr_upr[`OR1K_SPR_UPR_PICP] = (FEATURE_PIC!="NONE");
94			assign spr_upr[`OR1K_SPR_UPR_PMP] = (FEATURE_PMU!="NONE");
95			assign spr_upr[`OR1K_SPR_UPR_TTP] = (FEATURE_TIMER!="NONE");
96			assign spr_upr[`OR1K_SPR_UPR_RESERVED] = 0;
97			assign spr_upr[`OR1K_SPR_UPR_CUP] = 0;
98
99			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_NSGF] = OPTION_RF_NUM_SHADOW_GPR;
100			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_CFG] = 0;
101			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OB32S] = 1;
102			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OB64S] = 0;
103			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OF32S] = 0;
104			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OF64S] = 0;
105			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_OV64S] = 0;
106			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_ND] = (FEATURE_DELAYSLOT=="NONE");
107			`/* AVR will always be present in mor1kx */`
108			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_AVRP] = 1;
109			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_EVBARP] = (FEATURE_EVBAR!="NONE");
110			`/* ISRs will always be present */`
111			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_ISRP] = 1;
112			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_AECSRP] = (FEATURE_AECSR!="NONE");
113			assign spr_cpucfgr[`OR1K_SPR_CPUCFGR_RESERVED] = 0;
114
115			`/* Version register 2 */`
116			`/* Implementation ID as per:`
117			`http://opencores.org/or1k/OR1K_CPU_Cores#CPU_ID_Table`
118			`mor1kx breaks up the VR2[23:0] to be 3 8-bit fields`
119			`23:16 - Major version number`
120			`15:8 - Minor version number`
121			`7:0 - Pipeline implementation identifier (set outside of this module)`
122			`*/`
123			assign spr_vr2[`OR1K_SPR_VR2_CPUID] = `MOR1KX_CPUID;
124			assign spr_vr2[`OR1K_SPR_VR2_VER] = {`MOR1KX_VERSION_MAJOR,
125			`MOR1KX_VERSION_MINOR,
126			`8'd0};`
127
128			`/* Currently supporting OR1K version 1.1 rev0 */`
129			assign spr_avr[`OR1K_SPR_AVR_MAJ] = 8'd1;
130			assign spr_avr[`OR1K_SPR_AVR_MIN] = 8'd1;
131			assign spr_avr[`OR1K_SPR_AVR_REV] = 8'd0;
132			assign spr_avr[`OR1K_SPR_AVR_RESERVED] = 0;
133
134			`/* Data MMU Configuration Register */`
135			`/* Reserved */`
136			`assign spr_dmmucfgr[31:15] = 0;`
137			`/* Hardware TLB Reload */`
138			assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_HTR] = 0;
139			`/* TLB Entry Invalidate Register Implemented */`
140			assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_TEIRI] = 0;
141			`/* Protection Register Implemented */`
142			assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_PRI] = 0;
143			`/* Control Register Implemented */`
144			assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_CRI] = 0;
145			`/* Number of ATB entries */`
146			assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NAE] = 0;
147			`/* Number of TLB sets */`
148			assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NTS] = (FEATURE_DMMU!="NONE") ?
149			`OPTION_DMMU_SET_WIDTH : 0;`
150			`/* Number of TLB ways */`
151			assign spr_dmmucfgr[`OR1K_SPR_DMMUFGR_NTW] = (FEATURE_DMMU!="NONE") ?
152			`OPTION_DMMU_WAYS-1 : 0;`
153
154			`/* Instruction MMU Configuration Register */`
155			`/* Reserved */`
156			`assign spr_immucfgr[31:15] = 0;`
157			`/* Hardware TLB Reload */`
158			assign spr_immucfgr[`OR1K_SPR_IMMUFGR_HTR] = 0;
159			`/* TLB Entry Invalidate Register Implemented */`
160			assign spr_immucfgr[`OR1K_SPR_IMMUFGR_TEIRI] = 0;
161			`/* Protection Register Implemented */`
162			assign spr_immucfgr[`OR1K_SPR_IMMUFGR_PRI] = 0;
163			`/* Control Register Implemented */`
164			assign spr_immucfgr[`OR1K_SPR_IMMUFGR_CRI] = 0;
165			`/* Number of ATB entries */`
166			assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NAE] = 0;
167			`/* Number of TLB sets */`
168			assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NTS] = (FEATURE_IMMU!="NONE") ?
169			`OPTION_IMMU_SET_WIDTH : 0;`
170			`/* Number of TLB ways */`
171			assign spr_immucfgr[`OR1K_SPR_IMMUFGR_NTW] = (FEATURE_IMMU!="NONE") ?
172			`OPTION_IMMU_WAYS-1 : 0;`
173
174			`/* Data Cache Configuration register */`
175			`/* Reserved */`
176			`assign spr_dccfgr[31:15] = 0;`
177			`/* Cache Block Write-Back Register Implemented */`
178			assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBWBRI] = 0;
179			`/* Cache Block Flush Register Implemented */`
180			assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBFRI] = (FEATURE_DATACACHE!="NONE");
181			`/* Cache Block Lock Register Implemented */`
182			assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBLRI] = 0;
183			`/* Cache Block Prefetch Register Implemented */`
184			assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBPRI] = 0;
185			`/* Cache Block Invalidate Register Implemented */`
186			assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBIRI] = (FEATURE_DATACACHE!="NONE");
187			`/* Cache Control Register Implemented */`
188			assign spr_dccfgr[`OR1K_SPR_DCCFGR_CCRI] = 0;
189			`/* Cache Write Strategy (0 = write-through, 1 = write-back) */`
190			assign spr_dccfgr[`OR1K_SPR_DCCFGR_CWS] = 0;
191			`/* Cache Block Size (0 = 16 bytes, 1 = 32 bytes) */`
192			assign spr_dccfgr[`OR1K_SPR_DCCFGR_CBS] = (FEATURE_DATACACHE!="NONE") ?
193			`(OPTION_DCACHE_BLOCK_WIDTH == 5 ?`
194			`1 : 0) : 0;`
195			`/* Number of Cache Sets */`
196			assign spr_dccfgr[`OR1K_SPR_DCCFGR_NCS] = (FEATURE_DATACACHE!="NONE") ?
197			`OPTION_DCACHE_SET_WIDTH : 0;`
198			`/* Number of Cache Ways */`
199			assign spr_dccfgr[`OR1K_SPR_DCCFGR_NCW] = (FEATURE_DATACACHE!="NONE") ?
200			`(OPTION_DCACHE_WAYS == 1) ? 3'd0 :`
201			`(OPTION_DCACHE_WAYS == 2) ? 3'd1 :`
202			`(OPTION_DCACHE_WAYS == 4) ? 3'd2 :`
203			`(OPTION_DCACHE_WAYS == 8) ? 3'd3 :`
204			`(OPTION_DCACHE_WAYS == 16) ? 3'd4 :`
205			`(OPTION_DCACHE_WAYS == 32) ? 3'd5 :`
206			`3'd0 : 3'd0;`
207
208			`/* Instruction Cache Configuration register */`
209			`/* Reserved */`
210			`assign spr_iccfgr[31:13] = 0;`
211			`assign spr_iccfgr[8] = 0;`
212			`/* Cache Block Lock Register Implemented */`
213			assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBLRI] = 0;
214			`/* Cache Block Prefetch Register Implemented */`
215			assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBPRI] = 0;
216			`/* Cache Block Invalidate Register Implemented */`
217			assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBIRI] = (FEATURE_INSTRUCTIONCACHE!="NONE");
218			`/* Cache Control Register Implemented */`
219			assign spr_iccfgr[`OR1K_SPR_ICCFGR_CCRI] = 0;
220			`/* Cache Block Size (0 = 16 bytes, 1 = 32 bytes) */`
221			assign spr_iccfgr[`OR1K_SPR_ICCFGR_CBS] = (FEATURE_INSTRUCTIONCACHE!="NONE") ?
222			`(OPTION_ICACHE_BLOCK_WIDTH == 5 ?`
223			`1 : 0) : 0;`
224			`/* Number of Cache Sets */`
225			assign spr_iccfgr[`OR1K_SPR_ICCFGR_NCS] = (FEATURE_INSTRUCTIONCACHE!="NONE") ?
226			`OPTION_ICACHE_SET_WIDTH : 0;`
227			`/* Number of Cache Ways */`
228			assign spr_iccfgr[`OR1K_SPR_ICCFGR_NCW] = (FEATURE_INSTRUCTIONCACHE!="NONE") ?
229			`(OPTION_ICACHE_WAYS == 1) ? 3'd0 :`
230			`(OPTION_ICACHE_WAYS == 2) ? 3'd1 :`
231			`(OPTION_ICACHE_WAYS == 4) ? 3'd2 :`
232			`(OPTION_ICACHE_WAYS == 8) ? 3'd3 :`
233			`(OPTION_ICACHE_WAYS == 16) ? 3'd4 :`
234			`(OPTION_ICACHE_WAYS == 32) ? 3'd5 :`
235			`3'd0 : 3'd0;`
236
237			`assign spr_dcfgr = 0;`
238			`assign spr_pccfgr = 0;`
239			`assign spr_fpcsr = 0;`
240
241			`endmodule // mor1kx_cfgrs`