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/******************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: Instruction cache implementation
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Copyright (C) 2012-2013
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Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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Stefan Wallentowitz <stefan.wallentowitz@tum.de>
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******************************************************************************/
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`include "mor1kx-defines.v"
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module mor1kx_icache
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#(
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parameter OPTION_OPERAND_WIDTH = 32,
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parameter OPTION_ICACHE_BLOCK_WIDTH = 5,
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parameter OPTION_ICACHE_SET_WIDTH = 9,
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parameter OPTION_ICACHE_WAYS = 2,
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parameter OPTION_ICACHE_LIMIT_WIDTH = 32
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)
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(
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input clk,
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input rst,
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input ic_access_i,
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output refill_o,
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output refill_req_o,
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output refill_done_o,
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output invalidate_o,
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// CPU Interface
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output cpu_ack_o,
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output reg [`OR1K_INSN_WIDTH-1:0] cpu_dat_o,
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input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_i,
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input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_match_i,
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input cpu_req_i,
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input [OPTION_OPERAND_WIDTH-1:0] wradr_i,
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input [`OR1K_INSN_WIDTH-1:0] wrdat_i,
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input we_i,
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// SPR interface
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input [15:0] spr_bus_addr_i,
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input spr_bus_we_i,
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input spr_bus_stb_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i,
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output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o,
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output reg spr_bus_ack_o
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);
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// States
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localparam IDLE = 4'b0001;
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localparam READ = 4'b0010;
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localparam REFILL = 4'b0100;
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localparam INVALIDATE = 4'b1000;
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// Address space in bytes for a way
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localparam WAY_WIDTH = OPTION_ICACHE_BLOCK_WIDTH + OPTION_ICACHE_SET_WIDTH;
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/*
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* Tag memory layout
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* +---------------------------------------------------------+
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* (index) -> | LRU | wayN valid | wayN tag |...| way0 valid | way0 tag |
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* +---------------------------------------------------------+
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*/
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// The tag is the part left of the index
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localparam TAG_WIDTH = (OPTION_ICACHE_LIMIT_WIDTH - WAY_WIDTH);
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// The tag memory contains entries with OPTION_ICACHE_WAYS parts of
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// each TAGMEM_WAY_WIDTH. Each of those is tag and a valid flag.
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localparam TAGMEM_WAY_WIDTH = TAG_WIDTH + 1;
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localparam TAGMEM_WAY_VALID = TAGMEM_WAY_WIDTH - 1;
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// Additionally, the tag memory entry contains an LRU value. The
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// width of this is actually 0 for OPTION_ICACHE_LIMIT_WIDTH==1
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localparam TAG_LRU_WIDTH = OPTION_ICACHE_WAYS*(OPTION_ICACHE_WAYS-1) >> 1;
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// We have signals for the LRU which are not used for one way
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// caches. To avoid signal width [-1:0] this generates [0:0]
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// vectors for them, which are removed automatically then.
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localparam TAG_LRU_WIDTH_BITS = (OPTION_ICACHE_WAYS >= 2) ? TAG_LRU_WIDTH : 1;
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// Compute the total sum of the entry elements
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localparam TAGMEM_WIDTH = TAGMEM_WAY_WIDTH * OPTION_ICACHE_WAYS + TAG_LRU_WIDTH;
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// For convenience we define the position of the LRU in the tag
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// memory entries
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localparam TAG_LRU_MSB = TAGMEM_WIDTH - 1;
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localparam TAG_LRU_LSB = TAG_LRU_MSB - TAG_LRU_WIDTH + 1;
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// FSM state signals
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reg [3:0] state;
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wire idle;
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wire read;
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wire refill;
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wire invalidate;
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reg [WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH] invalidate_adr;
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wire [31:0] next_refill_adr;
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wire refill_done;
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wire refill_hit;
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reg [(1<<(OPTION_ICACHE_BLOCK_WIDTH-2))-1:0] refill_valid;
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reg [(1<<(OPTION_ICACHE_BLOCK_WIDTH-2))-1:0] refill_valid_r;
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// The index we read and write from tag memory
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wire [OPTION_ICACHE_SET_WIDTH-1:0] tag_rindex;
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wire [OPTION_ICACHE_SET_WIDTH-1:0] tag_windex;
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// The data from the tag memory
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wire [TAGMEM_WIDTH-1:0] tag_dout;
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wire [TAG_LRU_WIDTH_BITS-1:0] tag_lru_out;
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wire [TAGMEM_WAY_WIDTH-1:0] tag_way_out [OPTION_ICACHE_WAYS-1:0];
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// The data to the tag memory
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wire [TAGMEM_WIDTH-1:0] tag_din;
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reg [TAG_LRU_WIDTH_BITS-1:0] tag_lru_in;
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reg [TAGMEM_WAY_WIDTH-1:0] tag_way_in [OPTION_ICACHE_WAYS-1:0];
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reg [TAGMEM_WAY_WIDTH-1:0] tag_way_save [OPTION_ICACHE_WAYS-1:0];
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// Whether to write to the tag memory in this cycle
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reg tag_we;
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// This is the tag we need to write to the tag memory during refill
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wire [TAG_WIDTH-1:0] tag_wtag;
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// This is the tag we check against
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wire [TAG_WIDTH-1:0] tag_tag;
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// Access to the way memories
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wire [WAY_WIDTH-3:0] way_raddr[OPTION_ICACHE_WAYS-1:0];
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wire [WAY_WIDTH-3:0] way_waddr[OPTION_ICACHE_WAYS-1:0];
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wire [OPTION_OPERAND_WIDTH-1:0] way_din[OPTION_ICACHE_WAYS-1:0];
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wire [OPTION_OPERAND_WIDTH-1:0] way_dout[OPTION_ICACHE_WAYS-1:0];
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reg [OPTION_ICACHE_WAYS-1:0] way_we;
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// Does any way hit?
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wire hit;
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wire [OPTION_ICACHE_WAYS-1:0] way_hit;
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// This is the least recently used value before access the memory.
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// Those are one hot encoded.
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wire [OPTION_ICACHE_WAYS-1:0] lru;
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// Register that stores the LRU value from lru
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reg [OPTION_ICACHE_WAYS-1:0] tag_save_lru;
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// The access vector to update the LRU history is the way that has
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// a hit or is refilled. It is also one-hot encoded.
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reg [OPTION_ICACHE_WAYS-1:0] access;
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// The current LRU history as read from tag memory and the update
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// value after we accessed it to write back to tag memory.
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wire [TAG_LRU_WIDTH_BITS-1:0] current_lru_history;
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wire [TAG_LRU_WIDTH_BITS-1:0] next_lru_history;
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// Intermediate signals to ease debugging
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wire [TAG_WIDTH-1:0] check_way_tag [OPTION_ICACHE_WAYS-1:0];
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wire check_way_match [OPTION_ICACHE_WAYS-1:0];
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wire check_way_valid [OPTION_ICACHE_WAYS-1:0];
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genvar i;
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// Allowing (out of the cache line being refilled) accesses during refill
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// exposes a bug somewhere, causing the Linux kernel to end up with a
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// bus error UNHANDLED EXCEPTION.
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// Until that is sorted out, disable it.
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assign cpu_ack_o = (read /*| refill & ic_access_i*/) & hit |
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refill_hit & ic_access_i;
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assign tag_rindex = cpu_adr_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH];
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/*
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* The tag mem is written during reads to write the lru info and during
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* refill and invalidate
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*/
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assign tag_windex = read ?
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cpu_adr_match_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH] :
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invalidate ? invalidate_adr :
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wradr_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH];
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assign tag_tag = cpu_adr_match_i[OPTION_ICACHE_LIMIT_WIDTH-1:WAY_WIDTH];
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assign tag_wtag = wradr_i[OPTION_ICACHE_LIMIT_WIDTH-1:WAY_WIDTH];
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generate
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if (OPTION_ICACHE_WAYS >= 2) begin
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// Multiplex the LRU history from and to tag memory
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assign current_lru_history = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB];
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assign tag_din[TAG_LRU_MSB:TAG_LRU_LSB] = tag_lru_in;
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assign tag_lru_out = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB];
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end
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for (i = 0; i < OPTION_ICACHE_WAYS; i=i+1) begin : ways
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assign way_raddr[i] = cpu_adr_i[WAY_WIDTH-1:2];
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assign way_waddr[i] = wradr_i[WAY_WIDTH-1:2];
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assign way_din[i] = wrdat_i;
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// compare stored tag with incoming tag and check valid bit
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assign check_way_tag[i] = tag_way_out[i][TAG_WIDTH-1:0];
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assign check_way_match[i] = (check_way_tag[i] == tag_tag);
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assign check_way_valid[i] = tag_way_out[i][TAGMEM_WAY_VALID];
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assign way_hit[i] = check_way_valid[i] & check_way_match[i];
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// Multiplex the way entries in the tag memory
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assign tag_din[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH] = tag_way_in[i];
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assign tag_way_out[i] = tag_dout[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH];
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end
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endgenerate
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assign hit = |way_hit;
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integer w0;
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always @(*) begin
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cpu_dat_o = {OPTION_OPERAND_WIDTH{1'bx}};
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// Put correct way on the data port
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for (w0 = 0; w0 < OPTION_ICACHE_WAYS; w0 = w0 + 1) begin
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if (way_hit[w0] | (refill_hit & tag_save_lru[w0])) begin
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cpu_dat_o = way_dout[w0];
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end
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end
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end
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assign next_refill_adr = (OPTION_ICACHE_BLOCK_WIDTH == 5) ?
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{wradr_i[31:5], wradr_i[4:0] + 5'd4} : // 32 byte
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{wradr_i[31:4], wradr_i[3:0] + 4'd4}; // 16 byte
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assign refill_done_o = refill_done;
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assign refill_done = refill_valid[next_refill_adr[OPTION_ICACHE_BLOCK_WIDTH-1:2]];
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assign refill_hit = refill_valid_r[cpu_adr_match_i[OPTION_ICACHE_BLOCK_WIDTH-1:2]] &
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cpu_adr_match_i[OPTION_ICACHE_LIMIT_WIDTH-1:
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OPTION_ICACHE_BLOCK_WIDTH] ==
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wradr_i[OPTION_ICACHE_LIMIT_WIDTH-1:
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OPTION_ICACHE_BLOCK_WIDTH] &
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refill;
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assign idle = (state == IDLE);
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assign refill = (state == REFILL);
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assign read = (state == READ);
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assign invalidate = (state == INVALIDATE);
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assign refill_o = refill;
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assign refill_req_o = read & cpu_req_i & !hit | refill;
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/*
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* SPR bus interface
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*/
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assign invalidate_o = spr_bus_stb_i & spr_bus_we_i &
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(spr_bus_addr_i == `OR1K_SPR_ICBIR_ADDR);
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/*
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* Cache FSM
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*/
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integer w1;
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always @(posedge clk `OR_ASYNC_RST) begin
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refill_valid_r <= refill_valid;
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spr_bus_ack_o <= 0;
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case (state)
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IDLE: begin
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if (cpu_req_i)
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state <= READ;
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end
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READ: begin
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if (ic_access_i) begin
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if (hit) begin
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state <= READ;
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end else if (cpu_req_i) begin
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refill_valid <= 0;
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refill_valid_r <= 0;
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// Store the LRU information for correct replacement
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// on refill. Always one when only one way.
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tag_save_lru <= (OPTION_ICACHE_WAYS==1) | lru;
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for (w1 = 0; w1 < OPTION_ICACHE_WAYS; w1 = w1 + 1) begin
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tag_way_save[w1] <= tag_way_out[w1];
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end
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state <= REFILL;
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end
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end else begin
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state <= IDLE;
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end
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end
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REFILL: begin
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if (we_i) begin
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refill_valid[wradr_i[OPTION_ICACHE_BLOCK_WIDTH-1:2]] <= 1;
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if (refill_done)
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state <= IDLE;
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end
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end
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INVALIDATE: begin
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if (!invalidate_o)
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state <= IDLE;
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spr_bus_ack_o <= 1;
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end
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default:
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state <= IDLE;
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endcase
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if (invalidate_o & !refill) begin
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invalidate_adr <= spr_bus_dat_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH];
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spr_bus_ack_o <= 1;
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state <= INVALIDATE;
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end
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if (rst)
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state <= IDLE;
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end
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integer w2;
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always @(*) begin
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// Default is to keep data, don't write and don't access
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tag_lru_in = tag_lru_out;
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for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin
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326 |
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|
tag_way_in[w2] = tag_way_out[w2];
|
327 |
|
|
end
|
328 |
|
|
|
329 |
|
|
tag_we = 1'b0;
|
330 |
|
|
way_we = {(OPTION_ICACHE_WAYS){1'b0}};
|
331 |
|
|
|
332 |
|
|
access = {(OPTION_ICACHE_WAYS){1'b0}};
|
333 |
|
|
|
334 |
|
|
case (state)
|
335 |
|
|
READ: begin
|
336 |
|
|
if (hit) begin
|
337 |
|
|
// We got a hit. The LRU module gets the access
|
338 |
|
|
// information. Depending on this we update the LRU
|
339 |
|
|
// history in the tag.
|
340 |
|
|
access = way_hit;
|
341 |
|
|
|
342 |
|
|
// This is the updated LRU history after hit
|
343 |
|
|
tag_lru_in = next_lru_history;
|
344 |
|
|
|
345 |
|
|
tag_we = 1'b1;
|
346 |
|
|
end
|
347 |
|
|
end
|
348 |
|
|
|
349 |
|
|
REFILL: begin
|
350 |
|
|
if (we_i) begin
|
351 |
|
|
// Write the data to the way that is replaced (which is
|
352 |
|
|
// the LRU)
|
353 |
|
|
way_we = tag_save_lru;
|
354 |
|
|
|
355 |
|
|
// Access pattern
|
356 |
|
|
access = tag_save_lru;
|
357 |
|
|
|
358 |
|
|
/* Invalidate the way on the first write */
|
359 |
|
|
if (refill_valid == 0) begin
|
360 |
|
|
for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin
|
361 |
|
|
if (tag_save_lru[w2]) begin
|
362 |
|
|
tag_way_in[w2][TAGMEM_WAY_VALID] = 1'b0;
|
363 |
|
|
end
|
364 |
|
|
end
|
365 |
|
|
|
366 |
|
|
tag_we = 1'b1;
|
367 |
|
|
end
|
368 |
|
|
|
369 |
|
|
// After refill update the tag memory entry of the
|
370 |
|
|
// filled way with the LRU history, the tag and set
|
371 |
|
|
// valid to 1.
|
372 |
|
|
if (refill_done) begin
|
373 |
|
|
for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin
|
374 |
|
|
tag_way_in[w2] = tag_way_save[w2];
|
375 |
|
|
if (tag_save_lru[w2]) begin
|
376 |
|
|
tag_way_in[w2] = { 1'b1, tag_wtag };
|
377 |
|
|
end
|
378 |
|
|
end
|
379 |
|
|
tag_lru_in = next_lru_history;
|
380 |
|
|
|
381 |
|
|
tag_we = 1'b1;
|
382 |
|
|
end
|
383 |
|
|
end
|
384 |
|
|
end
|
385 |
|
|
|
386 |
|
|
INVALIDATE: begin
|
387 |
|
|
// Lazy invalidation, invalidate everything that matches tag address
|
388 |
|
|
tag_lru_in = 0;
|
389 |
|
|
for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin
|
390 |
|
|
tag_way_in[w2] = 0;
|
391 |
|
|
end
|
392 |
|
|
|
393 |
|
|
tag_we = 1'b1;
|
394 |
|
|
end
|
395 |
|
|
|
396 |
|
|
default: begin
|
397 |
|
|
end
|
398 |
|
|
endcase
|
399 |
|
|
end
|
400 |
|
|
|
401 |
|
|
/* mor1kx_simple_dpram_sclk AUTO_TEMPLATE (
|
402 |
|
|
// Outputs
|
403 |
|
|
.dout (way_dout[i][OPTION_OPERAND_WIDTH-1:0]),
|
404 |
|
|
// Inputs
|
405 |
|
|
.raddr (way_raddr[i][WAY_WIDTH-3:0]),
|
406 |
|
|
.re (1'b1),
|
407 |
|
|
.waddr (way_waddr[i][WAY_WIDTH-3:0]),
|
408 |
|
|
.we (way_we[i]),
|
409 |
|
|
.din (way_din[i][31:0]));
|
410 |
|
|
*/
|
411 |
|
|
generate
|
412 |
|
|
for (i = 0; i < OPTION_ICACHE_WAYS; i=i+1) begin : way_memories
|
413 |
|
|
mor1kx_simple_dpram_sclk
|
414 |
|
|
#(
|
415 |
|
|
.ADDR_WIDTH(WAY_WIDTH-2),
|
416 |
|
|
.DATA_WIDTH(OPTION_OPERAND_WIDTH),
|
417 |
|
|
.ENABLE_BYPASS(0)
|
418 |
|
|
)
|
419 |
|
|
way_data_ram
|
420 |
|
|
(/*AUTOINST*/
|
421 |
|
|
// Outputs
|
422 |
|
|
.dout (way_dout[i][OPTION_OPERAND_WIDTH-1:0]), // Templated
|
423 |
|
|
// Inputs
|
424 |
|
|
.clk (clk),
|
425 |
|
|
.raddr (way_raddr[i][WAY_WIDTH-3:0]), // Templated
|
426 |
|
|
.re (1'b1), // Templated
|
427 |
|
|
.waddr (way_waddr[i][WAY_WIDTH-3:0]), // Templated
|
428 |
|
|
.we (way_we[i]), // Templated
|
429 |
|
|
.din (way_din[i][31:0])); // Templated
|
430 |
|
|
|
431 |
|
|
end // block: way_memories
|
432 |
|
|
|
433 |
|
|
if (OPTION_ICACHE_WAYS >= 2) begin : gen_u_lru
|
434 |
|
|
/* mor1kx_cache_lru AUTO_TEMPLATE(
|
435 |
|
|
.current (current_lru_history),
|
436 |
|
|
.update (next_lru_history),
|
437 |
|
|
.lru_pre (lru),
|
438 |
|
|
.lru_post (),
|
439 |
|
|
.access (access),
|
440 |
|
|
); */
|
441 |
|
|
|
442 |
|
|
mor1kx_cache_lru
|
443 |
|
|
#(.NUMWAYS(OPTION_ICACHE_WAYS))
|
444 |
|
|
u_lru(/*AUTOINST*/
|
445 |
|
|
// Outputs
|
446 |
|
|
.update (next_lru_history), // Templated
|
447 |
|
|
.lru_pre (lru), // Templated
|
448 |
|
|
.lru_post (), // Templated
|
449 |
|
|
// Inputs
|
450 |
|
|
.current (current_lru_history), // Templated
|
451 |
|
|
.access (access)); // Templated
|
452 |
|
|
end // if (OPTION_ICACHE_WAYS >= 2)
|
453 |
|
|
endgenerate
|
454 |
|
|
|
455 |
|
|
/* mor1kx_simple_dpram_sclk AUTO_TEMPLATE (
|
456 |
|
|
// Outputs
|
457 |
|
|
.dout (tag_dout[TAGMEM_WIDTH-1:0]),
|
458 |
|
|
// Inputs
|
459 |
|
|
.raddr (tag_rindex),
|
460 |
|
|
.re (1'b1),
|
461 |
|
|
.waddr (tag_windex),
|
462 |
|
|
.we (tag_we),
|
463 |
|
|
.din (tag_din));
|
464 |
|
|
*/
|
465 |
|
|
mor1kx_simple_dpram_sclk
|
466 |
|
|
#(
|
467 |
|
|
.ADDR_WIDTH(OPTION_ICACHE_SET_WIDTH),
|
468 |
|
|
.DATA_WIDTH(TAGMEM_WIDTH),
|
469 |
|
|
.ENABLE_BYPASS(0)
|
470 |
|
|
)
|
471 |
|
|
tag_ram
|
472 |
|
|
(/*AUTOINST*/
|
473 |
|
|
// Outputs
|
474 |
|
|
.dout (tag_dout[TAGMEM_WIDTH-1:0]), // Templated
|
475 |
|
|
// Inputs
|
476 |
|
|
.clk (clk),
|
477 |
|
|
.raddr (tag_rindex), // Templated
|
478 |
|
|
.re (1'b1), // Templated
|
479 |
|
|
.waddr (tag_windex), // Templated
|
480 |
|
|
.we (tag_we), // Templated
|
481 |
|
|
.din (tag_din)); // Templated
|
482 |
|
|
|
483 |
|
|
endmodule
|