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/******************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: Instruction MMU implementation
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Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
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******************************************************************************/
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`include "mor1kx-defines.v"
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module mor1kx_immu
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#(
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parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE",
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parameter OPTION_OPERAND_WIDTH = 32,
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parameter OPTION_IMMU_SET_WIDTH = 6,
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parameter OPTION_IMMU_WAYS = 1
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)
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(
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input clk,
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input rst,
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input enable_i,
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output busy_o,
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input [OPTION_OPERAND_WIDTH-1:0] virt_addr_i,
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input [OPTION_OPERAND_WIDTH-1:0] virt_addr_match_i,
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output [OPTION_OPERAND_WIDTH-1:0] phys_addr_o,
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output cache_inhibit_o,
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input supervisor_mode_i,
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output tlb_miss_o,
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output pagefault_o,
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output reg tlb_reload_req_o,
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input tlb_reload_ack_i,
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output reg [OPTION_OPERAND_WIDTH-1:0] tlb_reload_addr_o,
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input [OPTION_OPERAND_WIDTH-1:0] tlb_reload_data_i,
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output tlb_reload_pagefault_o,
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input tlb_reload_pagefault_clear_i,
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output tlb_reload_busy_o,
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// SPR interface
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input [15:0] spr_bus_addr_i,
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input spr_bus_we_i,
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input spr_bus_stb_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i,
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output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o,
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output spr_bus_ack_o
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);
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wire [OPTION_OPERAND_WIDTH-1:0] itlb_match_dout;
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wire [OPTION_IMMU_SET_WIDTH-1:0] itlb_match_addr;
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wire itlb_match_we;
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wire [OPTION_OPERAND_WIDTH-1:0] itlb_match_din;
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wire [OPTION_OPERAND_WIDTH-1:0] itlb_match_huge_dout;
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wire [OPTION_IMMU_SET_WIDTH-1:0] itlb_match_huge_addr;
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wire itlb_match_huge_we;
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wire [OPTION_OPERAND_WIDTH-1:0] itlb_trans_dout;
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wire [OPTION_IMMU_SET_WIDTH-1:0] itlb_trans_addr;
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wire itlb_trans_we;
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wire [OPTION_OPERAND_WIDTH-1:0] itlb_trans_din;
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wire [OPTION_OPERAND_WIDTH-1:0] itlb_trans_huge_dout;
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wire [OPTION_IMMU_SET_WIDTH-1:0] itlb_trans_huge_addr;
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wire itlb_trans_huge_we;
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reg itlb_match_reload_we;
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reg [OPTION_OPERAND_WIDTH-1:0] itlb_match_reload_din;
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reg itlb_trans_reload_we;
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reg [OPTION_OPERAND_WIDTH-1:0] itlb_trans_reload_din;
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wire itlb_match_spr_cs;
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reg itlb_match_spr_cs_r;
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wire itlb_trans_spr_cs;
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reg itlb_trans_spr_cs_r;
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wire immucr_spr_cs;
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reg immucr_spr_cs_r;
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reg [OPTION_OPERAND_WIDTH-1:0] immucr;
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wire tlb_huge;
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wire tlb_miss;
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wire tlb_huge_miss;
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reg tlb_reload_pagefault;
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reg tlb_reload_huge;
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// sxe: supervisor execute enable
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// uxe: user exexute enable
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wire sxe;
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wire uxe;
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reg spr_bus_ack;
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reg spr_bus_ack_r;
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wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat;
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reg [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_r;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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spr_bus_ack <= 0;
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else if (spr_bus_stb_i & spr_bus_addr_i[15:11] == 5'd2)
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spr_bus_ack <= 1;
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else
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spr_bus_ack <= 0;
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always @(posedge clk)
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spr_bus_ack_r <= spr_bus_ack;
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always @(posedge clk)
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if (spr_bus_ack & !spr_bus_ack_r)
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spr_bus_dat_r <= spr_bus_dat;
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assign spr_bus_ack_o = spr_bus_ack & spr_bus_stb_i &
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spr_bus_addr_i[15:11] == 5'd2;
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assign cache_inhibit_o = tlb_huge ? itlb_trans_huge_dout[1] :
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itlb_trans_dout[1];
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assign sxe = tlb_huge ? itlb_trans_huge_dout[6] : itlb_trans_dout[6];
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assign uxe = tlb_huge ? itlb_trans_huge_dout[7] : itlb_trans_dout[7];
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assign pagefault_o = (supervisor_mode_i ? !sxe : !uxe) &
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!tlb_reload_busy_o & !busy_o;
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assign busy_o = ((itlb_match_spr_cs | itlb_trans_spr_cs) & !spr_bus_ack |
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(itlb_match_spr_cs_r | itlb_trans_spr_cs_r) &
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spr_bus_ack & !spr_bus_ack_r) & enable_i;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst) begin
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itlb_match_spr_cs_r <= 0;
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itlb_trans_spr_cs_r <= 0;
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immucr_spr_cs_r <= 0;
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end else begin
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itlb_match_spr_cs_r <= itlb_match_spr_cs;
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itlb_trans_spr_cs_r <= itlb_trans_spr_cs;
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immucr_spr_cs_r <= immucr_spr_cs;
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end
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generate /* verilator lint_off WIDTH */
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if (FEATURE_IMMU_HW_TLB_RELOAD == "ENABLED") begin
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/* verilator lint_on WIDTH */
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assign immucr_spr_cs = spr_bus_stb_i &
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spr_bus_addr_i == `OR1K_SPR_IMMUCR_ADDR;
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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immucr <= 0;
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else if (immucr_spr_cs & spr_bus_we_i)
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immucr <= spr_bus_dat_i;
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end else begin
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assign immucr_spr_cs = 0;
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always @(posedge clk)
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immucr <= 0;
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end
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endgenerate
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// TODO: optimize this
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assign itlb_match_spr_cs = spr_bus_stb_i &
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(spr_bus_addr_i >= `OR1K_SPR_ITLBW0MR0_ADDR) &
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(spr_bus_addr_i < `OR1K_SPR_ITLBW0TR0_ADDR);
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assign itlb_trans_spr_cs = spr_bus_stb_i &
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(spr_bus_addr_i >= `OR1K_SPR_ITLBW0TR0_ADDR) &
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(spr_bus_addr_i < `OR1K_SPR_ITLBW1MR0_ADDR);
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assign itlb_match_addr = itlb_match_spr_cs & !spr_bus_ack ?
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spr_bus_addr_i[OPTION_IMMU_SET_WIDTH-1:0] :
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virt_addr_i[13+(OPTION_IMMU_SET_WIDTH-1):13];
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assign itlb_trans_addr = itlb_trans_spr_cs & !spr_bus_ack ?
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spr_bus_addr_i[OPTION_IMMU_SET_WIDTH-1:0] :
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virt_addr_i[13+(OPTION_IMMU_SET_WIDTH-1):13];
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assign itlb_match_we = itlb_match_spr_cs & spr_bus_we_i & !spr_bus_ack |
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itlb_match_reload_we & !tlb_reload_huge;
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assign itlb_trans_we = itlb_trans_spr_cs & spr_bus_we_i & !spr_bus_ack |
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itlb_trans_reload_we & !tlb_reload_huge;
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assign itlb_match_din = itlb_match_spr_cs & spr_bus_we_i & !spr_bus_ack ?
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spr_bus_dat_i : itlb_match_reload_din;
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assign itlb_trans_din = itlb_trans_spr_cs & spr_bus_we_i & !spr_bus_ack ?
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spr_bus_dat_i : itlb_trans_reload_din;
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assign itlb_match_huge_addr = virt_addr_i[24+(OPTION_IMMU_SET_WIDTH-1):24];
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assign itlb_trans_huge_addr = virt_addr_i[24+(OPTION_IMMU_SET_WIDTH-1):24];
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assign itlb_match_huge_we = itlb_match_reload_we & tlb_reload_huge;
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assign itlb_trans_huge_we = itlb_trans_reload_we & tlb_reload_huge;
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assign spr_bus_dat = itlb_match_spr_cs_r ? itlb_match_dout :
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itlb_trans_spr_cs_r ? itlb_trans_dout :
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immucr_spr_cs_r ? immucr : 0;
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// Use registered value on all but the first cycle spr_bus_ack is asserted
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assign spr_bus_dat_o = spr_bus_ack & !spr_bus_ack_r ? spr_bus_dat :
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spr_bus_dat_r;
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assign tlb_huge = &itlb_match_huge_dout[1:0]; // huge & valid
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assign tlb_miss = itlb_match_dout[31:13] != virt_addr_match_i[31:13] |
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!itlb_match_dout[0]; // valid bit
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assign tlb_huge_miss = itlb_match_huge_dout[31:24] !=
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virt_addr_match_i[31:24] | !itlb_match_huge_dout[0];
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assign tlb_miss_o = (tlb_miss & !tlb_huge | tlb_huge_miss & tlb_huge) &
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!tlb_reload_pagefault & !busy_o;
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assign phys_addr_o = tlb_huge ?
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{itlb_trans_huge_dout[31:24], virt_addr_match_i[23:0]} :
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{itlb_trans_dout[31:13], virt_addr_match_i[12:0]};
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generate /* verilator lint_off WIDTH */
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if (FEATURE_IMMU_HW_TLB_RELOAD == "ENABLED") begin
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/* verilator lint_on WIDTH */
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// Hardware TLB reload
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// Compliant with the suggestions outlined in this thread:
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// http://lists.openrisc.net/pipermail/openrisc/2013-July/001806.html
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//
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// PTE layout:
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// | 31 ... 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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// | PPN | Reserved |PRESENT| L | X | W | U | D | A |WOM|WBC|CI |CC |
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//
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// Where X/W/U maps into SXE/UXE like this:
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// X | W | U SXE | UXE
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// --------- ---------
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// 0 | x | 0 = 0 | 0
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// 0 | x | 1 = 0 | 0
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// ...
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// 1 | x | 0 = 1 | 0
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// 1 | x | 1 = 1 | 1
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localparam TLB_IDLE = 2'd0;
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localparam TLB_GET_PTE_POINTER = 2'd1;
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localparam TLB_GET_PTE = 2'd2;
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localparam TLB_READ = 2'd3;
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reg [1:0] tlb_reload_state = TLB_IDLE;
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wire do_reload;
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assign do_reload = enable_i & tlb_miss_o & (immucr[31:10] != 0);
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assign tlb_reload_busy_o = (tlb_reload_state != TLB_IDLE) | do_reload;
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assign tlb_reload_pagefault_o = tlb_reload_pagefault &
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!tlb_reload_pagefault_clear_i;
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always @(posedge clk) begin
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if (tlb_reload_pagefault_clear_i | rst)
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tlb_reload_pagefault <= 0;
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itlb_trans_reload_we <= 0;
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itlb_trans_reload_din <= 0;
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itlb_match_reload_we <= 0;
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itlb_match_reload_din <= 0;
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case (tlb_reload_state)
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TLB_IDLE: begin
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tlb_reload_huge <= 0;
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tlb_reload_req_o <= 0;
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if (do_reload) begin
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tlb_reload_req_o <= 1;
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tlb_reload_addr_o <= {immucr[31:10],
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virt_addr_match_i[31:24], 2'b00};
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tlb_reload_state <= TLB_GET_PTE_POINTER;
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end
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end
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//
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// Here we get the pointer to the PTE table, next is to fetch
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// the actual pte from the offset in the table.
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// The offset is calculated by:
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// ((virt_addr_match >> PAGE_BITS) & (PTE_CNT-1)) << 2
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// Where PAGE_BITS is 13 (8 kb page) and PTE_CNT is 2048
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// (number of PTEs in the PTE table)
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//
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TLB_GET_PTE_POINTER: begin
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tlb_reload_huge <= 0;
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if (tlb_reload_ack_i) begin
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if (tlb_reload_data_i[31:13] == 0) begin
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tlb_reload_pagefault <= 1;
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tlb_reload_req_o <= 0;
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tlb_reload_state <= TLB_IDLE;
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end else if (tlb_reload_data_i[9]) begin
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tlb_reload_huge <= 1;
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tlb_reload_req_o <= 0;
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tlb_reload_state <= TLB_GET_PTE;
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end else begin
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tlb_reload_addr_o <= {tlb_reload_data_i[31:13],
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virt_addr_match_i[23:13], 2'b00};
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tlb_reload_state <= TLB_GET_PTE;
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end
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end
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end
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//
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// Here we get the actual PTE, left to do is to translate the
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// PTE data into our translate and match registers.
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//
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TLB_GET_PTE: begin
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if (tlb_reload_ack_i) begin
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tlb_reload_req_o <= 0;
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// Check PRESENT bit
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|
|
if (!tlb_reload_data_i[10]) begin
|
313 |
|
|
tlb_reload_pagefault <= 1;
|
314 |
|
|
tlb_reload_state <= TLB_IDLE;
|
315 |
|
|
end else begin
|
316 |
|
|
// Translate register generation.
|
317 |
|
|
// PPN
|
318 |
|
|
itlb_trans_reload_din[31:13] <= tlb_reload_data_i[31:13];
|
319 |
|
|
// UXE = X & U
|
320 |
|
|
itlb_trans_reload_din[7] <= tlb_reload_data_i[8] &
|
321 |
|
|
tlb_reload_data_i[6];
|
322 |
|
|
// SXE = X
|
323 |
|
|
itlb_trans_reload_din[6] <= tlb_reload_data_i[8];
|
324 |
|
|
// Dirty, Accessed, Weakly-Ordered-Memory, Writeback cache,
|
325 |
|
|
// Cache inhibit, Cache coherent
|
326 |
|
|
itlb_trans_reload_din[5:0] <= tlb_reload_data_i[5:0];
|
327 |
|
|
itlb_trans_reload_we <= 1;
|
328 |
|
|
|
329 |
|
|
// Match register generation.
|
330 |
|
|
// VPN
|
331 |
|
|
itlb_match_reload_din[31:13] <= virt_addr_match_i[31:13];
|
332 |
|
|
// PL1
|
333 |
|
|
itlb_match_reload_din[1] <= tlb_reload_huge;
|
334 |
|
|
// Valid
|
335 |
|
|
itlb_match_reload_din[0] <= 1;
|
336 |
|
|
itlb_match_reload_we <= 1;
|
337 |
|
|
|
338 |
|
|
tlb_reload_state <= TLB_READ;
|
339 |
|
|
end
|
340 |
|
|
end
|
341 |
|
|
end
|
342 |
|
|
|
343 |
|
|
// Let the just written values propagate out on the read ports
|
344 |
|
|
TLB_READ: begin
|
345 |
|
|
tlb_reload_state <= TLB_IDLE;
|
346 |
|
|
end
|
347 |
|
|
|
348 |
|
|
default:
|
349 |
|
|
tlb_reload_state <= TLB_IDLE;
|
350 |
|
|
|
351 |
|
|
endcase
|
352 |
|
|
end
|
353 |
|
|
end else begin // if (FEATURE_IMMU_HW_TLB_RELOAD == "ENABLED")
|
354 |
|
|
assign tlb_reload_pagefault_o = 0;
|
355 |
|
|
assign tlb_reload_busy_o = 0;
|
356 |
|
|
always @(posedge clk) begin
|
357 |
|
|
tlb_reload_req_o <= 0;
|
358 |
|
|
tlb_reload_addr_o <= 0;
|
359 |
|
|
tlb_reload_pagefault <= 0;
|
360 |
|
|
itlb_trans_reload_we <= 0;
|
361 |
|
|
itlb_trans_reload_din <= 0;
|
362 |
|
|
itlb_match_reload_we <= 0;
|
363 |
|
|
itlb_match_reload_din <= 0;
|
364 |
|
|
end
|
365 |
|
|
end
|
366 |
|
|
endgenerate
|
367 |
|
|
|
368 |
|
|
// ITLB match registers
|
369 |
|
|
mor1kx_true_dpram_sclk
|
370 |
|
|
#(
|
371 |
|
|
.ADDR_WIDTH(OPTION_IMMU_SET_WIDTH),
|
372 |
|
|
.DATA_WIDTH(OPTION_OPERAND_WIDTH)
|
373 |
|
|
)
|
374 |
|
|
itlb_match_regs
|
375 |
|
|
(
|
376 |
|
|
// Outputs
|
377 |
|
|
.dout_a (itlb_match_dout),
|
378 |
|
|
.dout_b (itlb_match_huge_dout),
|
379 |
|
|
// Inputs
|
380 |
|
|
.clk (clk),
|
381 |
|
|
.addr_a (itlb_match_addr),
|
382 |
|
|
.we_a (itlb_match_we),
|
383 |
|
|
.din_a (itlb_match_din),
|
384 |
|
|
.addr_b (itlb_match_huge_addr),
|
385 |
|
|
.we_b (itlb_match_huge_we),
|
386 |
|
|
.din_b (itlb_match_reload_din)
|
387 |
|
|
);
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
// ITLB translate registers
|
391 |
|
|
mor1kx_true_dpram_sclk
|
392 |
|
|
#(
|
393 |
|
|
.ADDR_WIDTH(OPTION_IMMU_SET_WIDTH),
|
394 |
|
|
.DATA_WIDTH(OPTION_OPERAND_WIDTH)
|
395 |
|
|
)
|
396 |
|
|
itlb_translate_regs
|
397 |
|
|
(
|
398 |
|
|
// Outputs
|
399 |
|
|
.dout_a (itlb_trans_dout),
|
400 |
|
|
.dout_b (itlb_trans_huge_dout),
|
401 |
|
|
// Inputs
|
402 |
|
|
.clk (clk),
|
403 |
|
|
.addr_a (itlb_trans_addr),
|
404 |
|
|
.we_a (itlb_trans_we),
|
405 |
|
|
.din_a (itlb_trans_din),
|
406 |
|
|
.addr_b (itlb_trans_huge_addr),
|
407 |
|
|
.we_b (itlb_trans_huge_we),
|
408 |
|
|
.din_b (itlb_trans_reload_din)
|
409 |
|
|
);
|
410 |
|
|
|
411 |
|
|
endmodule
|