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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [rtl/] [verilog/] [mor1kx_pic.v] - Blame information for rev 38

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1 38 alirezamon 
/* ****************************************************************************
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  This Source Code Form is subject to the terms of the
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  Open Hardware Description License, v. 1.0. If a copy
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  of the OHDL was not distributed with this file, You
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  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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  Description: mor1kx PIC
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  Copyright (C) 2012 Authors
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  Author(s): Julius Baxter <juliusbaxter@gmail.com>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_pic
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  (/*AUTOARG*/
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   // Outputs
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   spr_picmr_o, spr_picsr_o, spr_bus_ack, spr_dat_o,
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   // Inputs
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   clk, rst, irq_i, spr_access_i, spr_we_i, spr_addr_i, spr_dat_i
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   );
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   parameter OPTION_PIC_TRIGGER="LEVEL";
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   parameter OPTION_PIC_NMI_WIDTH = 0;
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   input clk;
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   input rst;
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   input [31:0] irq_i;
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   output [31:0] spr_picmr_o;
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   output [31:0] spr_picsr_o;
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   // SPR Bus interface
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   input         spr_access_i;
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   input         spr_we_i;
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   input [15:0]  spr_addr_i;
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   input [31:0]  spr_dat_i;
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   output        spr_bus_ack;
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   output [31:0] spr_dat_o;
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   // Registers
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   reg [31:0]    spr_picmr;
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   reg [31:0]    spr_picsr;
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   wire spr_picmr_access;
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   wire spr_picsr_access;
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   wire [31:0]   irq_unmasked;
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   assign spr_picmr_o = spr_picmr;
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   assign spr_picsr_o = spr_picsr;
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   assign spr_picmr_access =
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     spr_access_i &
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     (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PICMR_ADDR));
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   assign spr_picsr_access =
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     spr_access_i &
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     (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PICSR_ADDR));
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   assign spr_bus_ack = spr_access_i;
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   assign spr_dat_o =  (spr_access_i & spr_picsr_access) ? spr_picsr :
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                       (spr_access_i & spr_picmr_access) ? spr_picmr :
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                       0;
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   assign irq_unmasked = spr_picmr & irq_i;
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   generate
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      genvar     irqline;
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      if (OPTION_PIC_TRIGGER=="EDGE") begin : edge_triggered
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         for(irqline=0;irqline<32;irqline=irqline+1)
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           begin: picgenerate
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              // PIC status register
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              always @(posedge clk `OR_ASYNC_RST)
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                if (rst)
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                  spr_picsr[irqline] <= 0;
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              // Clear
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                else if (spr_we_i & spr_picsr_access)
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                  spr_picsr[irqline] <= spr_dat_i[irqline] ? 0 :
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                                               spr_picsr[irqline];
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              // Set
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                else if (!spr_picsr[irqline] & irq_unmasked[irqline])
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                  spr_picsr[irqline] <= 1;
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           end // block: picgenerate
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      end // if (OPTION_PIC_TRIGGER=="EDGE")
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      else if (OPTION_PIC_TRIGGER=="LEVEL") begin : level_triggered
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         for(irqline=0;irqline<32;irqline=irqline+1)
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           begin: picsrlevelgenerate
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              // PIC status register
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              always @(*)
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                spr_picsr[irqline] <= irq_unmasked[irqline];
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           end
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      end // if (OPTION_PIC_TRIGGER=="LEVEL")
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      else if (OPTION_PIC_TRIGGER=="LATCHED_LEVEL") begin : latched_level
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         for(irqline=0;irqline<32;irqline=irqline+1)
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           begin: piclatchedlevelgenerate
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              // PIC status register
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              always @(posedge clk `OR_ASYNC_RST)
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                if (rst)
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                  spr_picsr[irqline] <= 0;
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                else if (spr_we_i && spr_picsr_access)
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                  spr_picsr[irqline] <= irq_unmasked[irqline] |
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                                               spr_dat_i[irqline];
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                else
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                  spr_picsr[irqline] <= spr_picsr[irqline] |
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                                        irq_unmasked[irqline];
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           end // block: picgenerate
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      end // if (OPTION_PIC_TRIGGER=="EDGE")
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      else begin : invalid
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         initial begin
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            $display("Error - invalid PIC level detection option %s",
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                     OPTION_PIC_TRIGGER);
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            $finish;
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         end
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      end // else: !if(OPTION_PIC_TRIGGER=="LEVEL")
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   endgenerate
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   // PIC (un)mask register
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   always @(posedge clk `OR_ASYNC_RST)
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     if (rst)
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       spr_picmr <= {{(32-OPTION_PIC_NMI_WIDTH){1'b0}},
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                     {OPTION_PIC_NMI_WIDTH{1'b1}}};
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     else if (spr_we_i && spr_picmr_access)
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       spr_picmr <= {spr_dat_i[31:OPTION_PIC_NMI_WIDTH],
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                     {OPTION_PIC_NMI_WIDTH{1'b1}}};
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endmodule // mor1kx_pic

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