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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [sw/] [mor1kx/] [crt0.S] - Blame information for rev 38

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Line No. Rev Author Line
1 38 alirezamon 
#include
2 
#include
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#include "spr-defs.h"
4 
#include "board.h"
5 
 
6 
/* ======================================================= [ macros ] === */
7 
 
8 
#define REDZONE 128
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#define EXCEPTION_STACK_SIZE (128 + 8 + REDZONE)
10 
 
11 
#define CLEAR_GPR(gpr) \
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        l.or    gpr, r0, r0
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14 
#define ENTRY(symbol)    \
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        .global symbol ; \
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symbol:
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18 
#define LOAD_SYMBOL_2_GPR(gpr,symbol)  \
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        .global symbol ;               \
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        l.movhi gpr, hi(symbol) ;      \
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        l.ori   gpr, gpr, lo(symbol)
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23 
        // Really goes to configurable interrupt handler
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#define EXCEPTION_HANDLER            \
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        l.addi  r1, r1, -EXCEPTION_STACK_SIZE;          \
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        l.sw    4(r1), r3;             \
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        l.sw    8(r1), r4;             \
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        l.mfspr r3,r0,SPR_NPC;          \
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        l.mfspr r4,r0,SPR_EPCR_BASE;   \
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        OR1K_DELAYED_NOP(OR1K_INST(l.j default_exception_handler))
31 
 
32 
/* =================================================== [ exceptions ] === */
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        .section .vectors, "ax"
34 
 
35 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
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        .org 0x100
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        l.movhi r0, 0
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        l.movhi r1, 0
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        l.movhi r2, 0
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        l.movhi r3, 0
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        l.movhi r4, 0
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        l.movhi r5, 0
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        l.movhi r6, 0
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        l.movhi r7, 0
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        l.movhi r8, 0
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        l.movhi r9, 0
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        l.movhi r10, 0
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        l.movhi r11, 0
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        l.movhi r12, 0
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        l.movhi r13, 0
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        l.movhi r14, 0
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        l.movhi r15, 0
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        l.movhi r16, 0
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        l.movhi r17, 0
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        l.movhi r18, 0
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        l.movhi r19, 0
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        l.movhi r20, 0
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        l.movhi r21, 0
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        l.movhi r22, 0
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        l.movhi r23, 0
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        l.movhi r24, 0
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        l.movhi r25, 0
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        l.movhi r26, 0
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        l.movhi r27, 0
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        l.movhi r28, 0
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        l.movhi r29, 0
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        l.movhi r30, 0
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        l.movhi r31, 0
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70 
        /* Clear status register, set supervisor mode */
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        l.ori r1, r0, SPR_SR_SM
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        l.mtspr r0, r1, SPR_SR
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        /* Clear timer  */
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        l.mtspr r0, r0, SPR_TTMR
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        /* Early Stack initilization */
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        LOAD_SYMBOL_2_GPR(r1, _stack)
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        l.addi  r2, r0, -3
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        l.and   r1, r1, r2
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80 
        /* Jump to program initialisation code */
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        LOAD_SYMBOL_2_GPR(r4, _start)
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        OR1K_DELAYED_NOP(OR1K_INST(l.jr    r4))
83 
 
84 
/* ---[ 0x200: BUS exception ]------------------------------------------- */
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        .org 0x200
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        EXCEPTION_HANDLER
87 
 
88 
/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
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        .org 0x300
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        EXCEPTION_HANDLER
91 
 
92 
/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
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        .org 0x400
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        EXCEPTION_HANDLER
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96 
/* ---[ 0x500: Timer exception ]----------------------------------------- */
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        .org 0x500
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        EXCEPTION_HANDLER
99 
 
100 
/* ---[ 0x600: Aligment exception ]-------------------------------------- */
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        .org 0x600
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        EXCEPTION_HANDLER
103 
 
104 
/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
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        .org 0x700
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        EXCEPTION_HANDLER
107 
 
108 
/* ---[ 0x800: External interrupt exception ]---------------------------- */
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        .org 0x800
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        EXCEPTION_HANDLER
111 
 
112 
/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
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        .org 0x900
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        EXCEPTION_HANDLER
115 
 
116 
/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
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        .org 0xa00
118 
        EXCEPTION_HANDLER
119 
 
120 
/* ---[ 0xb00: Range exception ]----------------------------------------- */
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        .org 0xb00
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        EXCEPTION_HANDLER
123 
 
124 
/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
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        .org 0xc00
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        EXCEPTION_HANDLER
127 
 
128 
/* ---[ 0xd00: FPU exception ]------------------------------------------- */
129 
        .org 0xd00
130 
        EXCEPTION_HANDLER
131 
 
132 
/* ---[ 0xe00: Trap exception ]------------------------------------------ */
133 
        .org 0xe00
134 
        EXCEPTION_HANDLER
135 
 
136 
/* ---[ 0xf00 - 0x1400: Reserved exceptions ]---------------------------- */
137 
/*
138 
        .org 0xf00
139 
        EXCEPTION_HANDLER
140 
 
141 
        .org 0x1000
142 
        EXCEPTION_HANDLER
143 
 
144 
        .org 0x1100
145 
        EXCEPTION_HANDLER
146 
 
147 
        .org 0x1200
148 
        EXCEPTION_HANDLER
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150 
        .org 0x1300
151 
        EXCEPTION_HANDLER
152 
 
153 
        .org 0x1400
154 
        EXCEPTION_HANDLER
155 
 
156 
*/
157 
/* ---[ 0x1500 - 0x1800: Implementation-specific exceptions ]------------ */
158 
/*
159 
        .org 0x1500
160 
        EXCEPTION_HANDLER
161 
 
162 
        .org 0x1600
163 
        EXCEPTION_HANDLER
164 
 
165 
        .org 0x1700
166 
        EXCEPTION_HANDLER
167 
 
168 
        .org 0x1800
169 
        EXCEPTION_HANDLER
170 
*/
171 
/* ---[ 0x1500 - 0x1F00: Custom exceptions ]----------------------------- */
172 
/*
173 
        .org 0x1900
174 
        EXCEPTION_HANDLER
175 
 
176 
        .org 0x1a00
177 
        EXCEPTION_HANDLER
178 
 
179 
        .org 0x1b00
180 
        EXCEPTION_HANDLER
181 
 
182 
        .org 0x1c00
183 
        EXCEPTION_HANDLER
184 
 
185 
        .org 0x1d00
186 
        EXCEPTION_HANDLER
187 
 
188 
        .org 0x1e00
189 
        EXCEPTION_HANDLER
190 
 
191 
        .org 0x1f00
192 
        EXCEPTION_HANDLER
193 
*/
194 
 
195 
/* ========================================================= [ entry ] === */
196 
        .section .text
197 
 
198 
ENTRY(_start)
199 
 
200 
        /* Cache initialisation */
201 
        l.jal _cache_init
202 
        l.nop
203 
 
204 
        /* Clear BSS */
205 
        LOAD_SYMBOL_2_GPR(r5, _bss_start)
206 
        LOAD_SYMBOL_2_GPR(r6, _bss_end)
207 
1:
208 
        l.sw    (0)(r5), r0
209 
        l.sfltu r5, r6
210 
        OR1K_DELAYED(
211 
        OR1K_INST(l.addi  r5, r5, 4),
212 
        OR1K_INST(l.bf    1b)
213 
        )
214 
 
215 
        /* Jump to main program entry point (argc = argv = 0) */
216 
        CLEAR_GPR(r3)
217 
        CLEAR_GPR(r4)
218 
        /* nop to reset cycle counter */
219 
        l.nop   NOP_CNT_RESET
220 
        OR1K_DELAYED_NOP(OR1K_INST(l.jal   main))
221 
 
222 
        /* If program exits, call exit routine */
223 
        /* Save r11 */
224 
        l.or    r4,r11,r11
225 
        /* l.nop 0x6 moves the simulator cycle count to regs 11,12 */
226 
        /* Put some nops around this op so that the RF isn't
227 
        doing anything else when we write to it it */
228 
        l.nop
229 
        l.nop
230 
        l.nop   NOP_GET_TICKS
231 
        l.nop
232 
        l.nop
233 
        /* report upper 32-bits first */
234 
        l.or    r3,r12,r12
235 
        l.nop   NOP_REPORT
236 
        l.or    r3, r11,r11
237 
        l.nop   NOP_REPORT
238 
        l.addi  r3, r4, 0
239 
        OR1K_DELAYED_NOP(OR1K_INST(l.jal   exit))
240 
 
241 
 
242 
/* ====================================== [ default exception handler ] === */
243 
 
244 
default_exception_handler:
245 
        l.sw    0x00(r1), r2
246 
        l.sw    0x0c(r1), r5
247 
        l.sw    0x10(r1), r6
248 
        l.sw    0x14(r1), r7
249 
        l.sw    0x18(r1), r8
250 
        l.sw    0x1c(r1), r9
251 
        l.sw    0x20(r1), r10
252 
        l.sw    0x24(r1), r11
253 
        l.sw    0x28(r1), r12
254 
        l.sw    0x2c(r1), r13
255 
        l.sw    0x30(r1), r14
256 
        l.sw    0x34(r1), r15
257 
        l.sw    0x38(r1), r16
258 
        l.sw    0x3c(r1), r17
259 
        l.sw    0x40(r1), r18
260 
        l.sw    0x44(r1), r19
261 
        l.sw    0x48(r1), r20
262 
        l.sw    0x4c(r1), r21
263 
        l.sw    0x50(r1), r22
264 
        l.sw    0x54(r1), r23
265 
        l.sw    0x58(r1), r24
266 
        l.sw    0x5c(r1), r25
267 
        l.sw    0x60(r1), r26
268 
        l.sw    0x64(r1), r27
269 
        l.sw    0x68(r1), r28
270 
        l.sw    0x6c(r1), r29
271 
        l.sw    0x70(r1), r30
272 
        l.sw    0x74(r1), r31
273 
        l.sw    0x78(r1), r4 /* EPCR */
274 
        l.mfspr r5,r0,SPR_ESR_BASE
275 
        l.sw    0x7c(r1), r5 /* ESR */
276 
 
277 
        l.ori   r6, r1, 0 /* Pass exception stack pointer as arg 4*/
278 
 
279 
        OR1K_DELAYED_NOP(OR1K_INST(l.jal   default_exception_handler_c))
280 
 
281 
        l.lwz   r2, 0x78(r1) /* EPCR */
282 
        l.mtspr r0,r2, SPR_EPCR_BASE
283 
        l.lwz   r2, 0x7c(r1) /* ESR */
284 
        l.mtspr r0,r2, SPR_ESR_BASE
285 
 
286 
        l.lwz    r2, 0x00(r1)
287 
        l.lwz    r3, 0x04(r1)
288 
        l.lwz    r4, 0x08(r1)
289 
        l.lwz    r5, 0x0c(r1)
290 
        l.lwz    r6, 0x10(r1)
291 
        l.lwz    r7, 0x14(r1)
292 
        l.lwz    r8, 0x18(r1)
293 
        l.lwz    r9, 0x1c(r1)
294 
        l.lwz    r10, 0x20(r1)
295 
        l.lwz    r11, 0x24(r1)
296 
        l.lwz    r12, 0x28(r1)
297 
        l.lwz    r13, 0x2c(r1)
298 
        l.lwz    r14, 0x30(r1)
299 
        l.lwz    r15, 0x34(r1)
300 
        l.lwz    r16, 0x38(r1)
301 
        l.lwz    r17, 0x3c(r1)
302 
        l.lwz    r18, 0x40(r1)
303 
        l.lwz    r19, 0x44(r1)
304 
        l.lwz    r20, 0x48(r1)
305 
        l.lwz    r21, 0x4c(r1)
306 
        l.lwz    r22, 0x50(r1)
307 
        l.lwz    r23, 0x54(r1)
308 
        l.lwz    r24, 0x58(r1)
309 
        l.lwz    r25, 0x5c(r1)
310 
        l.lwz    r26, 0x60(r1)
311 
        l.lwz    r27, 0x64(r1)
312 
        l.lwz    r28, 0x68(r1)
313 
        l.lwz    r29, 0x6c(r1)
314 
        l.lwz    r30, 0x70(r1)
315 
        l.lwz    r31, 0x74(r1)
316 
 
317 
        l.addi  r1, r1, EXCEPTION_STACK_SIZE
318 
 
319 
        l.rfe
320 
        l.nop

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