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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [sw/] [mor1kx/] [mmu.S] - Blame information for rev 38

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#include "spr-defs.h"
#include 
        /* MMU enable functions */
.global lo_dmmu_en
lo_dmmu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_DME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
 
 
.global lo_immu_en
lo_immu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
 
 

Line No.	Rev	Author	Line
1	38	alirezamon	`#include "spr-defs.h"`
2			`#include`
3			`/* MMU enable functions */`
4			`.global lo_dmmu_en`
5			`lo_dmmu_en:`
6			`l.mfspr r3,r0,SPR_SR`
7			`l.ori r3,r3,SPR_SR_DME`
8			`l.mtspr r0,r3,SPR_ESR_BASE`
9			`l.mtspr r0,r9,SPR_EPCR_BASE`
10			`l.rfe`
11
12
13			`.global lo_immu_en`
14			`lo_immu_en:`
15			`l.mfspr r3,r0,SPR_SR`
16			`l.ori r3,r3,SPR_SR_IME`
17			`l.mtspr r0,r3,SPR_ESR_BASE`
18			`l.mtspr r0,r9,SPR_EPCR_BASE`
19			`l.rfe`
20
21

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-3.1/] [sw/] [mor1kx/] [mmu.S] - Blame information for rev 38