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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx-defines.v] - Blame information for rev 48

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/* ****************************************************************************
  This Source Code Form is subject to the terms of the
  Open Hardware Description License, v. 1.0. If a copy
  of the OHDL was not distributed with this file, You
  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
 
  Description: mor1kx defines
 
  Copyright (C) 2012 Authors
 
  Author(s): Julius Baxter <juliusbaxter@gmail.com>
 
***************************************************************************** */
 
/* ORBIS32 opcodes - top 6 bits */
 
`define OR1K_INSN_WIDTH 32
 
`define OR1K_RD_SELECT 25:21
`define OR1K_RA_SELECT 20:16
`define OR1K_RB_SELECT 15:11
 
`define OR1K_IMM_WIDTH 16
`define OR1K_IMM_SELECT 15:0
 
`define OR1K_ALU_OPC_WIDTH 4
`define OR1K_ALU_OPC_SELECT 3:0
 
`define OR1K_ALU_OPC_ADD   `OR1K_ALU_OPC_WIDTH'h0
`define OR1K_ALU_OPC_ADDC  `OR1K_ALU_OPC_WIDTH'h1
`define OR1K_ALU_OPC_SUB   `OR1K_ALU_OPC_WIDTH'h2
`define OR1K_ALU_OPC_AND   `OR1K_ALU_OPC_WIDTH'h3
`define OR1K_ALU_OPC_OR    `OR1K_ALU_OPC_WIDTH'h4
`define OR1K_ALU_OPC_XOR   `OR1K_ALU_OPC_WIDTH'h5
`define OR1K_ALU_OPC_MUL   `OR1K_ALU_OPC_WIDTH'h6
`define OR1K_ALU_OPC_RESV  `OR1K_ALU_OPC_WIDTH'h7
`define OR1K_ALU_OPC_SHRT  `OR1K_ALU_OPC_WIDTH'h8
`define OR1K_ALU_OPC_DIV   `OR1K_ALU_OPC_WIDTH'h9
`define OR1K_ALU_OPC_DIVU  `OR1K_ALU_OPC_WIDTH'ha
`define OR1K_ALU_OPC_MULU  `OR1K_ALU_OPC_WIDTH'hb
`define OR1K_ALU_OPC_EXTBH `OR1K_ALU_OPC_WIDTH'hc
`define OR1K_ALU_OPC_EXTW  `OR1K_ALU_OPC_WIDTH'hd
`define OR1K_ALU_OPC_CMOV  `OR1K_ALU_OPC_WIDTH'he
`define OR1K_ALU_OPC_FFL1  `OR1K_ALU_OPC_WIDTH'hf
 
`define OR1K_ALU_OPC_SECONDARY_WIDTH 3
`define OR1K_ALU_OPC_SECONDARY_SELECT 8:6
 
`define OR1K_ALU_OPC_SECONDARY_SHRT_SLL `OR1K_ALU_OPC_SECONDARY_WIDTH'h0
`define OR1K_ALU_OPC_SECONDARY_SHRT_SRL `OR1K_ALU_OPC_SECONDARY_WIDTH'h1
`define OR1K_ALU_OPC_SECONDARY_SHRT_SRA `OR1K_ALU_OPC_SECONDARY_WIDTH'h2
`define OR1K_ALU_OPC_SECONDARY_SHRT_ROR `OR1K_ALU_OPC_SECONDARY_WIDTH'h3
 
`define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTHS `OR1K_ALU_OPC_SECONDARY_WIDTH'h0
`define OR1K_ALU_OPC_SECONDARY_EXTW_EXTWS  `OR1K_ALU_OPC_SECONDARY_WIDTH'h0
`define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTBS `OR1K_ALU_OPC_SECONDARY_WIDTH'h1
`define OR1K_ALU_OPC_SECONDARY_EXTW_EXTWZ  `OR1K_ALU_OPC_SECONDARY_WIDTH'h1
`define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTHZ `OR1K_ALU_OPC_SECONDARY_WIDTH'h2
`define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTBZ `OR1K_ALU_OPC_SECONDARY_WIDTH'h3
 
`define OR1K_COMP_OPC_WIDTH 4
`define OR1K_COMP_OPC_SELECT 24:21
`define OR1K_COMP_OPC_EQ  `OR1K_COMP_OPC_WIDTH'h0
`define OR1K_COMP_OPC_NE  `OR1K_COMP_OPC_WIDTH'h1
`define OR1K_COMP_OPC_GTU `OR1K_COMP_OPC_WIDTH'h2
`define OR1K_COMP_OPC_GEU `OR1K_COMP_OPC_WIDTH'h3
`define OR1K_COMP_OPC_LTU `OR1K_COMP_OPC_WIDTH'h4
`define OR1K_COMP_OPC_LEU `OR1K_COMP_OPC_WIDTH'h5
`define OR1K_COMP_OPC_GTS `OR1K_COMP_OPC_WIDTH'ha
`define OR1K_COMP_OPC_GES `OR1K_COMP_OPC_WIDTH'hb
`define OR1K_COMP_OPC_LTS `OR1K_COMP_OPC_WIDTH'hc
`define OR1K_COMP_OPC_LES `OR1K_COMP_OPC_WIDTH'hd
 
`define OR1K_JUMPBRANCH_IMMEDIATE_SELECT 25:0
 
`define OR1K_SYSTRAPSYNC_OPC_WIDTH 3
`define OR1K_SYSTRAPSYNC_OPC_SELECT 25:23
`define OR1K_SYSTRAPSYNC_OPC_SYSCALL `OR1K_SYSTRAPSYNC_OPC_WIDTH'h0
`define OR1K_SYSTRAPSYNC_OPC_TRAP `OR1K_SYSTRAPSYNC_OPC_WIDTH'h2
`define OR1K_SYSTRAPSYNC_OPC_MSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h4
`define OR1K_SYSTRAPSYNC_OPC_PSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h5
`define OR1K_SYSTRAPSYNC_OPC_CSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h6
 
`define OR1K_OPCODE_WIDTH 6
`define OR1K_OPCODE_SELECT 31:26
 
`define OR1K_OPCODE_J       {2'b00, 4'h0}
`define OR1K_OPCODE_JAL     {2'b00, 4'h1}
`define OR1K_OPCODE_BNF     {2'b00, 4'h3}
`define OR1K_OPCODE_BF      {2'b00, 4'h4}
`define OR1K_OPCODE_NOP     {2'b00, 4'h5}
`define OR1K_OPCODE_MOVHI   {2'b00, 4'h6}
`define OR1K_OPCODE_MACRC   {2'b00, 4'h6}
 
/*
`define OR1K_OPCODE_SYS     {2'b00, 4'h8}
`define OR1K_OPCODE_TRAP    {2'b00, 4'h8}
`define OR1K_OPCODE_MSYNC   {2'b00, 4'h8}
`define OR1K_OPCODE_PSYNC   {2'b00, 4'h8}
`define OR1K_OPCODE_CSYNC   {2'b00, 4'h8}
 */
`define OR1K_OPCODE_SYSTRAPSYNC {2'b00, 4'h8}
`define OR1K_OPCODE_RFE     {2'b00, 4'h9}
 
`define OR1K_OPCODE_JR      {2'b01, 4'h1}
`define OR1K_OPCODE_JALR    {2'b01, 4'h2}
`define OR1K_OPCODE_MACI    {2'b01, 4'h3}
`define OR1K_OPCODE_LWA     {2'b01, 4'hB}
`define OR1K_OPCODE_CUST1   {2'b01, 4'hC}
`define OR1K_OPCODE_CUST2   {2'b01, 4'hD}
`define OR1K_OPCODE_CUST3   {2'b01, 4'hE}
`define OR1K_OPCODE_CUST4   {2'b01, 4'hF}
 
`define OR1K_OPCODE_LD      {2'b10, 4'h0}
`define OR1K_OPCODE_LWZ     {2'b10, 4'h1}
`define OR1K_OPCODE_LWS     {2'b10, 4'h2}
`define OR1K_OPCODE_LBZ     {2'b10, 4'h3}
`define OR1K_OPCODE_LBS     {2'b10, 4'h4}
`define OR1K_OPCODE_LHZ     {2'b10, 4'h5}
`define OR1K_OPCODE_LHS     {2'b10, 4'h6}
 
`define OR1K_OPCODE_ADDI    {2'b10, 4'h7}
`define OR1K_OPCODE_ADDIC   {2'b10, 4'h8}
`define OR1K_OPCODE_ANDI    {2'b10, 4'h9}
`define OR1K_OPCODE_ORI     {2'b10, 4'hA}
`define OR1K_OPCODE_XORI    {2'b10, 4'hB}
`define OR1K_OPCODE_MULI    {2'b10, 4'hC}
`define OR1K_OPCODE_MFSPR   {2'b10, 4'hD}
/*
`define OR1K_OPCODE_SLLI    {2'b10, 4'hE}
`define OR1K_OPCODE_SRLI    {2'b10, 4'hE}
`define OR1K_OPCODE_SRAI    {2'b10, 4'hE}
`define OR1K_OPCODE_RORI    {2'b10, 4'hE}
*/
`define OR1K_OPCODE_SHRTI    {2'b10, 4'hE}
 
/*
`define OR1K_OPCODE_SFEQI   {2'b10, 4'hF}
`define OR1K_OPCODE_SFNEI   {2'b10, 4'hF}
`define OR1K_OPCODE_SFGTUI  {2'b10, 4'hF}
`define OR1K_OPCODE_SFGEUI  {2'b10, 4'hF}
`define OR1K_OPCODE_SFLTUI  {2'b10, 4'hF}
`define OR1K_OPCODE_SFLEUI  {2'b10, 4'hF}
`define OR1K_OPCODE_SFGTSI  {2'b10, 4'hF}
`define OR1K_OPCODE_SFGESI  {2'b10, 4'hF}
`define OR1K_OPCODE_SFLTSI  {2'b10, 4'hF}
`define OR1K_OPCODE_SFLESI  {2'b10, 4'hF}
*/
`define OR1K_OPCODE_SFIMM   {2'b10, 4'hF}
 
`define OR1K_OPCODE_MTSPR   {2'b11, 4'h0}
`define OR1K_OPCODE_MAC     {2'b11, 4'h1}
`define OR1K_OPCODE_MSB     {2'b11, 4'h1}
 
`define OR1K_OPCODE_SWA     {2'b11, 4'h3}
`define OR1K_OPCODE_SD      {2'b11, 4'h4}
`define OR1K_OPCODE_SW      {2'b11, 4'h5}
`define OR1K_OPCODE_SB      {2'b11, 4'h6}
`define OR1K_OPCODE_SH      {2'b11, 4'h7}
 
/*
`define OR1K_OPCODE_ADD     {2'b11, 4'h8}
`define OR1K_OPCODE_ADDC    {2'b11, 4'h8}
`define OR1K_OPCODE_SUB     {2'b11, 4'h8}
`define OR1K_OPCODE_AND     {2'b11, 4'h8}
`define OR1K_OPCODE_OR      {2'b11, 4'h8}
`define OR1K_OPCODE_XOR     {2'b11, 4'h8}
`define OR1K_OPCODE_MUL     {2'b11, 4'h8}
 
`define OR1K_OPCODE_SLL     {2'b11, 4'h8}
`define OR1K_OPCODE_SRL     {2'b11, 4'h8}
`define OR1K_OPCODE_SRA     {2'b11, 4'h8}
`define OR1K_OPCODE_ROR     {2'b11, 4'h8}
`define OR1K_OPCODE_DIV     {2'b11, 4'h8}
`define OR1K_OPCODE_DIVU    {2'b11, 4'h8}
`define OR1K_OPCODE_MULU    {2'b11, 4'h8}
`define OR1K_OPCODE_EXTBS   {2'b11, 4'h8}
`define OR1K_OPCODE_EXTHS   {2'b11, 4'h8}
`define OR1K_OPCODE_EXTWS   {2'b11, 4'h8}
`define OR1K_OPCODE_EXTBZ   {2'b11, 4'h8}
`define OR1K_OPCODE_EXTHZ   {2'b11, 4'h8}
`define OR1K_OPCODE_EXTWZ   {2'b11, 4'h8}
`define OR1K_OPCODE_CMOV    {2'b11, 4'h8}
`define OR1K_OPCODE_FF1     {2'b11, 4'h8}
`define OR1K_OPCODE_FL1     {2'b11, 4'h8}
*/
`define OR1K_OPCODE_ALU     {2'b11, 4'h8}
 
/*
`define OR1K_OPCODE_SFEQ    {2'b11, 4'h9}
`define OR1K_OPCODE_SFNE    {2'b11, 4'h9}
`define OR1K_OPCODE_SFGTU   {2'b11, 4'h9}
`define OR1K_OPCODE_SFGEU   {2'b11, 4'h9}
`define OR1K_OPCODE_SFLTU   {2'b11, 4'h9}
`define OR1K_OPCODE_SFLEU   {2'b11, 4'h9}
`define OR1K_OPCODE_SFGTS   {2'b11, 4'h9}
`define OR1K_OPCODE_SFGES   {2'b11, 4'h9}
`define OR1K_OPCODE_SFLTS   {2'b11, 4'h9}
`define OR1K_OPCODE_SFLES   {2'b11, 4'h9}
*/
`define OR1K_OPCODE_SF      {2'b11, 4'h9}
 
`define OR1K_OPCODE_CUST5   {2'b11, 4'hC}
`define OR1K_OPCODE_CUST6   {2'b11, 4'hD}
`define OR1K_OPCODE_CUST7   {2'b11, 4'hE}
`define OR1K_OPCODE_CUST8   {2'b11, 4'hF}
 
//
// ORFPX32 opcodes
//
`define OR1K_OPCODE_FPU  {2'b11, 4'h2}
// FP OPs
// MSbit indicates FPU operation valid
`define OR1K_FPUOP_WIDTH        8
`define OR1K_FPUOP_SELECT 7:0
// Select bits for Ordered/Unordered comparison
`define OR1K_FPUOP_GENERIC_CMP_WIDTH 3
`define OR1K_FPUOP_GENERIC_CMP_SELECT 2:0
// Unordered comparison bit
`define OR1K_FPUOP_UNORDERED_CMP_BIT 5
// FP instruction is double precision if bit 4 is set. We're a 32-bit 
// implementation thus do not support double precision FP 
`define OR1K_FPUOP_DOUBLE_BIT 4
// FP Arithmetic OPCs
`define OR1K_FPUOP_ADD       8'b0000_0000
`define OR1K_FPUOP_SUB       8'b0000_0001
`define OR1K_FPUOP_MUL       8'b0000_0010
`define OR1K_FPUOP_DIV       8'b0000_0011
`define OR1K_FPUOP_ITOF      8'b0000_0100
`define OR1K_FPUOP_FTOI      8'b0000_0101
`define OR1K_FPUOP_REM       8'b0000_0110
`define OR1K_FPUOP_RESERVED  8'b0000_0111
// FP Ordered Comparison OPCs
`define OR1K_FPCOP_SFEQ      8'b0000_1000
`define OR1K_FPCOP_SFNE      8'b0000_1001
`define OR1K_FPCOP_SFGT      8'b0000_1010
`define OR1K_FPCOP_SFGE      8'b0000_1011
`define OR1K_FPCOP_SFLT      8'b0000_1100
`define OR1K_FPCOP_SFLE      8'b0000_1101
// FP Unordered Comparison OPCs
`define OR1K_FPCOP_SFUEQ     8'b0010_1000
`define OR1K_FPCOP_SFUNE     8'b0010_1001
`define OR1K_FPCOP_SFUGT     8'b0010_1010
`define OR1K_FPCOP_SFUGE     8'b0010_1011
`define OR1K_FPCOP_SFULT     8'b0010_1100
`define OR1K_FPCOP_SFULE     8'b0010_1101
`define OR1K_FPCOP_SFUN      8'b0010_1110
 
 
//
// OR1K SPR defines
//
`include "mor1kx-sprs.v"
 
/* Exception addresses */
`define OR1K_RESET_VECTOR    5'h01
`define OR1K_BERR_VECTOR     5'h02
`define OR1K_DPF_VECTOR      5'h03
`define OR1K_IPF_VECTOR      5'h04
`define OR1K_TT_VECTOR       5'h05
`define OR1K_ALIGN_VECTOR    5'h06
`define OR1K_ILLEGAL_VECTOR  5'h07
`define OR1K_INT_VECTOR      5'h08
`define OR1K_DTLB_VECTOR     5'h09
`define OR1K_ITLB_VECTOR     5'h0a
`define OR1K_RANGE_VECTOR    5'h0b
`define OR1K_SYSCALL_VECTOR  5'h0c
`define OR1K_FP_VECTOR       5'h0d
`define OR1K_TRAP_VECTOR     5'h0e
 
// Whether we'll allow things using AYNC reset to have it:
//`define OR_ASYNC_RST or posedge rst
`define OR_ASYNC_RST
 
// Implementation version defines
`define MOR1KX_CPUID 8'h01
// mor1kx breaks up the VR2 version register to be 3 8-bit fields
// MSB is major version, middle byte is minor version number
// and final byte is the pipeline identifier.
`define MOR1KX_VERSION_MAJOR 8'd5
`define MOR1KX_VERSION_MINOR 8'd0
 
// mor1kx implementation-specific register definitions
`define MOR1KX_PIPEID_CAPPUCCINO 8'd1
`define MOR1KX_PIPEID_ESPRESSO   8'd2
`define MOR1KX_PIPEID_PRONTOESPRESSO 8'd3

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx-defines.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`/* ****************************************************************************`
2			`This Source Code Form is subject to the terms of the`
3			`Open Hardware Description License, v. 1.0. If a copy`
4			`of the OHDL was not distributed with this file, You`
5			`can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt`
6
7			`Description: mor1kx defines`
8
9			`Copyright (C) 2012 Authors`
10
11			`Author(s): Julius Baxter <juliusbaxter@gmail.com>`
12
13			`***************************************************************************** */`
14
15			`/* ORBIS32 opcodes - top 6 bits */`
16
17			`define OR1K_INSN_WIDTH 32
18
19			`define OR1K_RD_SELECT 25:21
20			`define OR1K_RA_SELECT 20:16
21			`define OR1K_RB_SELECT 15:11
22
23			`define OR1K_IMM_WIDTH 16
24			`define OR1K_IMM_SELECT 15:0
25
26			`define OR1K_ALU_OPC_WIDTH 4
27			`define OR1K_ALU_OPC_SELECT 3:0
28
29			`define OR1K_ALU_OPC_ADD `OR1K_ALU_OPC_WIDTH'h0
30			`define OR1K_ALU_OPC_ADDC `OR1K_ALU_OPC_WIDTH'h1
31			`define OR1K_ALU_OPC_SUB `OR1K_ALU_OPC_WIDTH'h2
32			`define OR1K_ALU_OPC_AND `OR1K_ALU_OPC_WIDTH'h3
33			`define OR1K_ALU_OPC_OR `OR1K_ALU_OPC_WIDTH'h4
34			`define OR1K_ALU_OPC_XOR `OR1K_ALU_OPC_WIDTH'h5
35			`define OR1K_ALU_OPC_MUL `OR1K_ALU_OPC_WIDTH'h6
36			`define OR1K_ALU_OPC_RESV `OR1K_ALU_OPC_WIDTH'h7
37			`define OR1K_ALU_OPC_SHRT `OR1K_ALU_OPC_WIDTH'h8
38			`define OR1K_ALU_OPC_DIV `OR1K_ALU_OPC_WIDTH'h9
39			`define OR1K_ALU_OPC_DIVU `OR1K_ALU_OPC_WIDTH'ha
40			`define OR1K_ALU_OPC_MULU `OR1K_ALU_OPC_WIDTH'hb
41			`define OR1K_ALU_OPC_EXTBH `OR1K_ALU_OPC_WIDTH'hc
42			`define OR1K_ALU_OPC_EXTW `OR1K_ALU_OPC_WIDTH'hd
43			`define OR1K_ALU_OPC_CMOV `OR1K_ALU_OPC_WIDTH'he
44			`define OR1K_ALU_OPC_FFL1 `OR1K_ALU_OPC_WIDTH'hf
45
46			`define OR1K_ALU_OPC_SECONDARY_WIDTH 3
47			`define OR1K_ALU_OPC_SECONDARY_SELECT 8:6
48
49			`define OR1K_ALU_OPC_SECONDARY_SHRT_SLL `OR1K_ALU_OPC_SECONDARY_WIDTH'h0
50			`define OR1K_ALU_OPC_SECONDARY_SHRT_SRL `OR1K_ALU_OPC_SECONDARY_WIDTH'h1
51			`define OR1K_ALU_OPC_SECONDARY_SHRT_SRA `OR1K_ALU_OPC_SECONDARY_WIDTH'h2
52			`define OR1K_ALU_OPC_SECONDARY_SHRT_ROR `OR1K_ALU_OPC_SECONDARY_WIDTH'h3
53
54			`define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTHS `OR1K_ALU_OPC_SECONDARY_WIDTH'h0
55			`define OR1K_ALU_OPC_SECONDARY_EXTW_EXTWS `OR1K_ALU_OPC_SECONDARY_WIDTH'h0
56			`define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTBS `OR1K_ALU_OPC_SECONDARY_WIDTH'h1
57			`define OR1K_ALU_OPC_SECONDARY_EXTW_EXTWZ `OR1K_ALU_OPC_SECONDARY_WIDTH'h1
58			`define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTHZ `OR1K_ALU_OPC_SECONDARY_WIDTH'h2
59			`define OR1K_ALU_OPC_SECONDARY_EXTBH_EXTBZ `OR1K_ALU_OPC_SECONDARY_WIDTH'h3
60
61			`define OR1K_COMP_OPC_WIDTH 4
62			`define OR1K_COMP_OPC_SELECT 24:21
63			`define OR1K_COMP_OPC_EQ `OR1K_COMP_OPC_WIDTH'h0
64			`define OR1K_COMP_OPC_NE `OR1K_COMP_OPC_WIDTH'h1
65			`define OR1K_COMP_OPC_GTU `OR1K_COMP_OPC_WIDTH'h2
66			`define OR1K_COMP_OPC_GEU `OR1K_COMP_OPC_WIDTH'h3
67			`define OR1K_COMP_OPC_LTU `OR1K_COMP_OPC_WIDTH'h4
68			`define OR1K_COMP_OPC_LEU `OR1K_COMP_OPC_WIDTH'h5
69			`define OR1K_COMP_OPC_GTS `OR1K_COMP_OPC_WIDTH'ha
70			`define OR1K_COMP_OPC_GES `OR1K_COMP_OPC_WIDTH'hb
71			`define OR1K_COMP_OPC_LTS `OR1K_COMP_OPC_WIDTH'hc
72			`define OR1K_COMP_OPC_LES `OR1K_COMP_OPC_WIDTH'hd
73
74			`define OR1K_JUMPBRANCH_IMMEDIATE_SELECT 25:0
75
76			`define OR1K_SYSTRAPSYNC_OPC_WIDTH 3
77			`define OR1K_SYSTRAPSYNC_OPC_SELECT 25:23
78			`define OR1K_SYSTRAPSYNC_OPC_SYSCALL `OR1K_SYSTRAPSYNC_OPC_WIDTH'h0
79			`define OR1K_SYSTRAPSYNC_OPC_TRAP `OR1K_SYSTRAPSYNC_OPC_WIDTH'h2
80			`define OR1K_SYSTRAPSYNC_OPC_MSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h4
81			`define OR1K_SYSTRAPSYNC_OPC_PSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h5
82			`define OR1K_SYSTRAPSYNC_OPC_CSYNC `OR1K_SYSTRAPSYNC_OPC_WIDTH'h6
83
84			`define OR1K_OPCODE_WIDTH 6
85			`define OR1K_OPCODE_SELECT 31:26
86
87			`define OR1K_OPCODE_J {2'b00, 4'h0}
88			`define OR1K_OPCODE_JAL {2'b00, 4'h1}
89			`define OR1K_OPCODE_BNF {2'b00, 4'h3}
90			`define OR1K_OPCODE_BF {2'b00, 4'h4}
91			`define OR1K_OPCODE_NOP {2'b00, 4'h5}
92			`define OR1K_OPCODE_MOVHI {2'b00, 4'h6}
93			`define OR1K_OPCODE_MACRC {2'b00, 4'h6}
94
95			`/*`
96			`define OR1K_OPCODE_SYS {2'b00, 4'h8}
97			`define OR1K_OPCODE_TRAP {2'b00, 4'h8}
98			`define OR1K_OPCODE_MSYNC {2'b00, 4'h8}
99			`define OR1K_OPCODE_PSYNC {2'b00, 4'h8}
100			`define OR1K_OPCODE_CSYNC {2'b00, 4'h8}
101			`*/`
102			`define OR1K_OPCODE_SYSTRAPSYNC {2'b00, 4'h8}
103			`define OR1K_OPCODE_RFE {2'b00, 4'h9}
104
105			`define OR1K_OPCODE_JR {2'b01, 4'h1}
106			`define OR1K_OPCODE_JALR {2'b01, 4'h2}
107			`define OR1K_OPCODE_MACI {2'b01, 4'h3}
108			`define OR1K_OPCODE_LWA {2'b01, 4'hB}
109			`define OR1K_OPCODE_CUST1 {2'b01, 4'hC}
110			`define OR1K_OPCODE_CUST2 {2'b01, 4'hD}
111			`define OR1K_OPCODE_CUST3 {2'b01, 4'hE}
112			`define OR1K_OPCODE_CUST4 {2'b01, 4'hF}
113
114			`define OR1K_OPCODE_LD {2'b10, 4'h0}
115			`define OR1K_OPCODE_LWZ {2'b10, 4'h1}
116			`define OR1K_OPCODE_LWS {2'b10, 4'h2}
117			`define OR1K_OPCODE_LBZ {2'b10, 4'h3}
118			`define OR1K_OPCODE_LBS {2'b10, 4'h4}
119			`define OR1K_OPCODE_LHZ {2'b10, 4'h5}
120			`define OR1K_OPCODE_LHS {2'b10, 4'h6}
121
122			`define OR1K_OPCODE_ADDI {2'b10, 4'h7}
123			`define OR1K_OPCODE_ADDIC {2'b10, 4'h8}
124			`define OR1K_OPCODE_ANDI {2'b10, 4'h9}
125			`define OR1K_OPCODE_ORI {2'b10, 4'hA}
126			`define OR1K_OPCODE_XORI {2'b10, 4'hB}
127			`define OR1K_OPCODE_MULI {2'b10, 4'hC}
128			`define OR1K_OPCODE_MFSPR {2'b10, 4'hD}
129			`/*`
130			`define OR1K_OPCODE_SLLI {2'b10, 4'hE}
131			`define OR1K_OPCODE_SRLI {2'b10, 4'hE}
132			`define OR1K_OPCODE_SRAI {2'b10, 4'hE}
133			`define OR1K_OPCODE_RORI {2'b10, 4'hE}
134			`*/`
135			`define OR1K_OPCODE_SHRTI {2'b10, 4'hE}
136
137			`/*`
138			`define OR1K_OPCODE_SFEQI {2'b10, 4'hF}
139			`define OR1K_OPCODE_SFNEI {2'b10, 4'hF}
140			`define OR1K_OPCODE_SFGTUI {2'b10, 4'hF}
141			`define OR1K_OPCODE_SFGEUI {2'b10, 4'hF}
142			`define OR1K_OPCODE_SFLTUI {2'b10, 4'hF}
143			`define OR1K_OPCODE_SFLEUI {2'b10, 4'hF}
144			`define OR1K_OPCODE_SFGTSI {2'b10, 4'hF}
145			`define OR1K_OPCODE_SFGESI {2'b10, 4'hF}
146			`define OR1K_OPCODE_SFLTSI {2'b10, 4'hF}
147			`define OR1K_OPCODE_SFLESI {2'b10, 4'hF}
148			`*/`
149			`define OR1K_OPCODE_SFIMM {2'b10, 4'hF}
150
151			`define OR1K_OPCODE_MTSPR {2'b11, 4'h0}
152			`define OR1K_OPCODE_MAC {2'b11, 4'h1}
153			`define OR1K_OPCODE_MSB {2'b11, 4'h1}
154
155			`define OR1K_OPCODE_SWA {2'b11, 4'h3}
156			`define OR1K_OPCODE_SD {2'b11, 4'h4}
157			`define OR1K_OPCODE_SW {2'b11, 4'h5}
158			`define OR1K_OPCODE_SB {2'b11, 4'h6}
159			`define OR1K_OPCODE_SH {2'b11, 4'h7}
160
161			`/*`
162			`define OR1K_OPCODE_ADD {2'b11, 4'h8}
163			`define OR1K_OPCODE_ADDC {2'b11, 4'h8}
164			`define OR1K_OPCODE_SUB {2'b11, 4'h8}
165			`define OR1K_OPCODE_AND {2'b11, 4'h8}
166			`define OR1K_OPCODE_OR {2'b11, 4'h8}
167			`define OR1K_OPCODE_XOR {2'b11, 4'h8}
168			`define OR1K_OPCODE_MUL {2'b11, 4'h8}
169
170			`define OR1K_OPCODE_SLL {2'b11, 4'h8}
171			`define OR1K_OPCODE_SRL {2'b11, 4'h8}
172			`define OR1K_OPCODE_SRA {2'b11, 4'h8}
173			`define OR1K_OPCODE_ROR {2'b11, 4'h8}
174			`define OR1K_OPCODE_DIV {2'b11, 4'h8}
175			`define OR1K_OPCODE_DIVU {2'b11, 4'h8}
176			`define OR1K_OPCODE_MULU {2'b11, 4'h8}
177			`define OR1K_OPCODE_EXTBS {2'b11, 4'h8}
178			`define OR1K_OPCODE_EXTHS {2'b11, 4'h8}
179			`define OR1K_OPCODE_EXTWS {2'b11, 4'h8}
180			`define OR1K_OPCODE_EXTBZ {2'b11, 4'h8}
181			`define OR1K_OPCODE_EXTHZ {2'b11, 4'h8}
182			`define OR1K_OPCODE_EXTWZ {2'b11, 4'h8}
183			`define OR1K_OPCODE_CMOV {2'b11, 4'h8}
184			`define OR1K_OPCODE_FF1 {2'b11, 4'h8}
185			`define OR1K_OPCODE_FL1 {2'b11, 4'h8}
186			`*/`
187			`define OR1K_OPCODE_ALU {2'b11, 4'h8}
188
189			`/*`
190			`define OR1K_OPCODE_SFEQ {2'b11, 4'h9}
191			`define OR1K_OPCODE_SFNE {2'b11, 4'h9}
192			`define OR1K_OPCODE_SFGTU {2'b11, 4'h9}
193			`define OR1K_OPCODE_SFGEU {2'b11, 4'h9}
194			`define OR1K_OPCODE_SFLTU {2'b11, 4'h9}
195			`define OR1K_OPCODE_SFLEU {2'b11, 4'h9}
196			`define OR1K_OPCODE_SFGTS {2'b11, 4'h9}
197			`define OR1K_OPCODE_SFGES {2'b11, 4'h9}
198			`define OR1K_OPCODE_SFLTS {2'b11, 4'h9}
199			`define OR1K_OPCODE_SFLES {2'b11, 4'h9}
200			`*/`
201			`define OR1K_OPCODE_SF {2'b11, 4'h9}
202
203			`define OR1K_OPCODE_CUST5 {2'b11, 4'hC}
204			`define OR1K_OPCODE_CUST6 {2'b11, 4'hD}
205			`define OR1K_OPCODE_CUST7 {2'b11, 4'hE}
206			`define OR1K_OPCODE_CUST8 {2'b11, 4'hF}
207
208			`//`
209			`// ORFPX32 opcodes`
210			`//`
211			`define OR1K_OPCODE_FPU {2'b11, 4'h2}
212			`// FP OPs`
213			`// MSbit indicates FPU operation valid`
214			`define OR1K_FPUOP_WIDTH 8
215			`define OR1K_FPUOP_SELECT 7:0
216			`// Select bits for Ordered/Unordered comparison`
217			`define OR1K_FPUOP_GENERIC_CMP_WIDTH 3
218			`define OR1K_FPUOP_GENERIC_CMP_SELECT 2:0
219			`// Unordered comparison bit`
220			`define OR1K_FPUOP_UNORDERED_CMP_BIT 5
221			`// FP instruction is double precision if bit 4 is set. We're a 32-bit`
222			`// implementation thus do not support double precision FP`
223			`define OR1K_FPUOP_DOUBLE_BIT 4
224			`// FP Arithmetic OPCs`
225			`define OR1K_FPUOP_ADD 8'b0000_0000
226			`define OR1K_FPUOP_SUB 8'b0000_0001
227			`define OR1K_FPUOP_MUL 8'b0000_0010
228			`define OR1K_FPUOP_DIV 8'b0000_0011
229			`define OR1K_FPUOP_ITOF 8'b0000_0100
230			`define OR1K_FPUOP_FTOI 8'b0000_0101
231			`define OR1K_FPUOP_REM 8'b0000_0110
232			`define OR1K_FPUOP_RESERVED 8'b0000_0111
233			`// FP Ordered Comparison OPCs`
234			`define OR1K_FPCOP_SFEQ 8'b0000_1000
235			`define OR1K_FPCOP_SFNE 8'b0000_1001
236			`define OR1K_FPCOP_SFGT 8'b0000_1010
237			`define OR1K_FPCOP_SFGE 8'b0000_1011
238			`define OR1K_FPCOP_SFLT 8'b0000_1100
239			`define OR1K_FPCOP_SFLE 8'b0000_1101
240			`// FP Unordered Comparison OPCs`
241			`define OR1K_FPCOP_SFUEQ 8'b0010_1000
242			`define OR1K_FPCOP_SFUNE 8'b0010_1001
243			`define OR1K_FPCOP_SFUGT 8'b0010_1010
244			`define OR1K_FPCOP_SFUGE 8'b0010_1011
245			`define OR1K_FPCOP_SFULT 8'b0010_1100
246			`define OR1K_FPCOP_SFULE 8'b0010_1101
247			`define OR1K_FPCOP_SFUN 8'b0010_1110
248
249
250			`//`
251			`// OR1K SPR defines`
252			`//`
253			`include "mor1kx-sprs.v"
254
255			`/* Exception addresses */`
256			`define OR1K_RESET_VECTOR 5'h01
257			`define OR1K_BERR_VECTOR 5'h02
258			`define OR1K_DPF_VECTOR 5'h03
259			`define OR1K_IPF_VECTOR 5'h04
260			`define OR1K_TT_VECTOR 5'h05
261			`define OR1K_ALIGN_VECTOR 5'h06
262			`define OR1K_ILLEGAL_VECTOR 5'h07
263			`define OR1K_INT_VECTOR 5'h08
264			`define OR1K_DTLB_VECTOR 5'h09
265			`define OR1K_ITLB_VECTOR 5'h0a
266			`define OR1K_RANGE_VECTOR 5'h0b
267			`define OR1K_SYSCALL_VECTOR 5'h0c
268			`define OR1K_FP_VECTOR 5'h0d
269			`define OR1K_TRAP_VECTOR 5'h0e
270
271			`// Whether we'll allow things using AYNC reset to have it:`
272			//`define OR_ASYNC_RST or posedge rst
273			`define OR_ASYNC_RST
274
275			`// Implementation version defines`
276			`define MOR1KX_CPUID 8'h01
277			`// mor1kx breaks up the VR2 version register to be 3 8-bit fields`
278			`// MSB is major version, middle byte is minor version number`
279			`// and final byte is the pipeline identifier.`
280			`define MOR1KX_VERSION_MAJOR 8'd5
281			`define MOR1KX_VERSION_MINOR 8'd0
282
283			`// mor1kx implementation-specific register definitions`
284			`define MOR1KX_PIPEID_CAPPUCCINO 8'd1
285			`define MOR1KX_PIPEID_ESPRESSO 8'd2
286			`define MOR1KX_PIPEID_PRONTOESPRESSO 8'd3