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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx_branch_predictor_gshare.v] - Blame information for rev 48

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1 48 alirezamon 
/******************************************************************************
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 This Source Code Form is subject to the terms of the
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 Open Hardware Description License, v. 1.0. If a copy
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 of the OHDL was not distributed with this file, You
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 can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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 Description: gshare branch predictor
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 This predictor is based on array of FSMs with 4 states: strongly not taken,
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 weakly not taken, weakly taken, strongly taken. Check saturation predictor.
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 Index to the array of FSMs is built using xor of global history and lower bits of PC.
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 Copyright (C) 2016 Alexey Baturo <baturo.alexey@gmail.com>
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 ******************************************************************************/
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`include "mor1kx-defines.v"
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module mor1kx_branch_predictor_gshare
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  #(
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    parameter GSHARE_BITS_NUM = 10,
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    parameter OPTION_OPERAND_WIDTH = 32
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    )
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   (
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    input clk,
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    input rst,
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    // Signals belonging to the stage where the branch is predicted.
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    output predicted_flag_o,     //result of predictor
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    input execute_op_bf_i,       // prev insn was bf
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    input execute_op_bnf_i,      // prev insn was bnf
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    input op_bf_i,               // cur insn is bf
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    input op_bnf_i,              // cur insn is bnf
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    input padv_decode_i,         // pipeline is moved
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    input flag_i,                // prev predicted flag
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    // Signals belonging to the stage where the branch is resolved.
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    input prev_op_brcond_i,      // prev op was cond brn
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    input branch_mispredict_i,    // prev brn was mispredicted
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    input [OPTION_OPERAND_WIDTH-1:0]  brn_pc_i
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    );
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   localparam [1:0]
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      STATE_STRONGLY_NOT_TAKEN = 2'b00,
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      STATE_WEAKLY_NOT_TAKEN   = 2'b01,
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      STATE_WEAKLY_TAKEN       = 2'b10,
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      STATE_STRONGLY_TAKEN     = 2'b11;
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   localparam FSM_NUM = 2 ** GSHARE_BITS_NUM;
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   integer i = 0;
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   reg [1:0] state [0:FSM_NUM];
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   reg [GSHARE_BITS_NUM:0] brn_hist_reg = 0;
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   reg [GSHARE_BITS_NUM - 1:0] prev_idx = 0;
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   // +2 bits for alignement
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   wire [GSHARE_BITS_NUM - 1:0] state_index = brn_hist_reg[GSHARE_BITS_NUM - 1:0] ^ brn_pc_i[GSHARE_BITS_NUM + 1:2];
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   assign predicted_flag_o = (state[state_index][1] && op_bf_i) ||
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                             (!state[state_index][1] && op_bnf_i);
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   wire brn_taken = (execute_op_bf_i && flag_i) || (execute_op_bnf_i && !flag_i);
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   always @(posedge clk) begin
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      if (rst) begin
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         brn_hist_reg <= 0;
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         prev_idx <= 0;
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         for(i = 0; i < FSM_NUM; i = i + 1) begin
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            state[i] <= STATE_WEAKLY_TAKEN;
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         end
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      end else begin
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         if (op_bf_i || op_bnf_i) begin
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            // store prev index
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            prev_idx <= state_index;
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         end
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         if (prev_op_brcond_i && padv_decode_i) begin
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            brn_hist_reg <= {brn_hist_reg[GSHARE_BITS_NUM - 1 : 0], brn_taken};
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            if (!brn_taken) begin
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               // change fsm state:
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               //   STATE_STRONGLY_TAKEN -> STATE_WEAKLY_TAKEN
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               //   STATE_WEAKLY_TAKEN -> STATE_WEAKLY_NOT_TAKEN
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               //   STATE_WEAKLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
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               //   STATE_STRONGLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
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               case (state[prev_idx])
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                  STATE_STRONGLY_TAKEN:
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                     state[prev_idx] <= STATE_WEAKLY_TAKEN;
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                  STATE_WEAKLY_TAKEN:
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                     state[prev_idx] <= STATE_WEAKLY_NOT_TAKEN;
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                  STATE_WEAKLY_NOT_TAKEN:
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                     state[prev_idx] <= STATE_STRONGLY_NOT_TAKEN;
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                  STATE_STRONGLY_NOT_TAKEN:
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                     state[prev_idx] <= STATE_STRONGLY_NOT_TAKEN;
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               endcase
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            end else begin
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               // change fsm state:
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               //   STATE_STRONGLY_NOT_TAKEN -> STATE_WEAKLY_NOT_TAKEN
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               //   STATE_WEAKLY_NOT_TAKEN -> STATE_WEAKLY_TAKEN
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               //   STATE_WEAKLY_TAKEN -> STATE_STRONGLY_TAKEN
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               //   STATE_STRONGLY_TAKEN -> STATE_STRONGLY_TAKEN
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               case (state[prev_idx])
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                  STATE_STRONGLY_NOT_TAKEN:
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                     state[prev_idx] <= STATE_WEAKLY_NOT_TAKEN;
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                  STATE_WEAKLY_NOT_TAKEN:
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                     state[prev_idx] <= STATE_WEAKLY_TAKEN;
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                  STATE_WEAKLY_TAKEN:
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                     state[prev_idx] <= STATE_STRONGLY_TAKEN;
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                  STATE_STRONGLY_TAKEN:
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                     state[prev_idx] <= STATE_STRONGLY_TAKEN;
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               endcase
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            end
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         end
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      end
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   end
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endmodule

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