OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx_branch_predictor_saturation_counter.v] - Blame information for rev 48

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 48 alirezamon 
/******************************************************************************
2 
 This Source Code Form is subject to the terms of the
3 
 Open Hardware Description License, v. 1.0. If a copy
4 
 of the OHDL was not distributed with this file, You
5 
 can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
6 
 
7 
 Description: Saturating counter branch predictor
8 
 This is FSM with 4 states: strongly not taken, weakly not taken,
9 
 weakly taken, strongly taken.
10 
 Fsm changes it state upon real(not predicted) flag.
11 
 If flag was "true" and instruction was bf  or flag was "false" and
12 
 instruction was bnf fsm changes its state towards "taken". And vice versa
13 
 otherwise.
14 
 We predict flag on current fsm state and current branch type.
15 
 If we are in any "taken" state and current instruction is bf,
16 
 we predict flag to be "true". Or we're in any "not taken" state and
17 
 current instruction is bnf, we predict flag to be "true".
18 
 
19 
 Copyright (C) 2016 Alexey Baturo <baturo.alexey@gmail.com>
20 
 
21 
 ******************************************************************************/
22 
 
23 
`include "mor1kx-defines.v"
24 
 
25 
module mor1kx_branch_predictor_saturation_counter
26 
   (
27 
    input clk,
28 
    input rst,
29 
 
30 
    // Signals belonging to the stage where the branch is predicted.
31 
    output predicted_flag_o,     //result of predictor
32 
 
33 
    input execute_op_bf_i,       // prev insn was bf
34 
    input execute_op_bnf_i,      // prev insn was bnf
35 
    input op_bf_i,               // cur insn is bf
36 
    input op_bnf_i,              // cur insn is bnf
37 
    input padv_decode_i,         // pipeline is moved
38 
    input flag_i,                // prev predicted flag
39 
 
40 
    // Signals belonging to the stage where the branch is resolved.
41 
    input prev_op_brcond_i,      // prev op was cond brn
42 
    input branch_mispredict_i    // prev brn was mispredicted
43 
    );
44 
 
45 
   localparam [1:0]
46 
      STATE_STRONGLY_NOT_TAKEN = 2'b00,
47 
      STATE_WEAKLY_NOT_TAKEN   = 2'b01,
48 
      STATE_WEAKLY_TAKEN       = 2'b10,
49 
      STATE_STRONGLY_TAKEN     = 2'b11;
50 
 
51 
   reg [1:0] state = STATE_WEAKLY_TAKEN;
52 
 
53 
   assign predicted_flag_o = (state[1] && op_bf_i) || (!state[1] && op_bnf_i);
54 
   wire brn_taken = (execute_op_bf_i && flag_i) || (execute_op_bnf_i && !flag_i);
55 
 
56 
   always @(posedge clk) begin
57 
      if (rst) begin
58 
         state <= STATE_WEAKLY_TAKEN;
59 
      end else begin
60 
         if (prev_op_brcond_i && padv_decode_i) begin
61 
            if (!brn_taken) begin
62 
               // change fsm state:
63 
               //   STATE_STRONGLY_TAKEN -> STATE_WEAKLY_TAKEN
64 
               //   STATE_WEAKLY_TAKEN -> STATE_WEAKLY_NOT_TAKEN
65 
               //   STATE_WEAKLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
66 
               //   STATE_STRONGLY_NOT_TAKEN -> STATE_STRONGLY_NOT_TAKEN
67 
               case (state)
68 
                  STATE_STRONGLY_TAKEN:
69 
                     state <= STATE_WEAKLY_TAKEN;
70 
                  STATE_WEAKLY_TAKEN:
71 
                     state <= STATE_WEAKLY_NOT_TAKEN;
72 
                  STATE_WEAKLY_NOT_TAKEN:
73 
                     state <= STATE_STRONGLY_NOT_TAKEN;
74 
                  STATE_STRONGLY_NOT_TAKEN:
75 
                     state <= STATE_STRONGLY_NOT_TAKEN;
76 
               endcase
77 
            end else begin
78 
               // change fsm state:
79 
               //   STATE_STRONGLY_NOT_TAKEN -> STATE_WEAKLY_NOT_TAKEN
80 
               //   STATE_WEAKLY_NOT_TAKEN -> STATE_WEAKLY_TAKEN
81 
               //   STATE_WEAKLY_TAKEN -> STATE_STRONGLY_TAKEN
82 
               //   STATE_STRONGLY_TAKEN -> STATE_STRONGLY_TAKEN
83 
               case (state)
84 
                  STATE_STRONGLY_NOT_TAKEN:
85 
                     state <= STATE_WEAKLY_NOT_TAKEN;
86 
                  STATE_WEAKLY_NOT_TAKEN:
87 
                     state <= STATE_WEAKLY_TAKEN;
88 
                  STATE_WEAKLY_TAKEN:
89 
                     state <= STATE_STRONGLY_TAKEN;
90 
                  STATE_STRONGLY_TAKEN:
91 
                     state <= STATE_STRONGLY_TAKEN;
92 
               endcase
93 
            end
94 
         end
95 
      end
96 
   end
97 
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.