OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx_branch_predictor_simple.v] - Blame information for rev 48

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 48 alirezamon
/******************************************************************************
2
 This Source Code Form is subject to the terms of the
3
 Open Hardware Description License, v. 1.0. If a copy
4
 of the OHDL was not distributed with this file, You
5
 can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
6
 
7
 Description: Simple branch predictor implementation
8
 We assume flag to be "true" if instruction is bf and it jumps backwords
9
 or if instruction is bnf and it jumps forward.
10
 
11
 Copyright (C) 2013 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
12
 
13
 ******************************************************************************/
14
 
15
`include "mor1kx-defines.v"
16
 
17
module mor1kx_branch_predictor_simple
18
   (
19
    // Signals belonging to the stage where the branch is predicted.
20
    input op_bf_i,               // branch if flag
21
    input op_bnf_i,              // branch if not flag
22
    input [9:0] immjbr_upper_i,  // branch offset
23
    output predicted_flag_o      //result of predictor
24
    );
25
 
26
   // Static branch prediction - backward branches are predicted as taken,
27
   // forward branches as not taken.
28
   assign predicted_flag_o = op_bf_i & immjbr_upper_i[9] |
29
                             op_bnf_i & !immjbr_upper_i[9];
30
 
31
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.