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alirezamon |
/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: "Cappuccino" pipeline CPU module
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Copyright (C) 2012 Authors
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Author(s): Julius Baxter <juliusbaxter@gmail.com>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_cpu_cappuccino
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#(
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parameter OPTION_OPERAND_WIDTH = 32,
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parameter FEATURE_DATACACHE = "NONE",
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parameter OPTION_DCACHE_BLOCK_WIDTH = 5,
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parameter OPTION_DCACHE_SET_WIDTH = 9,
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parameter OPTION_DCACHE_WAYS = 2,
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parameter OPTION_DCACHE_LIMIT_WIDTH = 32,
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parameter OPTION_DCACHE_SNOOP = "NONE",
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parameter FEATURE_DMMU = "NONE",
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parameter FEATURE_DMMU_HW_TLB_RELOAD = "NONE",
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parameter OPTION_DMMU_SET_WIDTH = 6,
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parameter OPTION_DMMU_WAYS = 1,
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parameter FEATURE_INSTRUCTIONCACHE = "NONE",
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parameter OPTION_ICACHE_BLOCK_WIDTH = 5,
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parameter OPTION_ICACHE_SET_WIDTH = 9,
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parameter OPTION_ICACHE_WAYS = 2,
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parameter OPTION_ICACHE_LIMIT_WIDTH = 32,
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parameter FEATURE_IMMU = "NONE",
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parameter FEATURE_IMMU_HW_TLB_RELOAD = "NONE",
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parameter OPTION_IMMU_SET_WIDTH = 6,
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parameter OPTION_IMMU_WAYS = 1,
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parameter FEATURE_TIMER = "ENABLED",
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parameter FEATURE_DEBUGUNIT = "NONE",
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parameter FEATURE_PERFCOUNTERS = "NONE",
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parameter OPTION_PERFCOUNTERS_NUM = 0,
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parameter FEATURE_MAC = "NONE",
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parameter FEATURE_SYSCALL = "ENABLED",
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parameter FEATURE_TRAP = "ENABLED",
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parameter FEATURE_RANGE = "ENABLED",
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parameter FEATURE_PIC = "ENABLED",
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parameter OPTION_PIC_TRIGGER = "LEVEL",
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parameter OPTION_PIC_NMI_WIDTH = 0,
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parameter FEATURE_DSX = "NONE",
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parameter FEATURE_OVERFLOW = "NONE",
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parameter FEATURE_CARRY_FLAG = "ENABLED",
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parameter FEATURE_FASTCONTEXTS = "NONE",
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parameter OPTION_RF_CLEAR_ON_INIT = 0,
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parameter OPTION_RF_NUM_SHADOW_GPR = 0,
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parameter OPTION_RF_ADDR_WIDTH = 5,
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parameter OPTION_RF_WORDS = 32,
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parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
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`OR1K_RESET_VECTOR,8'd0},
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parameter FEATURE_MULTIPLIER = "THREESTAGE",
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parameter FEATURE_DIVIDER = "NONE",
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parameter OPTION_SHIFTER = "BARREL",
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parameter FEATURE_ADDC = "NONE",
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parameter FEATURE_SRA = "ENABLED",
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parameter FEATURE_ROR = "NONE",
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parameter FEATURE_EXT = "NONE",
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parameter FEATURE_CMOV = "NONE",
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parameter FEATURE_FFL1 = "NONE",
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parameter FEATURE_MSYNC = "ENABLED",
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parameter FEATURE_PSYNC = "NONE",
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parameter FEATURE_CSYNC = "NONE",
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parameter FEATURE_ATOMIC = "ENABLED",
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parameter FEATURE_FPU = "NONE", // ENABLED|NONE
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parameter FEATURE_CUST1 = "NONE",
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parameter FEATURE_CUST2 = "NONE",
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parameter FEATURE_CUST3 = "NONE",
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parameter FEATURE_CUST4 = "NONE",
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parameter FEATURE_CUST5 = "NONE",
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parameter FEATURE_CUST6 = "NONE",
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parameter FEATURE_CUST7 = "NONE",
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parameter FEATURE_CUST8 = "NONE",
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parameter FEATURE_STORE_BUFFER = "ENABLED",
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parameter OPTION_STORE_BUFFER_DEPTH_WIDTH = 8,
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parameter FEATURE_MULTICORE = "NONE",
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parameter FEATURE_TRACEPORT_EXEC = "NONE",
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parameter FEATURE_BRANCH_PREDICTOR = "SIMPLE" // SIMPLE|SAT_COUNTER|GSHARE
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)
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(
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input clk,
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input rst,
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// Instruction bus
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input ibus_err_i,
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input ibus_ack_i,
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input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i,
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output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o,
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output ibus_req_o,
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output ibus_burst_o,
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// Data bus
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input dbus_err_i,
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input dbus_ack_i,
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input [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i,
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output [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o,
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output [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o,
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output dbus_req_o,
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output [3:0] dbus_bsel_o,
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output dbus_we_o,
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output dbus_burst_o,
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// Interrupts
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input [31:0] irq_i,
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// Debug interface
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input [15:0] du_addr_i,
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input du_stb_i,
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input [OPTION_OPERAND_WIDTH-1:0] du_dat_i,
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input du_we_i,
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output [OPTION_OPERAND_WIDTH-1:0] du_dat_o,
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output du_ack_o,
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// Stall control from debug interface
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input du_stall_i,
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output du_stall_o,
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output reg traceport_exec_valid_o,
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output reg [31:0] traceport_exec_pc_o,
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output reg traceport_exec_jb_o,
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output reg traceport_exec_jal_o,
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output reg traceport_exec_jr_o,
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output reg [31:0] traceport_exec_jbtarget_o,
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output reg [`OR1K_INSN_WIDTH-1:0] traceport_exec_insn_o,
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output [OPTION_OPERAND_WIDTH-1:0] traceport_exec_wbdata_o,
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output [OPTION_RF_ADDR_WIDTH-1:0] traceport_exec_wbreg_o,
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output traceport_exec_wben_o,
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// SPR accesses to external units (cache, mmu, etc.)
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output [15:0] spr_bus_addr_o,
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output spr_bus_we_o,
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output spr_bus_stb_o,
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output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_mac_i,
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input spr_bus_ack_mac_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pmu_i,
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input spr_bus_ack_pmu_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_pcu_i,
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input spr_bus_ack_pcu_i,
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_fpu_i,
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input spr_bus_ack_fpu_i,
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output [15:0] spr_sr_o,
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input [OPTION_OPERAND_WIDTH-1:0] multicore_coreid_i,
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input [OPTION_OPERAND_WIDTH-1:0] multicore_numcores_i,
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input [31:0] snoop_adr_i,
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input snoop_en_i
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);
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wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_to_decode;
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wire [`OR1K_INSN_WIDTH-1:0] insn_fetch_to_decode;
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wire [OPTION_OPERAND_WIDTH-1:0] pc_decode_to_execute;
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wire [OPTION_OPERAND_WIDTH-1:0] pc_execute_to_ctrl;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [OPTION_OPERAND_WIDTH-1:0] adder_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire [OPTION_OPERAND_WIDTH-1:0] alu_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire alu_valid_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire atomic_flag_clear_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
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wire atomic_flag_set_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
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wire branch_mispredict_o; // From mor1kx_branch_prediction of mor1kx_branch_prediction.v
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wire carry_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire carry_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
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wire [OPTION_OPERAND_WIDTH-1:0] ctrl_alu_result_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire [OPTION_OPERAND_WIDTH-1:0] ctrl_branch_except_pc_o;// From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
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wire ctrl_branch_exception_o;// From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
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wire ctrl_bubble_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
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wire ctrl_carry_clear_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_carry_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
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wire ctrl_carry_set_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire [OPTION_OPERAND_WIDTH-1:0] ctrl_epcr_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
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wire ctrl_except_align_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_except_dbus_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_except_dpagefault_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_except_dtlb_miss_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_except_ibus_align_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_except_ibus_err_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_except_illegal_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_except_ipagefault_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_except_itlb_miss_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_except_syscall_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_except_trap_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_flag_clear_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_flag_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
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wire ctrl_flag_set_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire [OPTION_OPERAND_WIDTH-1:0] ctrl_lsu_adr_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire [1:0] ctrl_lsu_length_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_lsu_zext_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_mfspr_ack_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
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wire ctrl_mtspr_ack_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
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wire ctrl_op_lsu_atomic_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_op_lsu_load_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_op_lsu_store_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_op_mfspr_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_op_msync_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_op_mtspr_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_op_mul_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_op_rfe_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_overflow_clear_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_overflow_set_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire [`OR1K_FPCSR_WIDTH-1:0] ctrl_fpcsr_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_fpcsr_set_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire [`OR1K_FPCSR_RM_SIZE-1:0] ctrl_fpu_round_mode_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
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wire ctrl_rf_wb_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire [OPTION_OPERAND_WIDTH-1:0] ctrl_rfb_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire [OPTION_RF_ADDR_WIDTH-1:0] ctrl_rfd_adr_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire ctrl_valid_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
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wire decode_adder_do_carry_o;// From mor1kx_decode of mor1kx_decode.v
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wire decode_adder_do_sub_o; // From mor1kx_decode of mor1kx_decode.v
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wire decode_branch_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
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wire [OPTION_OPERAND_WIDTH-1:0] decode_branch_target_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
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wire decode_bubble_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
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wire decode_except_ibus_err_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
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wire decode_except_illegal_o;// From mor1kx_decode of mor1kx_decode.v
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wire decode_except_ipagefault_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
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wire decode_except_itlb_miss_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
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wire decode_except_syscall_o;// From mor1kx_decode of mor1kx_decode.v
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wire decode_except_trap_o; // From mor1kx_decode of mor1kx_decode.v
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wire [`OR1K_IMM_WIDTH-1:0] decode_imm16_o; // From mor1kx_decode of mor1kx_decode.v
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wire [OPTION_OPERAND_WIDTH-1:0] decode_immediate_o;// From mor1kx_decode of mor1kx_decode.v
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wire decode_immediate_sel_o; // From mor1kx_decode of mor1kx_decode.v
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246 |
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|
wire [9:0] decode_immjbr_upper_o; // From mor1kx_decode of mor1kx_decode.v
|
247 |
|
|
wire [1:0] decode_lsu_length_o; // From mor1kx_decode of mor1kx_decode.v
|
248 |
|
|
wire decode_lsu_zext_o; // From mor1kx_decode of mor1kx_decode.v
|
249 |
|
|
wire decode_op_add_o; // From mor1kx_decode of mor1kx_decode.v
|
250 |
|
|
wire decode_op_alu_o; // From mor1kx_decode of mor1kx_decode.v
|
251 |
|
|
wire decode_op_bf_o; // From mor1kx_decode of mor1kx_decode.v
|
252 |
|
|
wire decode_op_bnf_o; // From mor1kx_decode of mor1kx_decode.v
|
253 |
|
|
wire decode_op_branch_o; // From mor1kx_decode of mor1kx_decode.v
|
254 |
|
|
wire decode_op_brcond_o; // From mor1kx_decode of mor1kx_decode.v
|
255 |
|
|
wire decode_op_div_o; // From mor1kx_decode of mor1kx_decode.v
|
256 |
|
|
wire decode_op_div_signed_o; // From mor1kx_decode of mor1kx_decode.v
|
257 |
|
|
wire decode_op_div_unsigned_o;// From mor1kx_decode of mor1kx_decode.v
|
258 |
|
|
wire decode_op_ffl1_o; // From mor1kx_decode of mor1kx_decode.v
|
259 |
|
|
wire decode_op_jal_o; // From mor1kx_decode of mor1kx_decode.v
|
260 |
|
|
wire decode_op_jbr_o; // From mor1kx_decode of mor1kx_decode.v
|
261 |
|
|
wire decode_op_jr_o; // From mor1kx_decode of mor1kx_decode.v
|
262 |
|
|
wire decode_op_lsu_atomic_o; // From mor1kx_decode of mor1kx_decode.v
|
263 |
|
|
wire decode_op_lsu_load_o; // From mor1kx_decode of mor1kx_decode.v
|
264 |
|
|
wire decode_op_lsu_store_o; // From mor1kx_decode of mor1kx_decode.v
|
265 |
|
|
wire decode_op_mfspr_o; // From mor1kx_decode of mor1kx_decode.v
|
266 |
|
|
wire decode_op_movhi_o; // From mor1kx_decode of mor1kx_decode.v
|
267 |
|
|
wire decode_op_ext_o; // From mor1kx_decode of mor1kx_decode.v
|
268 |
|
|
wire decode_op_msync_o; // From mor1kx_decode of mor1kx_decode.v
|
269 |
|
|
wire [`OR1K_FPUOP_WIDTH-1:0] decode_op_fpu_o; // From mor1kx_decode of mor1kx_decode.v
|
270 |
|
|
wire decode_op_mtspr_o; // From mor1kx_decode of mor1kx_decode.v
|
271 |
|
|
wire decode_op_mul_o; // From mor1kx_decode of mor1kx_decode.v
|
272 |
|
|
wire decode_op_mul_signed_o; // From mor1kx_decode of mor1kx_decode.v
|
273 |
|
|
wire decode_op_mul_unsigned_o;// From mor1kx_decode of mor1kx_decode.v
|
274 |
|
|
wire decode_op_rfe_o; // From mor1kx_decode of mor1kx_decode.v
|
275 |
|
|
wire decode_op_setflag_o; // From mor1kx_decode of mor1kx_decode.v
|
276 |
|
|
wire decode_op_shift_o; // From mor1kx_decode of mor1kx_decode.v
|
277 |
|
|
wire [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_o;// From mor1kx_decode of mor1kx_decode.v
|
278 |
|
|
wire [`OR1K_ALU_OPC_WIDTH-1:0] decode_opc_alu_secondary_o;// From mor1kx_decode of mor1kx_decode.v
|
279 |
|
|
wire [`OR1K_OPCODE_WIDTH-1:0] decode_opc_insn_o;// From mor1kx_decode of mor1kx_decode.v
|
280 |
|
|
wire decode_rf_wb_o; // From mor1kx_decode of mor1kx_decode.v
|
281 |
|
|
wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfa_adr_o;// From mor1kx_decode of mor1kx_decode.v
|
282 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] decode_rfa_o;// From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v
|
283 |
|
|
wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfb_adr_o;// From mor1kx_decode of mor1kx_decode.v
|
284 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] decode_rfb_o;// From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v
|
285 |
|
|
wire [OPTION_RF_ADDR_WIDTH-1:0] decode_rfd_adr_o;// From mor1kx_decode of mor1kx_decode.v
|
286 |
|
|
wire decode_valid_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
287 |
|
|
wire doing_rfe_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
|
288 |
|
|
wire du_restart_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
|
289 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_o;// From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
|
290 |
|
|
wire execute_adder_do_carry_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
291 |
|
|
wire execute_adder_do_sub_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
292 |
|
|
wire execute_bubble_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
293 |
|
|
wire execute_except_ibus_align_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
294 |
|
|
wire execute_except_ibus_err_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
295 |
|
|
wire execute_except_illegal_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
296 |
|
|
wire execute_except_ipagefault_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
297 |
|
|
wire execute_except_itlb_miss_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
298 |
|
|
wire execute_except_syscall_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
299 |
|
|
wire execute_except_trap_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
300 |
|
|
wire [`OR1K_IMM_WIDTH-1:0] execute_imm16_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
301 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] execute_immediate_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
302 |
|
|
wire execute_immediate_sel_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
303 |
|
|
wire [9:0] execute_immjbr_upper_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
304 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] execute_jal_result_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
305 |
|
|
wire [1:0] execute_lsu_length_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
306 |
|
|
wire execute_lsu_zext_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
307 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] execute_mispredict_target_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
308 |
|
|
wire execute_op_add_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
309 |
|
|
wire execute_op_alu_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
310 |
|
|
wire execute_op_bf_o;
|
311 |
|
|
wire execute_op_bnf_o;
|
312 |
|
|
wire execute_op_branch_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
313 |
|
|
wire execute_op_brcond_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
314 |
|
|
wire execute_op_div_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
315 |
|
|
wire execute_op_div_signed_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
316 |
|
|
wire execute_op_div_unsigned_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
317 |
|
|
wire execute_op_ffl1_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
318 |
|
|
wire execute_op_jal_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
319 |
|
|
wire execute_op_jbr_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
320 |
|
|
wire execute_op_jr_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
321 |
|
|
wire execute_op_lsu_atomic_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
322 |
|
|
wire execute_op_lsu_load_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
323 |
|
|
wire execute_op_lsu_store_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
324 |
|
|
wire execute_op_mfspr_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
325 |
|
|
wire execute_op_movhi_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
326 |
|
|
wire execute_op_ext_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
327 |
|
|
wire execute_op_msync_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
328 |
|
|
wire [`OR1K_FPUOP_WIDTH-1:0] execute_op_fpu_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
329 |
|
|
wire execute_op_mtspr_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
330 |
|
|
wire execute_op_mul_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
331 |
|
|
wire execute_op_mul_signed_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
332 |
|
|
wire execute_op_mul_unsigned_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
333 |
|
|
wire execute_op_rfe_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
334 |
|
|
wire execute_op_setflag_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
335 |
|
|
wire execute_op_shift_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
336 |
|
|
wire [`OR1K_ALU_OPC_WIDTH-1:0] execute_opc_alu_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
337 |
|
|
wire [`OR1K_ALU_OPC_WIDTH-1:0] execute_opc_alu_secondary_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
338 |
|
|
wire [`OR1K_OPCODE_WIDTH-1:0] execute_opc_insn_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
339 |
|
|
wire execute_predicted_flag_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
340 |
|
|
wire execute_rf_wb_o; // From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
341 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] execute_rfa_o;// From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v
|
342 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] execute_rfb_o;// From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v
|
343 |
|
|
wire [OPTION_RF_ADDR_WIDTH-1:0] execute_rfd_adr_o;// From mor1kx_decode_execute_cappuccino of mor1kx_decode_execute_cappuccino.v
|
344 |
|
|
wire execute_valid_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
|
345 |
|
|
wire fetch_exception_taken_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
|
346 |
|
|
wire fetch_rf_adr_valid_o; // From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
|
347 |
|
|
wire [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
|
348 |
|
|
wire [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
|
349 |
|
|
wire fetch_valid_o; // From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
|
350 |
|
|
wire flag_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
|
351 |
|
|
wire flag_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
|
352 |
|
|
wire icache_hit_o; // From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
|
353 |
|
|
wire dcache_hit_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
354 |
|
|
wire lsu_except_align_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
355 |
|
|
wire lsu_except_dbus_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
356 |
|
|
wire lsu_except_dpagefault_o;// From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
357 |
|
|
wire lsu_except_dtlb_miss_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
358 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] lsu_result_o;// From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
359 |
|
|
wire lsu_valid_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
360 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] mfspr_dat_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
|
361 |
|
|
wire msync_stall_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
362 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] mul_result_o;// From mor1kx_execute_alu of mor1kx_execute_alu.v
|
363 |
|
|
wire overflow_clear_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
|
364 |
|
|
wire overflow_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
|
365 |
|
|
wire[`OR1K_FPCSR_WIDTH-1:0] fpcsr_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
|
366 |
|
|
wire fpcsr_set_o; // From mor1kx_execute_alu of mor1kx_execute_alu.v
|
367 |
|
|
wire padv_ctrl_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
|
368 |
|
|
wire padv_decode_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
|
369 |
|
|
wire padv_execute_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
|
370 |
|
|
wire padv_fetch_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
|
371 |
|
|
wire pipeline_flush_o; // From mor1kx_ctrl_cappuccino of mor1kx_ctrl_cappuccino.v
|
372 |
|
|
wire predicted_flag_o; // From mor1kx_branch_prediction of mor1kx_branch_prediction.v
|
373 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] rf_result_o; // From mor1kx_wb_mux_cappuccino of mor1kx_wb_mux_cappuccino.v
|
374 |
|
|
wire spr_bus_ack_dc_i; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
375 |
|
|
wire spr_bus_ack_dmmu_i; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
376 |
|
|
wire spr_bus_ack_ic_i; // From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
|
377 |
|
|
wire spr_bus_ack_immu_i; // From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
|
378 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dc_i;// From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
379 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_dmmu_i;// From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
380 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_i;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
|
381 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_immu_i;// From mor1kx_fetch_cappuccino of mor1kx_fetch_cappuccino.v
|
382 |
|
|
wire spr_gpr_ack_o; // From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v
|
383 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] spr_gpr_dat_o;// From mor1kx_rf_cappuccino of mor1kx_rf_cappuccino.v
|
384 |
|
|
wire [OPTION_OPERAND_WIDTH-1:0] store_buffer_epcr_o;// From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
385 |
|
|
wire store_buffer_err_o; // From mor1kx_lsu_cappuccino of mor1kx_lsu_cappuccino.v
|
386 |
|
|
wire wb_rf_wb_o; // From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
|
387 |
|
|
wire [OPTION_RF_ADDR_WIDTH-1:0] wb_rfd_adr_o;// From mor1kx_execute_ctrl_cappuccino of mor1kx_execute_ctrl_cappuccino.v
|
388 |
|
|
// End of automatics
|
389 |
|
|
|
390 |
|
|
/* mor1kx_fetch_cappuccino AUTO_TEMPLATE (
|
391 |
|
|
.padv_i (padv_fetch_o),
|
392 |
|
|
.padv_ctrl_i (padv_ctrl_o),
|
393 |
|
|
.decode_branch_i (decode_branch_o),
|
394 |
|
|
.decode_branch_target_i (decode_branch_target_o),
|
395 |
|
|
.ctrl_branch_exception_i (ctrl_branch_exception_o),
|
396 |
|
|
.ctrl_branch_except_pc_i (ctrl_branch_except_pc_o),
|
397 |
|
|
.doing_rfe_i (doing_rfe_o),
|
398 |
|
|
.pipeline_flush_i (pipeline_flush_o),
|
399 |
|
|
.pc_decode_o (pc_fetch_to_decode),
|
400 |
|
|
.decode_insn_o (insn_fetch_to_decode),
|
401 |
|
|
.du_restart_pc_i (du_restart_pc_o),
|
402 |
|
|
.du_restart_i (du_restart_o),
|
403 |
|
|
.decode_op_brcond_i (decode_op_brcond_o),
|
404 |
|
|
.branch_mispredict_i (branch_mispredict_o),
|
405 |
|
|
.execute_mispredict_target_i (execute_mispredict_target_o),
|
406 |
|
|
.spr_bus_dat_ic_o (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]),
|
407 |
|
|
.spr_bus_ack_ic_o (spr_bus_ack_ic_i),
|
408 |
|
|
.spr_bus_dat_immu_o (spr_bus_dat_immu_i[OPTION_OPERAND_WIDTH-1:0]),
|
409 |
|
|
.spr_bus_ack_immu_o (spr_bus_ack_immu_i),
|
410 |
|
|
.spr_bus_addr_i (spr_bus_addr_o[15:0]),
|
411 |
|
|
.spr_bus_we_i (spr_bus_we_o),
|
412 |
|
|
.spr_bus_stb_i (spr_bus_stb_o),
|
413 |
|
|
.spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
414 |
|
|
.ic_enable (spr_sr_o[`OR1K_SPR_SR_ICE]),
|
415 |
|
|
.immu_enable_i (spr_sr_o[`OR1K_SPR_SR_IME]),
|
416 |
|
|
.supervisor_mode_i (spr_sr_o[`OR1K_SPR_SR_SM]),
|
417 |
|
|
); */
|
418 |
|
|
mor1kx_fetch_cappuccino
|
419 |
|
|
#(
|
420 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
421 |
|
|
.OPTION_RESET_PC(OPTION_RESET_PC),
|
422 |
|
|
.FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE),
|
423 |
|
|
.OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH),
|
424 |
|
|
.OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH),
|
425 |
|
|
.OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS),
|
426 |
|
|
.OPTION_ICACHE_LIMIT_WIDTH(OPTION_ICACHE_LIMIT_WIDTH),
|
427 |
|
|
.FEATURE_IMMU(FEATURE_IMMU),
|
428 |
|
|
.FEATURE_IMMU_HW_TLB_RELOAD(FEATURE_IMMU_HW_TLB_RELOAD),
|
429 |
|
|
.OPTION_IMMU_SET_WIDTH(OPTION_IMMU_SET_WIDTH),
|
430 |
|
|
.OPTION_IMMU_WAYS(OPTION_IMMU_WAYS)
|
431 |
|
|
)
|
432 |
|
|
mor1kx_fetch_cappuccino
|
433 |
|
|
(/*AUTOINST*/
|
434 |
|
|
// Outputs
|
435 |
|
|
.spr_bus_dat_ic_o (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]), // Templated
|
436 |
|
|
.spr_bus_ack_ic_o (spr_bus_ack_ic_i), // Templated
|
437 |
|
|
.spr_bus_dat_immu_o (spr_bus_dat_immu_i[OPTION_OPERAND_WIDTH-1:0]), // Templated
|
438 |
|
|
.spr_bus_ack_immu_o (spr_bus_ack_immu_i), // Templated
|
439 |
|
|
.ibus_req_o (ibus_req_o),
|
440 |
|
|
.ibus_adr_o (ibus_adr_o[OPTION_OPERAND_WIDTH-1:0]),
|
441 |
|
|
.ibus_burst_o (ibus_burst_o),
|
442 |
|
|
.pc_decode_o (pc_fetch_to_decode), // Templated
|
443 |
|
|
.decode_insn_o (insn_fetch_to_decode), // Templated
|
444 |
|
|
.fetch_valid_o (fetch_valid_o),
|
445 |
|
|
.fetch_rfa_adr_o (fetch_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
446 |
|
|
.fetch_rfb_adr_o (fetch_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
447 |
|
|
.fetch_rf_adr_valid_o (fetch_rf_adr_valid_o),
|
448 |
|
|
.decode_except_ibus_err_o (decode_except_ibus_err_o),
|
449 |
|
|
.decode_except_itlb_miss_o (decode_except_itlb_miss_o),
|
450 |
|
|
.decode_except_ipagefault_o (decode_except_ipagefault_o),
|
451 |
|
|
.fetch_exception_taken_o (fetch_exception_taken_o),
|
452 |
|
|
.ic_hit_o (icache_hit_o),
|
453 |
|
|
// Inputs
|
454 |
|
|
.clk (clk),
|
455 |
|
|
.rst (rst),
|
456 |
|
|
.spr_bus_addr_i (spr_bus_addr_o[15:0]), // Templated
|
457 |
|
|
.spr_bus_we_i (spr_bus_we_o), // Templated
|
458 |
|
|
.spr_bus_stb_i (spr_bus_stb_o), // Templated
|
459 |
|
|
.spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), // Templated
|
460 |
|
|
.ic_enable (spr_sr_o[`OR1K_SPR_SR_ICE]), // Templated
|
461 |
|
|
.immu_enable_i (spr_sr_o[`OR1K_SPR_SR_IME]), // Templated
|
462 |
|
|
.supervisor_mode_i (spr_sr_o[`OR1K_SPR_SR_SM]), // Templated
|
463 |
|
|
.ibus_err_i (ibus_err_i),
|
464 |
|
|
.ibus_ack_i (ibus_ack_i),
|
465 |
|
|
.ibus_dat_i (ibus_dat_i[`OR1K_INSN_WIDTH-1:0]),
|
466 |
|
|
.padv_i (padv_fetch_o), // Templated
|
467 |
|
|
.padv_ctrl_i (padv_ctrl_o), // Templated
|
468 |
|
|
.decode_branch_i (decode_branch_o), // Templated
|
469 |
|
|
.decode_branch_target_i (decode_branch_target_o), // Templated
|
470 |
|
|
.ctrl_branch_exception_i (ctrl_branch_exception_o), // Templated
|
471 |
|
|
.ctrl_branch_except_pc_i (ctrl_branch_except_pc_o), // Templated
|
472 |
|
|
.du_restart_i (du_restart_o), // Templated
|
473 |
|
|
.du_restart_pc_i (du_restart_pc_o), // Templated
|
474 |
|
|
.decode_op_brcond_i (decode_op_brcond_o), // Templated
|
475 |
|
|
.branch_mispredict_i (branch_mispredict_o), // Templated
|
476 |
|
|
.execute_mispredict_target_i (execute_mispredict_target_o), // Templated
|
477 |
|
|
.pipeline_flush_i (pipeline_flush_o), // Templated
|
478 |
|
|
.doing_rfe_i (doing_rfe_o)); // Templated
|
479 |
|
|
|
480 |
|
|
/* mor1kx_decode AUTO_TEMPLATE (
|
481 |
|
|
.decode_insn_i (insn_fetch_to_decode),
|
482 |
|
|
); */
|
483 |
|
|
mor1kx_decode
|
484 |
|
|
#(
|
485 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
486 |
|
|
.OPTION_RESET_PC(OPTION_RESET_PC),
|
487 |
|
|
.OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH),
|
488 |
|
|
.FEATURE_SYSCALL(FEATURE_SYSCALL),
|
489 |
|
|
.FEATURE_TRAP(FEATURE_TRAP),
|
490 |
|
|
.FEATURE_RANGE(FEATURE_RANGE),
|
491 |
|
|
.FEATURE_MAC(FEATURE_MAC),
|
492 |
|
|
.FEATURE_MULTIPLIER(FEATURE_MULTIPLIER),
|
493 |
|
|
.FEATURE_DIVIDER(FEATURE_DIVIDER),
|
494 |
|
|
.FEATURE_ADDC(FEATURE_ADDC),
|
495 |
|
|
.FEATURE_SRA(FEATURE_SRA),
|
496 |
|
|
.FEATURE_ROR(FEATURE_ROR),
|
497 |
|
|
.FEATURE_EXT(FEATURE_EXT),
|
498 |
|
|
.FEATURE_CMOV(FEATURE_CMOV),
|
499 |
|
|
.FEATURE_FFL1(FEATURE_FFL1),
|
500 |
|
|
.FEATURE_MSYNC(FEATURE_MSYNC),
|
501 |
|
|
.FEATURE_PSYNC(FEATURE_PSYNC),
|
502 |
|
|
.FEATURE_CSYNC(FEATURE_CSYNC),
|
503 |
|
|
.FEATURE_ATOMIC(FEATURE_ATOMIC),
|
504 |
|
|
.FEATURE_FPU(FEATURE_FPU), // pipeline cappuccino: decode instance
|
505 |
|
|
.FEATURE_CUST1(FEATURE_CUST1),
|
506 |
|
|
.FEATURE_CUST2(FEATURE_CUST2),
|
507 |
|
|
.FEATURE_CUST3(FEATURE_CUST3),
|
508 |
|
|
.FEATURE_CUST4(FEATURE_CUST4),
|
509 |
|
|
.FEATURE_CUST5(FEATURE_CUST5),
|
510 |
|
|
.FEATURE_CUST6(FEATURE_CUST6),
|
511 |
|
|
.FEATURE_CUST7(FEATURE_CUST7),
|
512 |
|
|
.FEATURE_CUST8(FEATURE_CUST8)
|
513 |
|
|
)
|
514 |
|
|
mor1kx_decode
|
515 |
|
|
(/*AUTOINST*/
|
516 |
|
|
// Outputs
|
517 |
|
|
.decode_opc_alu_o (decode_opc_alu_o[`OR1K_ALU_OPC_WIDTH-1:0]),
|
518 |
|
|
.decode_opc_alu_secondary_o (decode_opc_alu_secondary_o[`OR1K_ALU_OPC_WIDTH-1:0]),
|
519 |
|
|
.decode_imm16_o (decode_imm16_o[`OR1K_IMM_WIDTH-1:0]),
|
520 |
|
|
.decode_immediate_o (decode_immediate_o[OPTION_OPERAND_WIDTH-1:0]),
|
521 |
|
|
.decode_immediate_sel_o (decode_immediate_sel_o),
|
522 |
|
|
.decode_immjbr_upper_o (decode_immjbr_upper_o[9:0]),
|
523 |
|
|
.decode_rfd_adr_o (decode_rfd_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
524 |
|
|
.decode_rfa_adr_o (decode_rfa_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
525 |
|
|
.decode_rfb_adr_o (decode_rfb_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
526 |
|
|
.decode_rf_wb_o (decode_rf_wb_o),
|
527 |
|
|
.decode_op_jbr_o (decode_op_jbr_o),
|
528 |
|
|
.decode_op_jr_o (decode_op_jr_o),
|
529 |
|
|
.decode_op_jal_o (decode_op_jal_o),
|
530 |
|
|
.decode_op_bf_o (decode_op_bf_o),
|
531 |
|
|
.decode_op_bnf_o (decode_op_bnf_o),
|
532 |
|
|
.decode_op_brcond_o (decode_op_brcond_o),
|
533 |
|
|
.decode_op_branch_o (decode_op_branch_o),
|
534 |
|
|
.decode_op_alu_o (decode_op_alu_o),
|
535 |
|
|
.decode_op_lsu_load_o (decode_op_lsu_load_o),
|
536 |
|
|
.decode_op_lsu_store_o (decode_op_lsu_store_o),
|
537 |
|
|
.decode_op_lsu_atomic_o (decode_op_lsu_atomic_o),
|
538 |
|
|
.decode_lsu_length_o (decode_lsu_length_o[1:0]),
|
539 |
|
|
.decode_lsu_zext_o (decode_lsu_zext_o),
|
540 |
|
|
.decode_op_mfspr_o (decode_op_mfspr_o),
|
541 |
|
|
.decode_op_mtspr_o (decode_op_mtspr_o),
|
542 |
|
|
.decode_op_rfe_o (decode_op_rfe_o),
|
543 |
|
|
.decode_op_setflag_o (decode_op_setflag_o),
|
544 |
|
|
.decode_op_add_o (decode_op_add_o),
|
545 |
|
|
.decode_op_mul_o (decode_op_mul_o),
|
546 |
|
|
.decode_op_mul_signed_o (decode_op_mul_signed_o),
|
547 |
|
|
.decode_op_mul_unsigned_o (decode_op_mul_unsigned_o),
|
548 |
|
|
.decode_op_div_o (decode_op_div_o),
|
549 |
|
|
.decode_op_div_signed_o (decode_op_div_signed_o),
|
550 |
|
|
.decode_op_div_unsigned_o (decode_op_div_unsigned_o),
|
551 |
|
|
.decode_op_shift_o (decode_op_shift_o),
|
552 |
|
|
.decode_op_ffl1_o (decode_op_ffl1_o),
|
553 |
|
|
.decode_op_movhi_o (decode_op_movhi_o),
|
554 |
|
|
.decode_op_ext_o (decode_op_ext_o),
|
555 |
|
|
.decode_op_msync_o (decode_op_msync_o),
|
556 |
|
|
.decode_op_fpu_o (decode_op_fpu_o),
|
557 |
|
|
.decode_adder_do_sub_o (decode_adder_do_sub_o),
|
558 |
|
|
.decode_adder_do_carry_o (decode_adder_do_carry_o),
|
559 |
|
|
.decode_except_illegal_o (decode_except_illegal_o),
|
560 |
|
|
.decode_except_syscall_o (decode_except_syscall_o),
|
561 |
|
|
.decode_except_trap_o (decode_except_trap_o),
|
562 |
|
|
.decode_opc_insn_o (decode_opc_insn_o[`OR1K_OPCODE_WIDTH-1:0]),
|
563 |
|
|
// Inputs
|
564 |
|
|
.clk (clk),
|
565 |
|
|
.rst (rst),
|
566 |
|
|
.decode_insn_i (insn_fetch_to_decode)); // Templated
|
567 |
|
|
|
568 |
|
|
/* mor1kx_decode_execute_cappuccino AUTO_TEMPLATE (
|
569 |
|
|
.padv_i (padv_decode_o),
|
570 |
|
|
.pc_decode_i (pc_fetch_to_decode),
|
571 |
|
|
.decode_rfb_i (decode_rfb_o),
|
572 |
|
|
.execute_rfb_i (execute_rfb_o),
|
573 |
|
|
.predicted_flag_i (predicted_flag_o),
|
574 |
|
|
.flag_i (ctrl_flag_o),
|
575 |
|
|
.pc_execute_o (pc_decode_to_execute),
|
576 |
|
|
.pipeline_flush_i (pipeline_flush_o),
|
577 |
|
|
.decode_opc_alu_i (decode_opc_alu_o),
|
578 |
|
|
.decode_opc_alu_secondary_i (decode_opc_alu_secondary_o),
|
579 |
|
|
.decode_imm16_i (decode_imm16_o),
|
580 |
|
|
.decode_immediate_i (decode_immediate_o),
|
581 |
|
|
.decode_immediate_sel_i (decode_immediate_sel_o),
|
582 |
|
|
.decode_immjbr_upper_i (decode_immjbr_upper_o),
|
583 |
|
|
.decode_adder_do_sub_i (decode_adder_do_sub_o),
|
584 |
|
|
.decode_adder_do_carry_i (decode_adder_do_carry_o),
|
585 |
|
|
.decode_rfd_adr_i (decode_rfd_adr_o),
|
586 |
|
|
.decode_rfa_adr_i (decode_rfa_adr_o),
|
587 |
|
|
.decode_rfb_adr_i (decode_rfb_adr_o),
|
588 |
|
|
.ctrl_rfd_adr_i (ctrl_rfd_adr_o),
|
589 |
|
|
.ctrl_op_lsu_load_i (ctrl_op_lsu_load_o),
|
590 |
|
|
.ctrl_op_mfspr_i (ctrl_op_mfspr_o),
|
591 |
|
|
.ctrl_op_mul_i (ctrl_op_mul_o),
|
592 |
|
|
.decode_rf_wb_i (decode_rf_wb_o),
|
593 |
|
|
.decode_op_alu_i (decode_op_alu_o),
|
594 |
|
|
.decode_op_setflag_i (decode_op_setflag_o),
|
595 |
|
|
.decode_op_jbr_i (decode_op_jbr_o),
|
596 |
|
|
.decode_op_jr_i (decode_op_jr_o),
|
597 |
|
|
.decode_op_jal_i (decode_op_jal_o),
|
598 |
|
|
.decode_op_bf_i (decode_op_bf_o),
|
599 |
|
|
.decode_op_bnf_i (decode_op_bnf_o),
|
600 |
|
|
.decode_op_brcond_i (decode_op_brcond_o),
|
601 |
|
|
.decode_op_branch_i (decode_op_branch_o),
|
602 |
|
|
.decode_op_lsu_load_i (decode_op_lsu_load_o),
|
603 |
|
|
.decode_op_lsu_store_i (decode_op_lsu_store_o),
|
604 |
|
|
.decode_op_lsu_atomic_i (decode_op_lsu_atomic_o),
|
605 |
|
|
.decode_lsu_length_i (decode_lsu_length_o[1:0]),
|
606 |
|
|
.decode_lsu_zext_i (decode_lsu_zext_o),
|
607 |
|
|
.decode_op_mfspr_i (decode_op_mfspr_o),
|
608 |
|
|
.decode_op_mtspr_i (decode_op_mtspr_o),
|
609 |
|
|
.decode_op_rfe_i (decode_op_rfe_o),
|
610 |
|
|
.decode_op_add_i (decode_op_add_o),
|
611 |
|
|
.decode_op_mul_i (decode_op_mul_o),
|
612 |
|
|
.decode_op_mul_signed_i (decode_op_mul_signed_o),
|
613 |
|
|
.decode_op_mul_unsigned_i (decode_op_mul_unsigned_o),
|
614 |
|
|
.decode_op_div_i (decode_op_div_o),
|
615 |
|
|
.decode_op_div_signed_i (decode_op_div_signed_o),
|
616 |
|
|
.decode_op_div_unsigned_i (decode_op_div_unsigned_o),
|
617 |
|
|
.decode_op_shift_i (decode_op_shift_o),
|
618 |
|
|
.decode_op_ffl1_i (decode_op_ffl1_o),
|
619 |
|
|
.decode_op_movhi_i (decode_op_movhi_o),
|
620 |
|
|
.decode_op_msync_i (decode_op_msync_o),
|
621 |
|
|
.decode_op_fpu_i (decode_op_fpu_o),
|
622 |
|
|
.decode_opc_insn_i (decode_opc_insn_o[`OR1K_OPCODE_WIDTH-1:0]),
|
623 |
|
|
.decode_except_ibus_err_i (decode_except_ibus_err_o),
|
624 |
|
|
.decode_except_itlb_miss_i (decode_except_itlb_miss_o),
|
625 |
|
|
.decode_except_ipagefault_i (decode_except_ipagefault_o),
|
626 |
|
|
.decode_except_illegal_i (decode_except_illegal_o),
|
627 |
|
|
.decode_except_syscall_i (decode_except_syscall_o),
|
628 |
|
|
.decode_except_trap_i (decode_except_trap_o),
|
629 |
|
|
); */
|
630 |
|
|
mor1kx_decode_execute_cappuccino
|
631 |
|
|
#(
|
632 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
633 |
|
|
.OPTION_RESET_PC(OPTION_RESET_PC),
|
634 |
|
|
.OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH),
|
635 |
|
|
.FEATURE_SYSCALL(FEATURE_SYSCALL),
|
636 |
|
|
.FEATURE_TRAP(FEATURE_TRAP),
|
637 |
|
|
.FEATURE_FPU(FEATURE_FPU), // pipeline cappuccino: decode_execute instance
|
638 |
|
|
.FEATURE_MULTIPLIER(FEATURE_MULTIPLIER)
|
639 |
|
|
)
|
640 |
|
|
mor1kx_decode_execute_cappuccino
|
641 |
|
|
(/*AUTOINST*/
|
642 |
|
|
// Outputs
|
643 |
|
|
.execute_predicted_flag_o (execute_predicted_flag_o),
|
644 |
|
|
.execute_mispredict_target_o (execute_mispredict_target_o[OPTION_OPERAND_WIDTH-1:0]),
|
645 |
|
|
.execute_opc_alu_o (execute_opc_alu_o[`OR1K_ALU_OPC_WIDTH-1:0]),
|
646 |
|
|
.execute_opc_alu_secondary_o (execute_opc_alu_secondary_o[`OR1K_ALU_OPC_WIDTH-1:0]),
|
647 |
|
|
.execute_imm16_o (execute_imm16_o[`OR1K_IMM_WIDTH-1:0]),
|
648 |
|
|
.execute_immediate_o (execute_immediate_o[OPTION_OPERAND_WIDTH-1:0]),
|
649 |
|
|
.execute_immediate_sel_o (execute_immediate_sel_o),
|
650 |
|
|
.execute_adder_do_sub_o (execute_adder_do_sub_o),
|
651 |
|
|
.execute_adder_do_carry_o (execute_adder_do_carry_o),
|
652 |
|
|
.execute_immjbr_upper_o (execute_immjbr_upper_o[9:0]),
|
653 |
|
|
.execute_rfd_adr_o (execute_rfd_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
654 |
|
|
.execute_rf_wb_o (execute_rf_wb_o),
|
655 |
|
|
.execute_op_alu_o (execute_op_alu_o),
|
656 |
|
|
.execute_op_setflag_o (execute_op_setflag_o),
|
657 |
|
|
.execute_op_jbr_o (execute_op_jbr_o),
|
658 |
|
|
.execute_op_jr_o (execute_op_jr_o),
|
659 |
|
|
.execute_op_jal_o (execute_op_jal_o),
|
660 |
|
|
.execute_op_brcond_o (execute_op_brcond_o),
|
661 |
|
|
.execute_op_branch_o (execute_op_branch_o),
|
662 |
|
|
.execute_op_lsu_load_o (execute_op_lsu_load_o),
|
663 |
|
|
.execute_op_lsu_store_o (execute_op_lsu_store_o),
|
664 |
|
|
.execute_op_lsu_atomic_o (execute_op_lsu_atomic_o),
|
665 |
|
|
.execute_lsu_length_o (execute_lsu_length_o[1:0]),
|
666 |
|
|
.execute_lsu_zext_o (execute_lsu_zext_o),
|
667 |
|
|
.execute_op_mfspr_o (execute_op_mfspr_o),
|
668 |
|
|
.execute_op_mtspr_o (execute_op_mtspr_o),
|
669 |
|
|
.execute_op_rfe_o (execute_op_rfe_o),
|
670 |
|
|
.execute_op_add_o (execute_op_add_o),
|
671 |
|
|
.execute_op_mul_o (execute_op_mul_o),
|
672 |
|
|
.execute_op_mul_signed_o (execute_op_mul_signed_o),
|
673 |
|
|
.execute_op_mul_unsigned_o (execute_op_mul_unsigned_o),
|
674 |
|
|
.execute_op_div_o (execute_op_div_o),
|
675 |
|
|
.execute_op_div_signed_o (execute_op_div_signed_o),
|
676 |
|
|
.execute_op_div_unsigned_o (execute_op_div_unsigned_o),
|
677 |
|
|
.execute_op_shift_o (execute_op_shift_o),
|
678 |
|
|
.execute_op_ffl1_o (execute_op_ffl1_o),
|
679 |
|
|
.execute_op_movhi_o (execute_op_movhi_o),
|
680 |
|
|
.execute_op_ext_o (execute_op_ext_o),
|
681 |
|
|
.execute_op_msync_o (execute_op_msync_o),
|
682 |
|
|
.execute_op_fpu_o (execute_op_fpu_o),
|
683 |
|
|
.execute_op_bf_o (execute_op_bf_o),
|
684 |
|
|
.execute_op_bnf_o (execute_op_bnf_o),
|
685 |
|
|
.execute_jal_result_o (execute_jal_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
686 |
|
|
.execute_opc_insn_o (execute_opc_insn_o[`OR1K_OPCODE_WIDTH-1:0]),
|
687 |
|
|
.decode_branch_o (decode_branch_o),
|
688 |
|
|
.decode_branch_target_o (decode_branch_target_o[OPTION_OPERAND_WIDTH-1:0]),
|
689 |
|
|
.execute_except_ibus_err_o (execute_except_ibus_err_o),
|
690 |
|
|
.execute_except_itlb_miss_o (execute_except_itlb_miss_o),
|
691 |
|
|
.execute_except_ipagefault_o (execute_except_ipagefault_o),
|
692 |
|
|
.execute_except_illegal_o (execute_except_illegal_o),
|
693 |
|
|
.execute_except_ibus_align_o (execute_except_ibus_align_o),
|
694 |
|
|
.execute_except_syscall_o (execute_except_syscall_o),
|
695 |
|
|
.execute_except_trap_o (execute_except_trap_o),
|
696 |
|
|
.pc_execute_o (pc_decode_to_execute), // Templated
|
697 |
|
|
.decode_valid_o (decode_valid_o),
|
698 |
|
|
.decode_bubble_o (decode_bubble_o),
|
699 |
|
|
.execute_bubble_o (execute_bubble_o),
|
700 |
|
|
// Inputs
|
701 |
|
|
.clk (clk),
|
702 |
|
|
.rst (rst),
|
703 |
|
|
.padv_i (padv_decode_o), // Templated
|
704 |
|
|
.pc_decode_i (pc_fetch_to_decode), // Templated
|
705 |
|
|
.decode_rfb_i (decode_rfb_o), // Templated
|
706 |
|
|
.execute_rfb_i (execute_rfb_o), // Templated
|
707 |
|
|
.predicted_flag_i (predicted_flag_o), // Templated
|
708 |
|
|
.pipeline_flush_i (pipeline_flush_o), // Templated
|
709 |
|
|
.decode_opc_alu_i (decode_opc_alu_o), // Templated
|
710 |
|
|
.decode_opc_alu_secondary_i (decode_opc_alu_secondary_o), // Templated
|
711 |
|
|
.decode_imm16_i (decode_imm16_o), // Templated
|
712 |
|
|
.decode_immediate_i (decode_immediate_o), // Templated
|
713 |
|
|
.decode_immediate_sel_i (decode_immediate_sel_o), // Templated
|
714 |
|
|
.decode_adder_do_sub_i (decode_adder_do_sub_o), // Templated
|
715 |
|
|
.decode_adder_do_carry_i (decode_adder_do_carry_o), // Templated
|
716 |
|
|
.decode_immjbr_upper_i (decode_immjbr_upper_o), // Templated
|
717 |
|
|
.decode_rfd_adr_i (decode_rfd_adr_o), // Templated
|
718 |
|
|
.decode_rfa_adr_i (decode_rfa_adr_o), // Templated
|
719 |
|
|
.decode_rfb_adr_i (decode_rfb_adr_o), // Templated
|
720 |
|
|
.ctrl_rfd_adr_i (ctrl_rfd_adr_o), // Templated
|
721 |
|
|
.ctrl_op_lsu_load_i (ctrl_op_lsu_load_o), // Templated
|
722 |
|
|
.ctrl_op_mfspr_i (ctrl_op_mfspr_o), // Templated
|
723 |
|
|
.ctrl_op_mul_i (ctrl_op_mul_o), // Templated
|
724 |
|
|
.decode_rf_wb_i (decode_rf_wb_o), // Templated
|
725 |
|
|
.decode_op_alu_i (decode_op_alu_o), // Templated
|
726 |
|
|
.decode_op_setflag_i (decode_op_setflag_o), // Templated
|
727 |
|
|
.decode_op_jbr_i (decode_op_jbr_o), // Templated
|
728 |
|
|
.decode_op_jr_i (decode_op_jr_o), // Templated
|
729 |
|
|
.decode_op_jal_i (decode_op_jal_o), // Templated
|
730 |
|
|
.decode_op_bf_i (decode_op_bf_o), // Templated
|
731 |
|
|
.decode_op_bnf_i (decode_op_bnf_o), // Templated
|
732 |
|
|
.decode_op_brcond_i (decode_op_brcond_o), // Templated
|
733 |
|
|
.decode_op_branch_i (decode_op_branch_o), // Templated
|
734 |
|
|
.decode_op_lsu_load_i (decode_op_lsu_load_o), // Templated
|
735 |
|
|
.decode_op_lsu_store_i (decode_op_lsu_store_o), // Templated
|
736 |
|
|
.decode_op_lsu_atomic_i (decode_op_lsu_atomic_o), // Templated
|
737 |
|
|
.decode_lsu_length_i (decode_lsu_length_o[1:0]), // Templated
|
738 |
|
|
.decode_lsu_zext_i (decode_lsu_zext_o), // Templated
|
739 |
|
|
.decode_op_mfspr_i (decode_op_mfspr_o), // Templated
|
740 |
|
|
.decode_op_mtspr_i (decode_op_mtspr_o), // Templated
|
741 |
|
|
.decode_op_rfe_i (decode_op_rfe_o), // Templated
|
742 |
|
|
.decode_op_add_i (decode_op_add_o), // Templated
|
743 |
|
|
.decode_op_mul_i (decode_op_mul_o), // Templated
|
744 |
|
|
.decode_op_mul_signed_i (decode_op_mul_signed_o), // Templated
|
745 |
|
|
.decode_op_mul_unsigned_i (decode_op_mul_unsigned_o), // Templated
|
746 |
|
|
.decode_op_div_i (decode_op_div_o), // Templated
|
747 |
|
|
.decode_op_div_signed_i (decode_op_div_signed_o), // Templated
|
748 |
|
|
.decode_op_div_unsigned_i (decode_op_div_unsigned_o), // Templated
|
749 |
|
|
.decode_op_shift_i (decode_op_shift_o), // Templated
|
750 |
|
|
.decode_op_ffl1_i (decode_op_ffl1_o), // Templated
|
751 |
|
|
.decode_op_movhi_i (decode_op_movhi_o), // Templated
|
752 |
|
|
.decode_op_ext_i (decode_op_ext_o), // Templated
|
753 |
|
|
.decode_op_msync_i (decode_op_msync_o), // Templated
|
754 |
|
|
.decode_op_fpu_i (decode_op_fpu_o), // Templated
|
755 |
|
|
.decode_opc_insn_i (decode_opc_insn_o[`OR1K_OPCODE_WIDTH-1:0]), // Templated
|
756 |
|
|
.decode_except_ibus_err_i (decode_except_ibus_err_o), // Templated
|
757 |
|
|
.decode_except_itlb_miss_i (decode_except_itlb_miss_o), // Templated
|
758 |
|
|
.decode_except_ipagefault_i (decode_except_ipagefault_o), // Templated
|
759 |
|
|
.decode_except_illegal_i (decode_except_illegal_o), // Templated
|
760 |
|
|
.decode_except_syscall_i (decode_except_syscall_o), // Templated
|
761 |
|
|
.decode_except_trap_i (decode_except_trap_o)); // Templated
|
762 |
|
|
|
763 |
|
|
/* mor1kx_branch_prediction AUTO_TEMPLATE (
|
764 |
|
|
.op_bf_i (decode_op_bf_o),
|
765 |
|
|
.op_bnf_i (decode_op_bnf_o),
|
766 |
|
|
.execute_bf_i (execute_op_bf_o),
|
767 |
|
|
.execute_bnf_i (execute_op_bnf_o),
|
768 |
|
|
.padv_decode_i (padv_decode_o),
|
769 |
|
|
.immjbr_upper_i (decode_immjbr_upper_o),
|
770 |
|
|
.prev_op_brcond_i (execute_op_brcond_o),
|
771 |
|
|
.prev_predicted_flag_i (execute_predicted_flag_o),
|
772 |
|
|
.brn_pc_i (pc_fetch_to_decode),
|
773 |
|
|
.flag_i (ctrl_flag_o),
|
774 |
|
|
);*/
|
775 |
|
|
mor1kx_branch_prediction
|
776 |
|
|
#(
|
777 |
|
|
.FEATURE_BRANCH_PREDICTOR(FEATURE_BRANCH_PREDICTOR),
|
778 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
|
779 |
|
|
)
|
780 |
|
|
mor1kx_branch_prediction
|
781 |
|
|
(/*AUTOINST*/
|
782 |
|
|
// Outputs
|
783 |
|
|
.predicted_flag_o (predicted_flag_o),
|
784 |
|
|
.branch_mispredict_o (branch_mispredict_o),
|
785 |
|
|
// Inputs
|
786 |
|
|
.clk (clk),
|
787 |
|
|
.rst (rst),
|
788 |
|
|
.op_bf_i (decode_op_bf_o), // Templated
|
789 |
|
|
.op_bnf_i (decode_op_bnf_o), // Templated
|
790 |
|
|
.execute_bf_i (execute_op_bf_o), // Templated
|
791 |
|
|
.execute_bnf_i (execute_op_bnf_o), // Templated
|
792 |
|
|
.padv_decode_i (padv_decode_o), // Templated
|
793 |
|
|
.immjbr_upper_i (decode_immjbr_upper_o), // Templated
|
794 |
|
|
.prev_op_brcond_i (execute_op_brcond_o), // Templated
|
795 |
|
|
.prev_predicted_flag_i (execute_predicted_flag_o), // Templated
|
796 |
|
|
.brn_pc_i (pc_fetch_to_decode), // Templated
|
797 |
|
|
.flag_i (ctrl_flag_o)); // Templated
|
798 |
|
|
|
799 |
|
|
/* mor1kx_execute_alu AUTO_TEMPLATE (
|
800 |
|
|
.padv_decode_i (padv_decode_o),
|
801 |
|
|
.padv_execute_i (padv_execute_o),
|
802 |
|
|
.padv_ctrl_i (padv_ctrl_o),
|
803 |
|
|
.opc_alu_i (execute_opc_alu_o),
|
804 |
|
|
.opc_alu_secondary_i (execute_opc_alu_secondary_o),
|
805 |
|
|
.imm16_i (execute_imm16_o),
|
806 |
|
|
.decode_immediate_i (decode_immediate_o),
|
807 |
|
|
.decode_immediate_sel_i (decode_immediate_sel_o),
|
808 |
|
|
.immediate_i (execute_immediate_o),
|
809 |
|
|
.immediate_sel_i (execute_immediate_sel_o),
|
810 |
|
|
.decode_valid_i (decode_valid_o),
|
811 |
|
|
.decode_op_mul_i (decode_op_mul_o),
|
812 |
|
|
.op_alu_i (execute_op_alu_o),
|
813 |
|
|
.op_add_i (execute_op_add_o),
|
814 |
|
|
.op_mul_i (execute_op_mul_o),
|
815 |
|
|
.op_mul_signed_i (execute_op_mul_signed_o),
|
816 |
|
|
.op_mul_unsigned_i (execute_op_mul_unsigned_o),
|
817 |
|
|
.op_div_i (execute_op_div_o),
|
818 |
|
|
.op_div_signed_i (execute_op_div_signed_o),
|
819 |
|
|
.op_div_unsigned_i (execute_op_div_unsigned_o),
|
820 |
|
|
.op_shift_i (execute_op_shift_o),
|
821 |
|
|
.op_ffl1_i (execute_op_ffl1_o),
|
822 |
|
|
.op_setflag_i (execute_op_setflag_o),
|
823 |
|
|
.op_mtspr_i (execute_op_mtspr_o),
|
824 |
|
|
.op_mfspr_i (execute_op_mfspr_o),
|
825 |
|
|
.op_movhi_i (execute_op_movhi_o),
|
826 |
|
|
.op_fpu_i (execute_op_fpu_o),
|
827 |
|
|
.fpu_round_mode_i (ctrl_fpu_round_mode_o),
|
828 |
|
|
.op_jbr_i (execute_op_jbr_o),
|
829 |
|
|
.op_jr_i (execute_op_jr_o),
|
830 |
|
|
.immjbr_upper_i (execute_immjbr_upper_o),
|
831 |
|
|
.pc_execute_i (pc_decode_to_execute),
|
832 |
|
|
.adder_do_sub_i (execute_adder_do_sub_o),
|
833 |
|
|
.adder_do_carry_i (execute_adder_do_carry_o),
|
834 |
|
|
.decode_rfa_i (decode_rfa_o),
|
835 |
|
|
.decode_rfb_i (decode_rfb_o),
|
836 |
|
|
.rfa_i (execute_rfa_o),
|
837 |
|
|
.rfb_i (execute_rfb_o),
|
838 |
|
|
.flag_i (ctrl_flag_o),
|
839 |
|
|
.carry_i (ctrl_carry_o),
|
840 |
|
|
); */
|
841 |
|
|
mor1kx_execute_alu
|
842 |
|
|
#(
|
843 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
844 |
|
|
.FEATURE_OVERFLOW(FEATURE_OVERFLOW),
|
845 |
|
|
.FEATURE_CARRY_FLAG(FEATURE_CARRY_FLAG),
|
846 |
|
|
.FEATURE_MULTIPLIER(FEATURE_MULTIPLIER),
|
847 |
|
|
.FEATURE_DIVIDER(FEATURE_DIVIDER),
|
848 |
|
|
.FEATURE_ADDC(FEATURE_ADDC),
|
849 |
|
|
.FEATURE_SRA(FEATURE_SRA),
|
850 |
|
|
.FEATURE_ROR(FEATURE_ROR),
|
851 |
|
|
.FEATURE_EXT(FEATURE_EXT),
|
852 |
|
|
.FEATURE_CMOV(FEATURE_CMOV),
|
853 |
|
|
.FEATURE_FFL1(FEATURE_FFL1),
|
854 |
|
|
.FEATURE_CUST1(FEATURE_CUST1),
|
855 |
|
|
.FEATURE_CUST2(FEATURE_CUST2),
|
856 |
|
|
.FEATURE_CUST3(FEATURE_CUST3),
|
857 |
|
|
.FEATURE_CUST4(FEATURE_CUST4),
|
858 |
|
|
.FEATURE_CUST5(FEATURE_CUST5),
|
859 |
|
|
.FEATURE_CUST6(FEATURE_CUST6),
|
860 |
|
|
.FEATURE_CUST7(FEATURE_CUST7),
|
861 |
|
|
.FEATURE_CUST8(FEATURE_CUST8),
|
862 |
|
|
.FEATURE_FPU(FEATURE_FPU), // pipeline cappuccino: execute_alu instance
|
863 |
|
|
.OPTION_SHIFTER(OPTION_SHIFTER),
|
864 |
|
|
.CALCULATE_BRANCH_DEST("FALSE")
|
865 |
|
|
)
|
866 |
|
|
mor1kx_execute_alu
|
867 |
|
|
(/*AUTOINST*/
|
868 |
|
|
// Outputs
|
869 |
|
|
.flag_set_o (flag_set_o),
|
870 |
|
|
.flag_clear_o (flag_clear_o),
|
871 |
|
|
.carry_set_o (carry_set_o),
|
872 |
|
|
.carry_clear_o (carry_clear_o),
|
873 |
|
|
.overflow_set_o (overflow_set_o),
|
874 |
|
|
.overflow_clear_o (overflow_clear_o),
|
875 |
|
|
.fpcsr_o (fpcsr_o),
|
876 |
|
|
.fpcsr_set_o (fpcsr_set_o),
|
877 |
|
|
.alu_result_o (alu_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
878 |
|
|
.alu_valid_o (alu_valid_o),
|
879 |
|
|
.mul_result_o (mul_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
880 |
|
|
.adder_result_o (adder_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
881 |
|
|
// Inputs
|
882 |
|
|
.clk (clk),
|
883 |
|
|
.rst (rst),
|
884 |
|
|
.padv_decode_i (padv_decode_o), // Templated
|
885 |
|
|
.padv_execute_i (padv_execute_o), // Templated
|
886 |
|
|
.padv_ctrl_i (padv_ctrl_o), // Templated
|
887 |
|
|
.pipeline_flush_i (pipeline_flush_o),
|
888 |
|
|
.opc_alu_i (execute_opc_alu_o), // Templated
|
889 |
|
|
.opc_alu_secondary_i (execute_opc_alu_secondary_o), // Templated
|
890 |
|
|
.imm16_i (execute_imm16_o), // Templated
|
891 |
|
|
.immediate_i (execute_immediate_o), // Templated
|
892 |
|
|
.immediate_sel_i (execute_immediate_sel_o), // Templated
|
893 |
|
|
.decode_immediate_i (decode_immediate_o), // Templated
|
894 |
|
|
.decode_immediate_sel_i (decode_immediate_sel_o), // Templated
|
895 |
|
|
.decode_valid_i (decode_valid_o), // Templated
|
896 |
|
|
.decode_op_mul_i (decode_op_mul_o), // Templated
|
897 |
|
|
.op_alu_i (execute_op_alu_o), // Templated
|
898 |
|
|
.op_add_i (execute_op_add_o), // Templated
|
899 |
|
|
.op_mul_i (execute_op_mul_o), // Templated
|
900 |
|
|
.op_mul_signed_i (execute_op_mul_signed_o), // Templated
|
901 |
|
|
.op_mul_unsigned_i (execute_op_mul_unsigned_o), // Templated
|
902 |
|
|
.op_div_i (execute_op_div_o), // Templated
|
903 |
|
|
.op_div_signed_i (execute_op_div_signed_o), // Templated
|
904 |
|
|
.op_div_unsigned_i (execute_op_div_unsigned_o), // Templated
|
905 |
|
|
.op_shift_i (execute_op_shift_o), // Templated
|
906 |
|
|
.op_ffl1_i (execute_op_ffl1_o), // Templated
|
907 |
|
|
.op_setflag_i (execute_op_setflag_o), // Templated
|
908 |
|
|
.op_mtspr_i (execute_op_mtspr_o), // Templated
|
909 |
|
|
.op_mfspr_i (execute_op_mfspr_o), // Templated
|
910 |
|
|
.op_movhi_i (execute_op_movhi_o), // Templated
|
911 |
|
|
.op_ext_i (execute_op_ext_o), // Templated
|
912 |
|
|
.op_fpu_i (execute_op_fpu_o), // Templated
|
913 |
|
|
.fpu_round_mode_i (ctrl_fpu_round_mode_o), // Templated
|
914 |
|
|
.op_jbr_i (execute_op_jbr_o), // Templated
|
915 |
|
|
.op_jr_i (execute_op_jr_o), // Templated
|
916 |
|
|
.immjbr_upper_i (execute_immjbr_upper_o), // Templated
|
917 |
|
|
.pc_execute_i (pc_decode_to_execute), // Templated
|
918 |
|
|
.adder_do_sub_i (execute_adder_do_sub_o), // Templated
|
919 |
|
|
.adder_do_carry_i (execute_adder_do_carry_o), // Templated
|
920 |
|
|
.decode_rfa_i (decode_rfa_o), // Templated
|
921 |
|
|
.decode_rfb_i (decode_rfb_o), // Templated
|
922 |
|
|
.rfa_i (execute_rfa_o), // Templated
|
923 |
|
|
.rfb_i (execute_rfb_o), // Templated
|
924 |
|
|
.flag_i (ctrl_flag_o), // Templated
|
925 |
|
|
.carry_i (ctrl_carry_o)); // Templated
|
926 |
|
|
|
927 |
|
|
|
928 |
|
|
/* mor1kx_lsu_cappuccino AUTO_TEMPLATE (
|
929 |
|
|
.padv_execute_i (padv_execute_o),
|
930 |
|
|
.padv_ctrl_i (padv_ctrl_o),
|
931 |
|
|
.decode_valid_i (decode_valid_o),
|
932 |
|
|
.exec_lsu_adr_i (adder_result_o),
|
933 |
|
|
.ctrl_lsu_adr_i (ctrl_lsu_adr_o),
|
934 |
|
|
.ctrl_rfb_i (ctrl_rfb_o),
|
935 |
|
|
.exec_op_lsu_load_i (execute_op_lsu_load_o),
|
936 |
|
|
.exec_op_lsu_store_i (execute_op_lsu_store_o),
|
937 |
|
|
.exec_op_lsu_atomic_i (execute_op_lsu_atomic_o),
|
938 |
|
|
.ctrl_op_lsu_load_i (ctrl_op_lsu_load_o),
|
939 |
|
|
.ctrl_op_lsu_store_i (ctrl_op_lsu_store_o),
|
940 |
|
|
.ctrl_op_lsu_atomic_i (ctrl_op_lsu_atomic_o),
|
941 |
|
|
.ctrl_op_msync_i (ctrl_op_msync_o),
|
942 |
|
|
.ctrl_lsu_length_i (ctrl_lsu_length_o),
|
943 |
|
|
.ctrl_lsu_zext_i (ctrl_lsu_zext_o),
|
944 |
|
|
.ctrl_epcr_i (ctrl_epcr_o),
|
945 |
|
|
.pipeline_flush_i (pipeline_flush_o),
|
946 |
|
|
.dc_enable_i (spr_sr_o[`OR1K_SPR_SR_DCE]),
|
947 |
|
|
.dmmu_enable_i (spr_sr_o[`OR1K_SPR_SR_DME]),
|
948 |
|
|
.supervisor_mode_i (spr_sr_o[`OR1K_SPR_SR_SM]),
|
949 |
|
|
.spr_bus_dat_dc_o (spr_bus_dat_dc_i[OPTION_OPERAND_WIDTH-1:0]),
|
950 |
|
|
.spr_bus_ack_dc_o (spr_bus_ack_dc_i),
|
951 |
|
|
.spr_bus_dat_dmmu_o (spr_bus_dat_dmmu_i[OPTION_OPERAND_WIDTH-1:0]),
|
952 |
|
|
.spr_bus_ack_dmmu_o (spr_bus_ack_dmmu_i),
|
953 |
|
|
.spr_bus_addr_i (spr_bus_addr_o[15:0]),
|
954 |
|
|
.spr_bus_we_i (spr_bus_we_o),
|
955 |
|
|
.spr_bus_stb_i (spr_bus_stb_o),
|
956 |
|
|
.spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
957 |
|
|
); */
|
958 |
|
|
mor1kx_lsu_cappuccino
|
959 |
|
|
#(
|
960 |
|
|
.FEATURE_DATACACHE(FEATURE_DATACACHE),
|
961 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
962 |
|
|
.OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH),
|
963 |
|
|
.OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH),
|
964 |
|
|
.OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS),
|
965 |
|
|
.OPTION_DCACHE_LIMIT_WIDTH(OPTION_DCACHE_LIMIT_WIDTH),
|
966 |
|
|
.OPTION_DCACHE_SNOOP(OPTION_DCACHE_SNOOP),
|
967 |
|
|
.FEATURE_DMMU(FEATURE_DMMU),
|
968 |
|
|
.FEATURE_DMMU_HW_TLB_RELOAD(FEATURE_DMMU_HW_TLB_RELOAD),
|
969 |
|
|
.OPTION_DMMU_SET_WIDTH(OPTION_DMMU_SET_WIDTH),
|
970 |
|
|
.OPTION_DMMU_WAYS(OPTION_DMMU_WAYS),
|
971 |
|
|
.FEATURE_STORE_BUFFER(FEATURE_STORE_BUFFER),
|
972 |
|
|
.OPTION_STORE_BUFFER_DEPTH_WIDTH(OPTION_STORE_BUFFER_DEPTH_WIDTH),
|
973 |
|
|
.FEATURE_ATOMIC(FEATURE_ATOMIC)
|
974 |
|
|
)
|
975 |
|
|
mor1kx_lsu_cappuccino
|
976 |
|
|
(/*AUTOINST*/
|
977 |
|
|
// Outputs
|
978 |
|
|
.store_buffer_epcr_o (store_buffer_epcr_o[OPTION_OPERAND_WIDTH-1:0]),
|
979 |
|
|
.lsu_result_o (lsu_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
980 |
|
|
.lsu_valid_o (lsu_valid_o),
|
981 |
|
|
.lsu_except_dbus_o (lsu_except_dbus_o),
|
982 |
|
|
.lsu_except_align_o (lsu_except_align_o),
|
983 |
|
|
.lsu_except_dtlb_miss_o (lsu_except_dtlb_miss_o),
|
984 |
|
|
.lsu_except_dpagefault_o (lsu_except_dpagefault_o),
|
985 |
|
|
.store_buffer_err_o (store_buffer_err_o),
|
986 |
|
|
.atomic_flag_set_o (atomic_flag_set_o),
|
987 |
|
|
.atomic_flag_clear_o (atomic_flag_clear_o),
|
988 |
|
|
.msync_stall_o (msync_stall_o),
|
989 |
|
|
.spr_bus_dat_dc_o (spr_bus_dat_dc_i[OPTION_OPERAND_WIDTH-1:0]), // Templated
|
990 |
|
|
.spr_bus_ack_dc_o (spr_bus_ack_dc_i), // Templated
|
991 |
|
|
.spr_bus_dat_dmmu_o (spr_bus_dat_dmmu_i[OPTION_OPERAND_WIDTH-1:0]), // Templated
|
992 |
|
|
.spr_bus_ack_dmmu_o (spr_bus_ack_dmmu_i), // Templated
|
993 |
|
|
.dbus_adr_o (dbus_adr_o[OPTION_OPERAND_WIDTH-1:0]),
|
994 |
|
|
.dbus_req_o (dbus_req_o),
|
995 |
|
|
.dbus_dat_o (dbus_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
996 |
|
|
.dbus_bsel_o (dbus_bsel_o[3:0]),
|
997 |
|
|
.dbus_we_o (dbus_we_o),
|
998 |
|
|
.dbus_burst_o (dbus_burst_o),
|
999 |
|
|
.dc_hit_o (dcache_hit_o),
|
1000 |
|
|
// Inputs
|
1001 |
|
|
.clk (clk),
|
1002 |
|
|
.rst (rst),
|
1003 |
|
|
.padv_execute_i (padv_execute_o), // Templated
|
1004 |
|
|
.padv_ctrl_i (padv_ctrl_o), // Templated
|
1005 |
|
|
.decode_valid_i (decode_valid_o), // Templated
|
1006 |
|
|
.exec_lsu_adr_i (adder_result_o), // Templated
|
1007 |
|
|
.ctrl_lsu_adr_i (ctrl_lsu_adr_o), // Templated
|
1008 |
|
|
.ctrl_rfb_i (ctrl_rfb_o), // Templated
|
1009 |
|
|
.exec_op_lsu_load_i (execute_op_lsu_load_o), // Templated
|
1010 |
|
|
.exec_op_lsu_store_i (execute_op_lsu_store_o), // Templated
|
1011 |
|
|
.exec_op_lsu_atomic_i (execute_op_lsu_atomic_o), // Templated
|
1012 |
|
|
.ctrl_op_lsu_load_i (ctrl_op_lsu_load_o), // Templated
|
1013 |
|
|
.ctrl_op_lsu_store_i (ctrl_op_lsu_store_o), // Templated
|
1014 |
|
|
.ctrl_op_lsu_atomic_i (ctrl_op_lsu_atomic_o), // Templated
|
1015 |
|
|
.ctrl_op_msync_i (ctrl_op_msync_o), // Templated
|
1016 |
|
|
.ctrl_lsu_length_i (ctrl_lsu_length_o), // Templated
|
1017 |
|
|
.ctrl_lsu_zext_i (ctrl_lsu_zext_o), // Templated
|
1018 |
|
|
.ctrl_epcr_i (ctrl_epcr_o), // Templated
|
1019 |
|
|
.spr_bus_addr_i (spr_bus_addr_o[15:0]), // Templated
|
1020 |
|
|
.spr_bus_we_i (spr_bus_we_o), // Templated
|
1021 |
|
|
.spr_bus_stb_i (spr_bus_stb_o), // Templated
|
1022 |
|
|
.spr_bus_dat_i (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]), // Templated
|
1023 |
|
|
.dc_enable_i (spr_sr_o[`OR1K_SPR_SR_DCE]), // Templated
|
1024 |
|
|
.dmmu_enable_i (spr_sr_o[`OR1K_SPR_SR_DME]), // Templated
|
1025 |
|
|
.supervisor_mode_i (spr_sr_o[`OR1K_SPR_SR_SM]), // Templated
|
1026 |
|
|
.dbus_err_i (dbus_err_i),
|
1027 |
|
|
.dbus_ack_i (dbus_ack_i),
|
1028 |
|
|
.dbus_dat_i (dbus_dat_i[OPTION_OPERAND_WIDTH-1:0]),
|
1029 |
|
|
.pipeline_flush_i (pipeline_flush_o), // Templated
|
1030 |
|
|
.snoop_adr_i (snoop_adr_i[31:0]),
|
1031 |
|
|
.snoop_en_i (snoop_en_i));
|
1032 |
|
|
|
1033 |
|
|
|
1034 |
|
|
/* mor1kx_wb_mux_cappuccino AUTO_TEMPLATE (
|
1035 |
|
|
.alu_result_i (ctrl_alu_result_o),
|
1036 |
|
|
.lsu_result_i (lsu_result_o),
|
1037 |
|
|
.mul_result_i (mul_result_o),
|
1038 |
|
|
.spr_i (mfspr_dat_o),
|
1039 |
|
|
.op_mul_i (ctrl_op_mul_o),
|
1040 |
|
|
.op_lsu_load_i (ctrl_op_lsu_load_o),
|
1041 |
|
|
.pc_i (pc_execute_to_ctrl),
|
1042 |
|
|
.op_mfspr_i (ctrl_op_mfspr_o),
|
1043 |
|
|
); */
|
1044 |
|
|
mor1kx_wb_mux_cappuccino
|
1045 |
|
|
#(
|
1046 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH)
|
1047 |
|
|
)
|
1048 |
|
|
mor1kx_wb_mux_cappuccino
|
1049 |
|
|
(/*AUTOINST*/
|
1050 |
|
|
// Outputs
|
1051 |
|
|
.rf_result_o (rf_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
1052 |
|
|
// Inputs
|
1053 |
|
|
.clk (clk),
|
1054 |
|
|
.rst (rst),
|
1055 |
|
|
.alu_result_i (ctrl_alu_result_o), // Templated
|
1056 |
|
|
.lsu_result_i (lsu_result_o), // Templated
|
1057 |
|
|
.mul_result_i (mul_result_o), // Templated
|
1058 |
|
|
.spr_i (mfspr_dat_o), // Templated
|
1059 |
|
|
.op_mul_i (ctrl_op_mul_o), // Templated
|
1060 |
|
|
.op_lsu_load_i (ctrl_op_lsu_load_o), // Templated
|
1061 |
|
|
.op_mfspr_i (ctrl_op_mfspr_o)); // Templated
|
1062 |
|
|
|
1063 |
|
|
|
1064 |
|
|
/* mor1kx_rf_cappuccino AUTO_TEMPLATE (
|
1065 |
|
|
.padv_decode_i (padv_decode_o),
|
1066 |
|
|
.padv_execute_i (padv_execute_o),
|
1067 |
|
|
.padv_ctrl_i (padv_ctrl_o),
|
1068 |
|
|
.fetch_rf_adr_valid_i (fetch_rf_adr_valid_o),
|
1069 |
|
|
.fetch_rfa_adr_i (fetch_rfa_adr_o),
|
1070 |
|
|
.fetch_rfb_adr_i (fetch_rfb_adr_o),
|
1071 |
|
|
.decode_valid_i (decode_valid_o),
|
1072 |
|
|
.decode_rfa_adr_i (decode_rfa_adr_o),
|
1073 |
|
|
.decode_rfb_adr_i (decode_rfb_adr_o),
|
1074 |
|
|
.execute_rfd_adr_i (execute_rfd_adr_o),
|
1075 |
|
|
.ctrl_rfd_adr_i (ctrl_rfd_adr_o),
|
1076 |
|
|
.wb_rfd_adr_i (wb_rfd_adr_o),
|
1077 |
|
|
.spr_bus_addr_i (spr_bus_addr_o[15:0]),
|
1078 |
|
|
.spr_bus_stb_i (spr_bus_stb_o),
|
1079 |
|
|
.spr_bus_we_i (spr_bus_we_o),
|
1080 |
|
|
.spr_bus_dat_i (spr_bus_dat_o),
|
1081 |
|
|
.execute_rf_wb_i (execute_rf_wb_o),
|
1082 |
|
|
.ctrl_rf_wb_i (ctrl_rf_wb_o),
|
1083 |
|
|
.wb_rf_wb_i (wb_rf_wb_o),
|
1084 |
|
|
.result_i (rf_result_o),
|
1085 |
|
|
.ctrl_alu_result_i (ctrl_alu_result_o),
|
1086 |
|
|
.pipeline_flush_i (pipeline_flush_o),
|
1087 |
|
|
); */
|
1088 |
|
|
mor1kx_rf_cappuccino
|
1089 |
|
|
#(
|
1090 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
1091 |
|
|
.FEATURE_FASTCONTEXTS(FEATURE_FASTCONTEXTS),
|
1092 |
|
|
.OPTION_RF_CLEAR_ON_INIT(OPTION_RF_CLEAR_ON_INIT),
|
1093 |
|
|
.OPTION_RF_NUM_SHADOW_GPR(OPTION_RF_NUM_SHADOW_GPR),
|
1094 |
|
|
.OPTION_RF_ADDR_WIDTH(OPTION_RF_ADDR_WIDTH),
|
1095 |
|
|
.OPTION_RF_WORDS(OPTION_RF_WORDS),
|
1096 |
|
|
.FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT)
|
1097 |
|
|
)
|
1098 |
|
|
mor1kx_rf_cappuccino
|
1099 |
|
|
(/*AUTOINST*/
|
1100 |
|
|
// Outputs
|
1101 |
|
|
.spr_gpr_ack_o (spr_gpr_ack_o),
|
1102 |
|
|
.spr_gpr_dat_o (spr_gpr_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
1103 |
|
|
.decode_rfa_o (decode_rfa_o[OPTION_OPERAND_WIDTH-1:0]),
|
1104 |
|
|
.decode_rfb_o (decode_rfb_o[OPTION_OPERAND_WIDTH-1:0]),
|
1105 |
|
|
.execute_rfa_o (execute_rfa_o[OPTION_OPERAND_WIDTH-1:0]),
|
1106 |
|
|
.execute_rfb_o (execute_rfb_o[OPTION_OPERAND_WIDTH-1:0]),
|
1107 |
|
|
// Inputs
|
1108 |
|
|
.clk (clk),
|
1109 |
|
|
.rst (rst),
|
1110 |
|
|
.padv_decode_i (padv_decode_o), // Templated
|
1111 |
|
|
.padv_execute_i (padv_execute_o), // Templated
|
1112 |
|
|
.padv_ctrl_i (padv_ctrl_o), // Templated
|
1113 |
|
|
.decode_valid_i (decode_valid_o), // Templated
|
1114 |
|
|
.fetch_rf_adr_valid_i (fetch_rf_adr_valid_o), // Templated
|
1115 |
|
|
.fetch_rfa_adr_i (fetch_rfa_adr_o), // Templated
|
1116 |
|
|
.fetch_rfb_adr_i (fetch_rfb_adr_o), // Templated
|
1117 |
|
|
.decode_rfa_adr_i (decode_rfa_adr_o), // Templated
|
1118 |
|
|
.decode_rfb_adr_i (decode_rfb_adr_o), // Templated
|
1119 |
|
|
.execute_rfd_adr_i (execute_rfd_adr_o), // Templated
|
1120 |
|
|
.ctrl_rfd_adr_i (ctrl_rfd_adr_o), // Templated
|
1121 |
|
|
.wb_rfd_adr_i (wb_rfd_adr_o), // Templated
|
1122 |
|
|
.spr_bus_addr_i (spr_bus_addr_o[15:0]), // Templated
|
1123 |
|
|
.spr_bus_stb_i (spr_bus_stb_o), // Templated
|
1124 |
|
|
.spr_bus_we_i (spr_bus_we_o), // Templated
|
1125 |
|
|
.spr_bus_dat_i (spr_bus_dat_o), // Templated
|
1126 |
|
|
.execute_rf_wb_i (execute_rf_wb_o), // Templated
|
1127 |
|
|
.ctrl_rf_wb_i (ctrl_rf_wb_o), // Templated
|
1128 |
|
|
.wb_rf_wb_i (wb_rf_wb_o), // Templated
|
1129 |
|
|
.result_i (rf_result_o), // Templated
|
1130 |
|
|
.ctrl_alu_result_i (ctrl_alu_result_o), // Templated
|
1131 |
|
|
.pipeline_flush_i (pipeline_flush_o)); // Templated
|
1132 |
|
|
|
1133 |
|
|
|
1134 |
|
|
`ifndef SYNTHESIS
|
1135 |
|
|
// synthesis translate_off
|
1136 |
|
|
/* Debug signals required for the debug monitor */
|
1137 |
|
|
|
1138 |
|
|
`include "mor1kx_utils.vh"
|
1139 |
|
|
localparam RF_ADDR_WIDTH = calc_rf_addr_width(OPTION_RF_ADDR_WIDTH,
|
1140 |
|
|
OPTION_RF_NUM_SHADOW_GPR);
|
1141 |
|
|
|
1142 |
|
|
function [OPTION_OPERAND_WIDTH-1:0] get_gpr;
|
1143 |
|
|
// verilator public
|
1144 |
|
|
input [RF_ADDR_WIDTH-1:0] gpr_num;
|
1145 |
|
|
begin
|
1146 |
|
|
// TODO: handle load ops
|
1147 |
|
|
if ((mor1kx_rf_cappuccino.execute_rfd_adr_i == gpr_num[4:0]) &
|
1148 |
|
|
mor1kx_rf_cappuccino.execute_rf_wb_i)
|
1149 |
|
|
get_gpr = alu_result_o;
|
1150 |
|
|
else if ((mor1kx_rf_cappuccino.ctrl_rfd_adr_i == gpr_num[4:0]) &
|
1151 |
|
|
mor1kx_rf_cappuccino.ctrl_rf_wb_i)
|
1152 |
|
|
get_gpr = ctrl_alu_result_o;
|
1153 |
|
|
else if ((mor1kx_rf_cappuccino.wb_rfd_adr_i == gpr_num[4:0]) &
|
1154 |
|
|
mor1kx_rf_cappuccino.wb_rf_wb_i)
|
1155 |
|
|
get_gpr = mor1kx_rf_cappuccino.result_i;
|
1156 |
|
|
else
|
1157 |
|
|
get_gpr = mor1kx_rf_cappuccino.rfa.mem[gpr_num];
|
1158 |
|
|
end
|
1159 |
|
|
endfunction //
|
1160 |
|
|
|
1161 |
|
|
|
1162 |
|
|
task set_gpr;
|
1163 |
|
|
// verilator public
|
1164 |
|
|
input [RF_ADDR_WIDTH-1:0] gpr_num;
|
1165 |
|
|
input [OPTION_OPERAND_WIDTH-1:0] gpr_value;
|
1166 |
|
|
begin
|
1167 |
|
|
mor1kx_rf_cappuccino.rfa.mem[gpr_num] = gpr_value;
|
1168 |
|
|
mor1kx_rf_cappuccino.rfb.mem[gpr_num] = gpr_value;
|
1169 |
|
|
end
|
1170 |
|
|
endtask
|
1171 |
|
|
// synthesis translate_on
|
1172 |
|
|
`endif
|
1173 |
|
|
|
1174 |
|
|
|
1175 |
|
|
/* mor1kx_execute_ctrl_cappuccino AUTO_TEMPLATE (
|
1176 |
|
|
.padv_i (padv_execute_o),
|
1177 |
|
|
.padv_ctrl_i (padv_ctrl_o),
|
1178 |
|
|
.execute_except_ibus_err_i (execute_except_ibus_err_o),
|
1179 |
|
|
.execute_except_itlb_miss_i (execute_except_itlb_miss_o),
|
1180 |
|
|
.execute_except_ipagefault_i (execute_except_ipagefault_o),
|
1181 |
|
|
.execute_except_illegal_i (execute_except_illegal_o),
|
1182 |
|
|
.execute_except_ibus_align_i (execute_except_ibus_align_o),
|
1183 |
|
|
.execute_except_syscall_i (execute_except_syscall_o),
|
1184 |
|
|
.execute_except_trap_i (execute_except_trap_o),
|
1185 |
|
|
.lsu_except_dbus_i (lsu_except_dbus_o),
|
1186 |
|
|
.lsu_except_align_i (lsu_except_align_o),
|
1187 |
|
|
.lsu_except_dtlb_miss_i (lsu_except_dtlb_miss_o),
|
1188 |
|
|
.lsu_except_dpagefault_i (lsu_except_dpagefault_o),
|
1189 |
|
|
.op_mul_i (execute_op_mul_o),
|
1190 |
|
|
.op_lsu_load_i (execute_op_lsu_load_o),
|
1191 |
|
|
.op_lsu_store_i (execute_op_lsu_store_o),
|
1192 |
|
|
.op_lsu_atomic_i (execute_op_lsu_atomic_o),
|
1193 |
|
|
.lsu_length_i (execute_lsu_length_o),
|
1194 |
|
|
.lsu_zext_i (execute_lsu_zext_o),
|
1195 |
|
|
.op_msync_i (execute_op_msync_o),
|
1196 |
|
|
.op_mfspr_i (execute_op_mfspr_o),
|
1197 |
|
|
.op_mtspr_i (execute_op_mtspr_o),
|
1198 |
|
|
.alu_valid_i (alu_valid_o),
|
1199 |
|
|
.lsu_valid_i (lsu_valid_o),
|
1200 |
|
|
.msync_stall_i (msync_stall_o),
|
1201 |
|
|
.alu_result_i (alu_result_o),
|
1202 |
|
|
.adder_result_i (adder_result_o),
|
1203 |
|
|
.execute_jal_result_i (execute_jal_result_o),
|
1204 |
|
|
.op_jr_i (execute_op_jr_o),
|
1205 |
|
|
.op_jal_i (execute_op_jal_o),
|
1206 |
|
|
.op_rfe_i (execute_op_rfe_o),
|
1207 |
|
|
.rfb_i (execute_rfb_o),
|
1208 |
|
|
.flag_set_i (flag_set_o),
|
1209 |
|
|
.flag_clear_i (flag_clear_o),
|
1210 |
|
|
.pc_execute_i (pc_decode_to_execute),
|
1211 |
|
|
.execute_rf_wb_i (execute_rf_wb_o),
|
1212 |
|
|
.execute_rfd_adr_i (execute_rfd_adr_o),
|
1213 |
|
|
.ctrl_mfspr_ack_i (ctrl_mfspr_ack_o),
|
1214 |
|
|
.ctrl_mtspr_ack_i (ctrl_mtspr_ack_o),
|
1215 |
|
|
.pipeline_flush_i (pipeline_flush_o),
|
1216 |
|
|
.pc_ctrl_o (pc_execute_to_ctrl),
|
1217 |
|
|
.execute_bubble_i (execute_bubble_o),
|
1218 |
|
|
.carry_set_i (carry_set_o),
|
1219 |
|
|
.carry_clear_i (carry_clear_o),
|
1220 |
|
|
.overflow_set_i (overflow_set_o),
|
1221 |
|
|
.overflow_clear_i (overflow_clear_o),
|
1222 |
|
|
.fpcsr_i (fpcsr_o),
|
1223 |
|
|
.fpcsr_set_i (fpcsr_set_o),
|
1224 |
|
|
); */
|
1225 |
|
|
mor1kx_execute_ctrl_cappuccino
|
1226 |
|
|
#(
|
1227 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
1228 |
|
|
.OPTION_RESET_PC(OPTION_RESET_PC),
|
1229 |
|
|
.FEATURE_FPU(FEATURE_FPU), // pipeline cappuccino: execute_ctrl instance
|
1230 |
|
|
.FEATURE_MULTIPLIER(FEATURE_MULTIPLIER)
|
1231 |
|
|
)
|
1232 |
|
|
mor1kx_execute_ctrl_cappuccino
|
1233 |
|
|
(/*AUTOINST*/
|
1234 |
|
|
// Outputs
|
1235 |
|
|
.ctrl_rf_wb_o (ctrl_rf_wb_o),
|
1236 |
|
|
.wb_rf_wb_o (wb_rf_wb_o),
|
1237 |
|
|
.ctrl_rfd_adr_o (ctrl_rfd_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
1238 |
|
|
.wb_rfd_adr_o (wb_rfd_adr_o[OPTION_RF_ADDR_WIDTH-1:0]),
|
1239 |
|
|
.ctrl_alu_result_o (ctrl_alu_result_o[OPTION_OPERAND_WIDTH-1:0]),
|
1240 |
|
|
.ctrl_lsu_adr_o (ctrl_lsu_adr_o[OPTION_OPERAND_WIDTH-1:0]),
|
1241 |
|
|
.ctrl_rfb_o (ctrl_rfb_o[OPTION_OPERAND_WIDTH-1:0]),
|
1242 |
|
|
.ctrl_flag_set_o (ctrl_flag_set_o),
|
1243 |
|
|
.ctrl_flag_clear_o (ctrl_flag_clear_o),
|
1244 |
|
|
.ctrl_carry_set_o (ctrl_carry_set_o),
|
1245 |
|
|
.ctrl_carry_clear_o (ctrl_carry_clear_o),
|
1246 |
|
|
.ctrl_overflow_set_o (ctrl_overflow_set_o),
|
1247 |
|
|
.ctrl_overflow_clear_o (ctrl_overflow_clear_o),
|
1248 |
|
|
.ctrl_fpcsr_o (ctrl_fpcsr_o),
|
1249 |
|
|
.ctrl_fpcsr_set_o (ctrl_fpcsr_set_o),
|
1250 |
|
|
.pc_ctrl_o (pc_execute_to_ctrl), // Templated
|
1251 |
|
|
.ctrl_op_mul_o (ctrl_op_mul_o),
|
1252 |
|
|
.ctrl_op_lsu_load_o (ctrl_op_lsu_load_o),
|
1253 |
|
|
.ctrl_op_lsu_store_o (ctrl_op_lsu_store_o),
|
1254 |
|
|
.ctrl_op_lsu_atomic_o (ctrl_op_lsu_atomic_o),
|
1255 |
|
|
.ctrl_lsu_length_o (ctrl_lsu_length_o[1:0]),
|
1256 |
|
|
.ctrl_lsu_zext_o (ctrl_lsu_zext_o),
|
1257 |
|
|
.ctrl_op_msync_o (ctrl_op_msync_o),
|
1258 |
|
|
.ctrl_op_mfspr_o (ctrl_op_mfspr_o),
|
1259 |
|
|
.ctrl_op_mtspr_o (ctrl_op_mtspr_o),
|
1260 |
|
|
.ctrl_op_rfe_o (ctrl_op_rfe_o),
|
1261 |
|
|
.ctrl_except_ibus_err_o (ctrl_except_ibus_err_o),
|
1262 |
|
|
.ctrl_except_itlb_miss_o (ctrl_except_itlb_miss_o),
|
1263 |
|
|
.ctrl_except_ipagefault_o (ctrl_except_ipagefault_o),
|
1264 |
|
|
.ctrl_except_ibus_align_o (ctrl_except_ibus_align_o),
|
1265 |
|
|
.ctrl_except_illegal_o (ctrl_except_illegal_o),
|
1266 |
|
|
.ctrl_except_syscall_o (ctrl_except_syscall_o),
|
1267 |
|
|
.ctrl_except_dbus_o (ctrl_except_dbus_o),
|
1268 |
|
|
.ctrl_except_dtlb_miss_o (ctrl_except_dtlb_miss_o),
|
1269 |
|
|
.ctrl_except_dpagefault_o (ctrl_except_dpagefault_o),
|
1270 |
|
|
.ctrl_except_align_o (ctrl_except_align_o),
|
1271 |
|
|
.ctrl_except_trap_o (ctrl_except_trap_o),
|
1272 |
|
|
.execute_valid_o (execute_valid_o),
|
1273 |
|
|
.ctrl_valid_o (ctrl_valid_o),
|
1274 |
|
|
// Inputs
|
1275 |
|
|
.clk (clk),
|
1276 |
|
|
.rst (rst),
|
1277 |
|
|
.padv_i (padv_execute_o), // Templated
|
1278 |
|
|
.padv_ctrl_i (padv_ctrl_o), // Templated
|
1279 |
|
|
.execute_except_ibus_err_i (execute_except_ibus_err_o), // Templated
|
1280 |
|
|
.execute_except_itlb_miss_i (execute_except_itlb_miss_o), // Templated
|
1281 |
|
|
.execute_except_ipagefault_i (execute_except_ipagefault_o), // Templated
|
1282 |
|
|
.execute_except_illegal_i (execute_except_illegal_o), // Templated
|
1283 |
|
|
.execute_except_ibus_align_i (execute_except_ibus_align_o), // Templated
|
1284 |
|
|
.execute_except_syscall_i (execute_except_syscall_o), // Templated
|
1285 |
|
|
.lsu_except_dbus_i (lsu_except_dbus_o), // Templated
|
1286 |
|
|
.lsu_except_align_i (lsu_except_align_o), // Templated
|
1287 |
|
|
.lsu_except_dtlb_miss_i (lsu_except_dtlb_miss_o), // Templated
|
1288 |
|
|
.lsu_except_dpagefault_i (lsu_except_dpagefault_o), // Templated
|
1289 |
|
|
.execute_except_trap_i (execute_except_trap_o), // Templated
|
1290 |
|
|
.pipeline_flush_i (pipeline_flush_o), // Templated
|
1291 |
|
|
.op_mul_i (execute_op_mul_o), // Templated
|
1292 |
|
|
.op_lsu_load_i (execute_op_lsu_load_o), // Templated
|
1293 |
|
|
.op_lsu_store_i (execute_op_lsu_store_o), // Templated
|
1294 |
|
|
.op_lsu_atomic_i (execute_op_lsu_atomic_o), // Templated
|
1295 |
|
|
.lsu_length_i (execute_lsu_length_o), // Templated
|
1296 |
|
|
.lsu_zext_i (execute_lsu_zext_o), // Templated
|
1297 |
|
|
.op_msync_i (execute_op_msync_o), // Templated
|
1298 |
|
|
.op_mfspr_i (execute_op_mfspr_o), // Templated
|
1299 |
|
|
.op_mtspr_i (execute_op_mtspr_o), // Templated
|
1300 |
|
|
.alu_valid_i (alu_valid_o), // Templated
|
1301 |
|
|
.lsu_valid_i (lsu_valid_o), // Templated
|
1302 |
|
|
.msync_stall_i (msync_stall_o), // Templated
|
1303 |
|
|
.op_jr_i (execute_op_jr_o), // Templated
|
1304 |
|
|
.op_jal_i (execute_op_jal_o), // Templated
|
1305 |
|
|
.op_rfe_i (execute_op_rfe_o), // Templated
|
1306 |
|
|
.alu_result_i (alu_result_o), // Templated
|
1307 |
|
|
.adder_result_i (adder_result_o), // Templated
|
1308 |
|
|
.rfb_i (execute_rfb_o), // Templated
|
1309 |
|
|
.execute_jal_result_i (execute_jal_result_o), // Templated
|
1310 |
|
|
.flag_set_i (flag_set_o), // Templated
|
1311 |
|
|
.flag_clear_i (flag_clear_o), // Templated
|
1312 |
|
|
.carry_set_i (carry_set_o), // Templated
|
1313 |
|
|
.carry_clear_i (carry_clear_o), // Templated
|
1314 |
|
|
.overflow_set_i (overflow_set_o), // Templated
|
1315 |
|
|
.overflow_clear_i (overflow_clear_o), // Templated
|
1316 |
|
|
.fpcsr_i (fpcsr_o),
|
1317 |
|
|
.fpcsr_set_i (fpcsr_set_o),
|
1318 |
|
|
.pc_execute_i (pc_decode_to_execute), // Templated
|
1319 |
|
|
.execute_rf_wb_i (execute_rf_wb_o), // Templated
|
1320 |
|
|
.execute_rfd_adr_i (execute_rfd_adr_o), // Templated
|
1321 |
|
|
.execute_bubble_i (execute_bubble_o), // Templated
|
1322 |
|
|
.ctrl_mfspr_ack_i (ctrl_mfspr_ack_o), // Templated
|
1323 |
|
|
.ctrl_mtspr_ack_i (ctrl_mtspr_ack_o)); // Templated
|
1324 |
|
|
|
1325 |
|
|
/* mor1kx_ctrl_cappuccino AUTO_TEMPLATE (
|
1326 |
|
|
.ctrl_alu_result_i (ctrl_alu_result_o),
|
1327 |
|
|
.ctrl_lsu_adr_i (ctrl_lsu_adr_o),
|
1328 |
|
|
.ctrl_rfb_i (ctrl_rfb_o),
|
1329 |
|
|
.ctrl_flag_set_i (ctrl_flag_set_o),
|
1330 |
|
|
.ctrl_flag_clear_i (ctrl_flag_clear_o),
|
1331 |
|
|
.atomic_flag_set_i (atomic_flag_set_o),
|
1332 |
|
|
.atomic_flag_clear_i (atomic_flag_clear_o),
|
1333 |
|
|
.pc_ctrl_i (pc_execute_to_ctrl),
|
1334 |
|
|
.pc_execute_i (pc_decode_to_execute),
|
1335 |
|
|
.execute_op_branch_i (execute_op_branch_o),
|
1336 |
|
|
.ctrl_op_mfspr_i (ctrl_op_mfspr_o),
|
1337 |
|
|
.ctrl_op_mtspr_i (ctrl_op_mtspr_o),
|
1338 |
|
|
.ctrl_op_rfe_i (ctrl_op_rfe_o),
|
1339 |
|
|
.decode_branch_i (decode_branch_o),
|
1340 |
|
|
.decode_branch_target_i (decode_branch_target_o),
|
1341 |
|
|
.branch_mispredict_i (branch_mispredict_o),
|
1342 |
|
|
.execute_mispredict_target_i (execute_mispredict_target_o),
|
1343 |
|
|
.except_ibus_err_i (ctrl_except_ibus_err_o),
|
1344 |
|
|
.except_itlb_miss_i (ctrl_except_itlb_miss_o),
|
1345 |
|
|
.except_ipagefault_i (ctrl_except_ipagefault_o),
|
1346 |
|
|
.except_ibus_align_i (ctrl_except_ibus_align_o),
|
1347 |
|
|
.except_illegal_i (ctrl_except_illegal_o),
|
1348 |
|
|
.except_syscall_i (ctrl_except_syscall_o),
|
1349 |
|
|
.except_dbus_i (ctrl_except_dbus_o),
|
1350 |
|
|
.except_dtlb_miss_i (ctrl_except_dtlb_miss_o),
|
1351 |
|
|
.except_dpagefault_i (ctrl_except_dpagefault_o),
|
1352 |
|
|
.except_trap_i (ctrl_except_trap_o),
|
1353 |
|
|
.except_align_i (ctrl_except_align_o),
|
1354 |
|
|
.fetch_valid_i (fetch_valid_o),
|
1355 |
|
|
.decode_valid_i (decode_valid_o),
|
1356 |
|
|
.execute_valid_i (execute_valid_o),
|
1357 |
|
|
.ctrl_valid_i (ctrl_valid_o),
|
1358 |
|
|
.fetch_exception_taken_i (fetch_exception_taken_o),
|
1359 |
|
|
.decode_bubble_i (decode_bubble_o),
|
1360 |
|
|
.execute_bubble_i (execute_bubble_o),
|
1361 |
|
|
.store_buffer_epcr_i (store_buffer_epcr_o),
|
1362 |
|
|
.store_buffer_err_i (store_buffer_err_o),
|
1363 |
|
|
.ctrl_carry_set_i (ctrl_carry_set_o),
|
1364 |
|
|
.ctrl_carry_clear_i (ctrl_carry_clear_o),
|
1365 |
|
|
.ctrl_overflow_set_i (ctrl_overflow_set_o),
|
1366 |
|
|
.ctrl_overflow_clear_i (ctrl_overflow_clear_o),
|
1367 |
|
|
.ctrl_fpcsr_i (ctrl_fpcsr_o),
|
1368 |
|
|
.ctrl_fpcsr_set_i (ctrl_fpcsr_set_o),
|
1369 |
|
|
.spr_gpr_ack_i (spr_gpr_ack_o),
|
1370 |
|
|
.spr_gpr_dat_i (spr_gpr_dat_o),
|
1371 |
|
|
) */
|
1372 |
|
|
mor1kx_ctrl_cappuccino
|
1373 |
|
|
#(
|
1374 |
|
|
.OPTION_OPERAND_WIDTH(OPTION_OPERAND_WIDTH),
|
1375 |
|
|
.OPTION_RESET_PC(OPTION_RESET_PC),
|
1376 |
|
|
.FEATURE_PIC(FEATURE_PIC),
|
1377 |
|
|
.FEATURE_TIMER(FEATURE_TIMER),
|
1378 |
|
|
.OPTION_PIC_TRIGGER(OPTION_PIC_TRIGGER),
|
1379 |
|
|
.OPTION_PIC_NMI_WIDTH(OPTION_PIC_NMI_WIDTH),
|
1380 |
|
|
.FEATURE_DATACACHE(FEATURE_DATACACHE),
|
1381 |
|
|
.OPTION_DCACHE_BLOCK_WIDTH(OPTION_DCACHE_BLOCK_WIDTH),
|
1382 |
|
|
.OPTION_DCACHE_SET_WIDTH(OPTION_DCACHE_SET_WIDTH),
|
1383 |
|
|
.OPTION_DCACHE_WAYS(OPTION_DCACHE_WAYS),
|
1384 |
|
|
.FEATURE_DMMU(FEATURE_DMMU),
|
1385 |
|
|
.OPTION_DMMU_SET_WIDTH(OPTION_DMMU_SET_WIDTH),
|
1386 |
|
|
.OPTION_DMMU_WAYS(OPTION_DMMU_WAYS),
|
1387 |
|
|
.FEATURE_INSTRUCTIONCACHE(FEATURE_INSTRUCTIONCACHE),
|
1388 |
|
|
.OPTION_ICACHE_BLOCK_WIDTH(OPTION_ICACHE_BLOCK_WIDTH),
|
1389 |
|
|
.OPTION_ICACHE_SET_WIDTH(OPTION_ICACHE_SET_WIDTH),
|
1390 |
|
|
.OPTION_ICACHE_WAYS(OPTION_ICACHE_WAYS),
|
1391 |
|
|
.FEATURE_IMMU(FEATURE_IMMU),
|
1392 |
|
|
.OPTION_IMMU_SET_WIDTH(OPTION_IMMU_SET_WIDTH),
|
1393 |
|
|
.OPTION_IMMU_WAYS(OPTION_IMMU_WAYS),
|
1394 |
|
|
.FEATURE_DEBUGUNIT(FEATURE_DEBUGUNIT),
|
1395 |
|
|
.FEATURE_PERFCOUNTERS(FEATURE_PERFCOUNTERS),
|
1396 |
|
|
.OPTION_PERFCOUNTERS_NUM(OPTION_PERFCOUNTERS_NUM),
|
1397 |
|
|
.FEATURE_MAC(FEATURE_MAC),
|
1398 |
|
|
.FEATURE_FPU(FEATURE_FPU), // pipeline cappuccino: ctrl instance
|
1399 |
|
|
.FEATURE_MULTICORE(FEATURE_MULTICORE),
|
1400 |
|
|
.FEATURE_SYSCALL(FEATURE_SYSCALL),
|
1401 |
|
|
.FEATURE_TRAP(FEATURE_TRAP),
|
1402 |
|
|
.FEATURE_RANGE(FEATURE_RANGE),
|
1403 |
|
|
.FEATURE_DSX(FEATURE_DSX),
|
1404 |
|
|
.FEATURE_FASTCONTEXTS(FEATURE_FASTCONTEXTS),
|
1405 |
|
|
.OPTION_RF_NUM_SHADOW_GPR(OPTION_RF_NUM_SHADOW_GPR),
|
1406 |
|
|
.FEATURE_OVERFLOW(FEATURE_OVERFLOW),
|
1407 |
|
|
.FEATURE_CARRY_FLAG(FEATURE_CARRY_FLAG)
|
1408 |
|
|
)
|
1409 |
|
|
mor1kx_ctrl_cappuccino
|
1410 |
|
|
(/*AUTOINST*/
|
1411 |
|
|
// Outputs
|
1412 |
|
|
.ctrl_epcr_o (ctrl_epcr_o[OPTION_OPERAND_WIDTH-1:0]),
|
1413 |
|
|
.mfspr_dat_o (mfspr_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
1414 |
|
|
.ctrl_mfspr_ack_o (ctrl_mfspr_ack_o),
|
1415 |
|
|
.ctrl_mtspr_ack_o (ctrl_mtspr_ack_o),
|
1416 |
|
|
.ctrl_flag_o (ctrl_flag_o),
|
1417 |
|
|
.ctrl_carry_o (ctrl_carry_o),
|
1418 |
|
|
.ctrl_fpu_round_mode_o (ctrl_fpu_round_mode_o),
|
1419 |
|
|
.ctrl_branch_exception_o (ctrl_branch_exception_o),
|
1420 |
|
|
.ctrl_branch_except_pc_o (ctrl_branch_except_pc_o[OPTION_OPERAND_WIDTH-1:0]),
|
1421 |
|
|
.pipeline_flush_o (pipeline_flush_o),
|
1422 |
|
|
.doing_rfe_o (doing_rfe_o),
|
1423 |
|
|
.padv_fetch_o (padv_fetch_o),
|
1424 |
|
|
.padv_decode_o (padv_decode_o),
|
1425 |
|
|
.padv_execute_o (padv_execute_o),
|
1426 |
|
|
.padv_ctrl_o (padv_ctrl_o),
|
1427 |
|
|
.du_dat_o (du_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
1428 |
|
|
.du_ack_o (du_ack_o),
|
1429 |
|
|
.du_stall_o (du_stall_o),
|
1430 |
|
|
.du_restart_pc_o (du_restart_pc_o[OPTION_OPERAND_WIDTH-1:0]),
|
1431 |
|
|
.du_restart_o (du_restart_o),
|
1432 |
|
|
.spr_bus_addr_o (spr_bus_addr_o[15:0]),
|
1433 |
|
|
.spr_bus_we_o (spr_bus_we_o),
|
1434 |
|
|
.spr_bus_stb_o (spr_bus_stb_o),
|
1435 |
|
|
.spr_bus_dat_o (spr_bus_dat_o[OPTION_OPERAND_WIDTH-1:0]),
|
1436 |
|
|
.spr_sr_o (spr_sr_o[15:0]),
|
1437 |
|
|
.ctrl_bubble_o (ctrl_bubble_o),
|
1438 |
|
|
// Inputs
|
1439 |
|
|
.clk (clk),
|
1440 |
|
|
.rst (rst),
|
1441 |
|
|
.ctrl_alu_result_i (ctrl_alu_result_o), // Templated
|
1442 |
|
|
.ctrl_lsu_adr_i (ctrl_lsu_adr_o), // Templated
|
1443 |
|
|
.ctrl_rfb_i (ctrl_rfb_o), // Templated
|
1444 |
|
|
.ctrl_flag_set_i (ctrl_flag_set_o), // Templated
|
1445 |
|
|
.ctrl_flag_clear_i (ctrl_flag_clear_o), // Templated
|
1446 |
|
|
.atomic_flag_set_i (atomic_flag_set_o), // Templated
|
1447 |
|
|
.atomic_flag_clear_i (atomic_flag_clear_o), // Templated
|
1448 |
|
|
.pc_ctrl_i (pc_execute_to_ctrl), // Templated
|
1449 |
|
|
.ctrl_op_mfspr_i (ctrl_op_mfspr_o), // Templated
|
1450 |
|
|
.ctrl_op_mtspr_i (ctrl_op_mtspr_o), // Templated
|
1451 |
|
|
.ctrl_op_rfe_i (ctrl_op_rfe_o), // Templated
|
1452 |
|
|
.decode_branch_i (decode_branch_o), // Templated
|
1453 |
|
|
.decode_branch_target_i (decode_branch_target_o), // Templated
|
1454 |
|
|
.branch_mispredict_i (branch_mispredict_o), // Templated
|
1455 |
|
|
.execute_mispredict_target_i (execute_mispredict_target_o), // Templated
|
1456 |
|
|
.pc_execute_i (pc_decode_to_execute), // Templated
|
1457 |
|
|
.execute_op_branch_i (execute_op_branch_o), // Templated
|
1458 |
|
|
.except_ibus_err_i (ctrl_except_ibus_err_o), // Templated
|
1459 |
|
|
.except_itlb_miss_i (ctrl_except_itlb_miss_o), // Templated
|
1460 |
|
|
.except_ipagefault_i (ctrl_except_ipagefault_o), // Templated
|
1461 |
|
|
.except_ibus_align_i (ctrl_except_ibus_align_o), // Templated
|
1462 |
|
|
.except_illegal_i (ctrl_except_illegal_o), // Templated
|
1463 |
|
|
.except_syscall_i (ctrl_except_syscall_o), // Templated
|
1464 |
|
|
.except_dbus_i (ctrl_except_dbus_o), // Templated
|
1465 |
|
|
.except_dtlb_miss_i (ctrl_except_dtlb_miss_o), // Templated
|
1466 |
|
|
.except_dpagefault_i (ctrl_except_dpagefault_o), // Templated
|
1467 |
|
|
.except_trap_i (ctrl_except_trap_o), // Templated
|
1468 |
|
|
.except_align_i (ctrl_except_align_o), // Templated
|
1469 |
|
|
.fetch_valid_i (fetch_valid_o), // Templated
|
1470 |
|
|
.decode_valid_i (decode_valid_o), // Templated
|
1471 |
|
|
.execute_valid_i (execute_valid_o), // Templated
|
1472 |
|
|
.execute_op_lsu_load_i (execute_op_lsu_load_o),
|
1473 |
|
|
.execute_op_lsu_store_i (execute_op_lsu_store_o),
|
1474 |
|
|
.ctrl_valid_i (ctrl_valid_o), // Templated
|
1475 |
|
|
.fetch_exception_taken_i (fetch_exception_taken_o), // Templated
|
1476 |
|
|
.decode_bubble_i (decode_bubble_o), // Templated
|
1477 |
|
|
.execute_bubble_i (execute_bubble_o), // Templated
|
1478 |
|
|
.irq_i (irq_i[31:0]),
|
1479 |
|
|
.store_buffer_epcr_i (store_buffer_epcr_o), // Templated
|
1480 |
|
|
.store_buffer_err_i (store_buffer_err_o), // Templated
|
1481 |
|
|
.ctrl_carry_set_i (ctrl_carry_set_o), // Templated
|
1482 |
|
|
.ctrl_carry_clear_i (ctrl_carry_clear_o), // Templated
|
1483 |
|
|
.ctrl_overflow_set_i (ctrl_overflow_set_o), // Templated
|
1484 |
|
|
.ctrl_overflow_clear_i (ctrl_overflow_clear_o), // Templated
|
1485 |
|
|
.ctrl_fpcsr_i (ctrl_fpcsr_o),
|
1486 |
|
|
.ctrl_fpcsr_set_i (ctrl_fpcsr_set_o),
|
1487 |
|
|
.icache_hit_i (icache_hit_o),
|
1488 |
|
|
.dcache_hit_i (dcache_hit_o),
|
1489 |
|
|
.du_addr_i (du_addr_i[15:0]),
|
1490 |
|
|
.du_stb_i (du_stb_i),
|
1491 |
|
|
.du_dat_i (du_dat_i[OPTION_OPERAND_WIDTH-1:0]),
|
1492 |
|
|
.du_we_i (du_we_i),
|
1493 |
|
|
.du_stall_i (du_stall_i),
|
1494 |
|
|
.spr_bus_dat_dc_i (spr_bus_dat_dc_i[OPTION_OPERAND_WIDTH-1:0]),
|
1495 |
|
|
.spr_bus_ack_dc_i (spr_bus_ack_dc_i),
|
1496 |
|
|
.spr_bus_dat_ic_i (spr_bus_dat_ic_i[OPTION_OPERAND_WIDTH-1:0]),
|
1497 |
|
|
.spr_bus_ack_ic_i (spr_bus_ack_ic_i),
|
1498 |
|
|
.spr_bus_dat_dmmu_i (spr_bus_dat_dmmu_i[OPTION_OPERAND_WIDTH-1:0]),
|
1499 |
|
|
.spr_bus_ack_dmmu_i (spr_bus_ack_dmmu_i),
|
1500 |
|
|
.spr_bus_dat_immu_i (spr_bus_dat_immu_i[OPTION_OPERAND_WIDTH-1:0]),
|
1501 |
|
|
.spr_bus_ack_immu_i (spr_bus_ack_immu_i),
|
1502 |
|
|
.spr_bus_dat_mac_i (spr_bus_dat_mac_i[OPTION_OPERAND_WIDTH-1:0]),
|
1503 |
|
|
.spr_bus_ack_mac_i (spr_bus_ack_mac_i),
|
1504 |
|
|
.spr_bus_dat_pmu_i (spr_bus_dat_pmu_i[OPTION_OPERAND_WIDTH-1:0]),
|
1505 |
|
|
.spr_bus_ack_pmu_i (spr_bus_ack_pmu_i),
|
1506 |
|
|
.spr_bus_dat_pcu_i (spr_bus_dat_pcu_i[OPTION_OPERAND_WIDTH-1:0]),
|
1507 |
|
|
.spr_bus_ack_pcu_i (spr_bus_ack_pcu_i),
|
1508 |
|
|
.spr_bus_dat_fpu_i (spr_bus_dat_fpu_i[OPTION_OPERAND_WIDTH-1:0]),
|
1509 |
|
|
.spr_bus_ack_fpu_i (spr_bus_ack_fpu_i),
|
1510 |
|
|
.spr_gpr_dat_i (spr_gpr_dat_o), // Templated
|
1511 |
|
|
.spr_gpr_ack_i (spr_gpr_ack_o), // Templated
|
1512 |
|
|
.multicore_coreid_i (multicore_coreid_i[OPTION_OPERAND_WIDTH-1:0]),
|
1513 |
|
|
.multicore_numcores_i (multicore_numcores_i[OPTION_OPERAND_WIDTH-1:0]));
|
1514 |
|
|
|
1515 |
|
|
reg [`OR1K_INSN_WIDTH-1:0] traceport_stage_decode_insn;
|
1516 |
|
|
reg [`OR1K_INSN_WIDTH-1:0] traceport_stage_exec_insn;
|
1517 |
|
|
|
1518 |
|
|
reg traceport_jal_execute_to_ctrl;
|
1519 |
|
|
reg traceport_jr_execute_to_ctrl;
|
1520 |
|
|
reg [31:0] traceport_jbtarget_decode_to_execute;
|
1521 |
|
|
reg [31:0] traceport_jbtarget_execute_to_ctrl;
|
1522 |
|
|
|
1523 |
|
|
reg traceport_waitexec;
|
1524 |
|
|
|
1525 |
|
|
always @(posedge clk) begin
|
1526 |
|
|
if (FEATURE_TRACEPORT_EXEC != "NONE") begin
|
1527 |
|
|
if (rst) begin
|
1528 |
|
|
traceport_waitexec <= 0;
|
1529 |
|
|
end else begin
|
1530 |
|
|
if (padv_decode_o) begin
|
1531 |
|
|
traceport_stage_decode_insn <= insn_fetch_to_decode;
|
1532 |
|
|
traceport_jbtarget_decode_to_execute <= decode_branch_target_o;
|
1533 |
|
|
end
|
1534 |
|
|
|
1535 |
|
|
if (padv_execute_o) begin
|
1536 |
|
|
traceport_stage_exec_insn <= traceport_stage_decode_insn;
|
1537 |
|
|
traceport_jbtarget_execute_to_ctrl <= traceport_jbtarget_decode_to_execute;
|
1538 |
|
|
traceport_jal_execute_to_ctrl <= execute_op_jal_o;
|
1539 |
|
|
traceport_jr_execute_to_ctrl <= execute_op_jr_o & !execute_op_jal_o;
|
1540 |
|
|
end
|
1541 |
|
|
|
1542 |
|
|
if (padv_ctrl_o) begin
|
1543 |
|
|
traceport_exec_jal_o <= traceport_jal_execute_to_ctrl;
|
1544 |
|
|
traceport_exec_jr_o <= traceport_jr_execute_to_ctrl;
|
1545 |
|
|
traceport_exec_insn_o <= traceport_stage_exec_insn;
|
1546 |
|
|
traceport_exec_jbtarget_o <= traceport_jbtarget_execute_to_ctrl;
|
1547 |
|
|
end
|
1548 |
|
|
|
1549 |
|
|
traceport_exec_pc_o <= pc_execute_to_ctrl;
|
1550 |
|
|
|
1551 |
|
|
if (!traceport_waitexec) begin
|
1552 |
|
|
if (padv_ctrl_o & !ctrl_bubble_o) begin
|
1553 |
|
|
if (execute_valid_o) begin
|
1554 |
|
|
traceport_exec_valid_o <= 1'b1;
|
1555 |
|
|
end else begin
|
1556 |
|
|
traceport_exec_valid_o <= 1'b0;
|
1557 |
|
|
traceport_waitexec <= 1'b1;
|
1558 |
|
|
end
|
1559 |
|
|
end else if (ctrl_op_rfe_o) begin
|
1560 |
|
|
traceport_exec_valid_o <= 1'b1;
|
1561 |
|
|
end else begin
|
1562 |
|
|
traceport_exec_valid_o <= 1'b0;
|
1563 |
|
|
end
|
1564 |
|
|
end else begin
|
1565 |
|
|
if (execute_valid_o) begin
|
1566 |
|
|
traceport_exec_valid_o <= 1'b1;
|
1567 |
|
|
traceport_waitexec <= 1'b0;
|
1568 |
|
|
end else begin
|
1569 |
|
|
traceport_exec_valid_o <= 1'b0;
|
1570 |
|
|
end
|
1571 |
|
|
end // else: !if(!traceport_waitexec)
|
1572 |
|
|
end // else: !if(rst)
|
1573 |
|
|
end else begin // if (FEATURE_TRACEPORT_EXEC != "NONE")
|
1574 |
|
|
traceport_stage_decode_insn <= {`OR1K_INSN_WIDTH{1'b0}};
|
1575 |
|
|
traceport_stage_exec_insn <= {`OR1K_INSN_WIDTH{1'b0}};
|
1576 |
|
|
traceport_exec_insn_o <= {`OR1K_INSN_WIDTH{1'b0}};
|
1577 |
|
|
traceport_exec_pc_o <= 32'h0;
|
1578 |
|
|
traceport_exec_valid_o <= 1'b0;
|
1579 |
|
|
end
|
1580 |
|
|
end
|
1581 |
|
|
|
1582 |
|
|
generate
|
1583 |
|
|
if (FEATURE_TRACEPORT_EXEC != "NONE") begin
|
1584 |
|
|
assign traceport_exec_wbreg_o = wb_rfd_adr_o;
|
1585 |
|
|
assign traceport_exec_wben_o = wb_rf_wb_o;
|
1586 |
|
|
assign traceport_exec_wbdata_o = rf_result_o;
|
1587 |
|
|
end else begin
|
1588 |
|
|
assign traceport_exec_wbreg_o = {OPTION_RF_ADDR_WIDTH{1'b0}};
|
1589 |
|
|
assign traceport_exec_wben_o = 1'b0;
|
1590 |
|
|
assign traceport_exec_wbdata_o = {OPTION_OPERAND_WIDTH{1'b0}};
|
1591 |
|
|
end
|
1592 |
|
|
endgenerate
|
1593 |
|
|
|
1594 |
|
|
endmodule // mor1kx_cpu_cappuccino
|