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/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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Description: mor1kx pronto espresso fetch unit
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Fetch insn, advance PC (or take new branch address) on padv_i.
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What we might want to do is have a 1-insn buffer here, so when the current
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insn is fetched, but the main pipeline doesn't want it yet
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indicate ibus errors
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Copyright (C) 2012 Authors
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Author(s): Julius Baxter <juliusbaxter@gmail.com>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_fetch_prontoespresso
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(/*AUTOARG*/
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// Outputs
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ibus_adr_o, ibus_req_o, ibus_burst_o, decode_insn_o, fetched_pc_o,
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fetch_ready_o, fetch_rfa_adr_o, fetch_rfb_adr_o, fetch_rf_re_o,
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pc_fetch_next_o, decode_except_ibus_err_o, fetch_sleep_o,
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fetch_quick_branch_o, spr_bus_dat_ic_o, spr_bus_ack_ic_o,
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// Inputs
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clk, rst, ibus_err_i, ibus_ack_i, ibus_dat_i, ic_enable, padv_i,
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branch_occur_i, branch_dest_i, ctrl_insn_done_i, du_restart_i,
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du_restart_pc_i, fetch_take_exception_branch_i, execute_waiting_i,
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du_stall_i, stepping_i, flag_i, flag_clear_i, flag_set_i,
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spr_bus_addr_i, spr_bus_we_i, spr_bus_stb_i, spr_bus_dat_i
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);
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parameter OPTION_OPERAND_WIDTH = 32;
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parameter OPTION_RF_ADDR_WIDTH = 5;
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parameter OPTION_RESET_PC = {{(OPTION_OPERAND_WIDTH-13){1'b0}},
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`OR1K_RESET_VECTOR,8'd0};
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// Mini cache registers, signals
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parameter FEATURE_INSTRUCTIONCACHE = "NONE";
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parameter OPTION_ICACHE_BLOCK_WIDTH = 3; // 3 for 8 words
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parameter FEATURE_QUICK_BRANCH_DETECTION = "NONE";
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input clk, rst;
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// interface to ibus
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output [OPTION_OPERAND_WIDTH-1:0] ibus_adr_o;
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output ibus_req_o;
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output ibus_burst_o;
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input ibus_err_i;
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input ibus_ack_i;
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input [`OR1K_INSN_WIDTH-1:0] ibus_dat_i;
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input ic_enable;
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// pipeline control input
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input padv_i;
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// interface to decode unit
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output reg [`OR1K_INSN_WIDTH-1:0] decode_insn_o;
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// PC of the current instruction, SPR_PPC basically
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output [OPTION_OPERAND_WIDTH-1:0] fetched_pc_o;
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// Indication to pipeline control that the fetch stage is ready
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output fetch_ready_o;
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// Signals going to register file to do the read access as we
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// register the instruction out to the decode stage
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output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfa_adr_o;
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output [OPTION_RF_ADDR_WIDTH-1:0] fetch_rfb_adr_o;
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output fetch_rf_re_o;
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// Signal back to the control
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output [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_o;
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// branch/jump indication
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input branch_occur_i;
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input [OPTION_OPERAND_WIDTH-1:0] branch_dest_i;
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// Instruction "retire" indication from control stage
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input ctrl_insn_done_i;
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// restart signals from debug unit
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input du_restart_i;
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input [OPTION_OPERAND_WIDTH-1:0] du_restart_pc_i;
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input fetch_take_exception_branch_i;
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input execute_waiting_i;
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// CPU is stalled
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input du_stall_i;
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// We're single stepping - this should cause us to fetch only a single insn
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input stepping_i;
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// Flag status information
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input flag_i, flag_clear_i, flag_set_i;
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// instruction ibus error indication out
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output reg decode_except_ibus_err_o;
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// fetch sleep mode enabled (due to jump-to-self instruction
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output fetch_sleep_o;
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// Indicate to the control stage that we had zero delay fetching
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// the branch target address
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output fetch_quick_branch_o;
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// SPR interface
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input [15:0] spr_bus_addr_i;
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input spr_bus_we_i;
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input spr_bus_stb_i;
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input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i;
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output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_ic_o;
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output spr_bus_ack_ic_o;
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// Registers
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reg [OPTION_OPERAND_WIDTH-1:0] pc;
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reg [OPTION_OPERAND_WIDTH-1:0] fetched_pc;
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reg fetch_req;
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reg next_insn_will_branch;
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reg have_early_pc_next;
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reg jump_insn_in_decode;
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reg took_early_calc_pc;
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reg [1:0] took_early_calc_pc_r;
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reg padv_r;
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reg took_branch;
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reg took_branch_r;
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reg execute_waiting_r;
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reg sleep;
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reg complete_current_req;
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reg no_rf_read;
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reg new_insn_wasnt_ready;
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reg took_early_pc_onto_cache_hit;
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reg waited_with_early_pc_onto_cache_hit;
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// Wires
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wire [`OR1K_INSN_WIDTH-1:0] new_insn;
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wire new_insn_ready;
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wire [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next;
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wire [OPTION_OPERAND_WIDTH-1:0] pc_plus_four;
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wire [OPTION_OPERAND_WIDTH-1:0] early_pc_next;
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wire padv_deasserted;
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wire padv_asserted;
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wire [`OR1K_OPCODE_WIDTH-1:0] next_insn_opcode;
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wire will_go_to_sleep;
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wire mini_cache_hit;
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wire mini_cache_hit_ungated;
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wire [`OR1K_INSN_WIDTH-1:0] mini_cache_insn;
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wire hold_decode_output;
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wire next_instruction_to_decode_condition;
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assign pc_plus_four = pc + 4;
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assign pc_fetch_next = have_early_pc_next ?
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early_pc_next : pc_plus_four;
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assign ibus_adr_o = pc;
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assign ibus_req_o = (fetch_req & !(fetch_take_exception_branch_i/* | branch_occur_i*/)
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// This is needed in the case that:
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// 1. a burst just finished and ack in went low because of this
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// 2. the instruction we just ACKed is a multicycle insn so the
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// execute_waiting_i goes high, but the bus interface will have
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// already put out the request onto the bus. It causes a bug
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// if we deassert the req from here 1 cycle later, so put this
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// signal into the assign logic so that the first cycle of it
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// causes req to go low, after which fetch_req is deasserted
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// and should handle it
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& !(execute_waiting_i & fetch_req)
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& !mini_cache_hit_ungated) |
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complete_current_req;
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assign ibus_burst_o = 0;
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assign fetch_ready_o = new_insn_ready | jump_insn_in_decode | ibus_err_i;
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assign pc_fetch_next_o = pc_fetch_next;
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assign new_insn = mini_cache_hit ? mini_cache_insn : ibus_dat_i;
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assign new_insn_ready = mini_cache_hit | ibus_ack_i;
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// Register file control
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assign fetch_rfa_adr_o = new_insn_ready ? new_insn[`OR1K_RA_SELECT] : 0;
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assign fetch_rfb_adr_o = new_insn_ready ? new_insn[`OR1K_RB_SELECT] : 0;
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assign fetch_rf_re_o = new_insn_ready & (padv_i | stepping_i) &
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!(no_rf_read | hold_decode_output);
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// Pick out opcode of next instruction to go to decode stage
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assign next_insn_opcode = new_insn[`OR1K_OPCODE_SELECT];
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// Can calculate next PC based on instruction coming in
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assign early_pc_next = {OPTION_OPERAND_WIDTH{have_early_pc_next}} &
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({{4{new_insn[25]}},
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new_insn[`OR1K_JUMPBRANCH_IMMEDIATE_SELECT],
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2'b00} + pc);
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assign will_go_to_sleep = have_early_pc_next &
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(early_pc_next == pc);
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assign fetch_sleep_o = sleep;
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// The pipeline advance signal deasserted for the instruction
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// we just put out, and we're still attempting to fetch. This should
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// result in a deassert cycle on the request signal out to the bus.
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// But, we don't want this to indicate when padv_i was deasserted for
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// a branch, because we will know about that, we just want this to
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// indicate it was deasserted for other reasons.
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assign padv_deasserted = padv_r & !padv_i & fetch_req & !took_branch;
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assign padv_asserted = !padv_r & padv_i;
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// This makes us hold the decode stage output for an additional
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// cycle when we've already got the next instruction in the
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// register output to the decode stage, but the pipeline has
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// stalled.
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assign hold_decode_output = (padv_asserted &
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mini_cache_hit & took_branch_r &
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!new_insn_wasnt_ready &
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took_early_calc_pc_r[1]) ||
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waited_with_early_pc_onto_cache_hit;
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always @*
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if (new_insn_ready)
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case (next_insn_opcode)
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`OR1K_OPCODE_J,
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`OR1K_OPCODE_JAL: begin
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have_early_pc_next = 1;
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next_insn_will_branch = 1;
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no_rf_read = 1;
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end
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`OR1K_OPCODE_JR,
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`OR1K_OPCODE_JALR: begin
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have_early_pc_next = 0;
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next_insn_will_branch = 1;
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no_rf_read = 0;
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end
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`OR1K_OPCODE_BNF: begin
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have_early_pc_next = !(flag_i | flag_set_i) | flag_clear_i;
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next_insn_will_branch = !(flag_i | flag_set_i) | flag_clear_i;
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no_rf_read = 1;
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end
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`OR1K_OPCODE_BF: begin
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have_early_pc_next = !(!flag_i | flag_clear_i) |flag_set_i;
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next_insn_will_branch = !(!flag_i | flag_clear_i) |flag_set_i;
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no_rf_read = 1;
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end
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`OR1K_OPCODE_SYSTRAPSYNC,
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`OR1K_OPCODE_RFE: begin
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have_early_pc_next = 0;
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next_insn_will_branch = 1;
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no_rf_read = 1;
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end
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default: begin
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have_early_pc_next = 0;
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next_insn_will_branch = 0;
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no_rf_read = 0;
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end
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endcase // case (next_insn_opcode)
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else
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begin
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have_early_pc_next = 0;
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next_insn_will_branch = 0;
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no_rf_read = 0;
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end
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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begin
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pc <= OPTION_RESET_PC;
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fetched_pc <= OPTION_RESET_PC;
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end
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else if (branch_occur_i & !took_early_calc_pc)
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begin
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pc <= branch_dest_i;
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end
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else if (fetch_take_exception_branch_i & !du_stall_i)
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begin
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pc <= branch_dest_i;
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end
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else if (new_insn_ready & (padv_i | stepping_i) &
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!hold_decode_output)
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begin
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pc <= pc_fetch_next_o;
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fetched_pc <= pc;
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end
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else if (du_restart_i)
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begin
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pc <= du_restart_pc_i;
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end
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else if (fetch_take_exception_branch_i & du_stall_i)
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begin
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pc <= du_restart_pc_i;
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end
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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new_insn_wasnt_ready <= 0;
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else if (branch_occur_i & !took_early_calc_pc)
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new_insn_wasnt_ready <= !new_insn_ready;
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else if (new_insn_ready & (padv_i | stepping_i) & !padv_deasserted)
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new_insn_wasnt_ready <= 0;
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assign fetched_pc_o = fetched_pc;
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assign next_instruction_to_decode_condition = new_insn_ready &
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(padv_i | stepping_i) &
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!padv_deasserted &
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!hold_decode_output &
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!((branch_occur_i & padv_i &
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!took_early_calc_pc) |
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fetch_take_exception_branch_i);
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always @(posedge clk `OR_ASYNC_RST)
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if (rst)
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decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
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else if (sleep | du_stall_i)
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decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
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else if (next_instruction_to_decode_condition)
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decode_insn_o <= new_insn;
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else if (branch_occur_i & padv_i)
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// We've just taken a branch, put a nop on the
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// instruction to the rest of the pipeline
|
330 |
|
|
decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
|
331 |
|
|
else if (fetch_take_exception_branch_i)
|
332 |
|
|
// Exception was just taken, get rid of whatever
|
333 |
|
|
// we're outputting
|
334 |
|
|
decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
|
335 |
|
|
else if (took_early_calc_pc)
|
336 |
|
|
// This covers the case where, for some reason,
|
337 |
|
|
// we don't get the branch_occur_i
|
338 |
|
|
decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
|
339 |
|
|
else if (ctrl_insn_done_i & !new_insn_ready)
|
340 |
|
|
// If the current instruction in the decode stage is retired
|
341 |
|
|
// then let's put a no-op back in the pipeline
|
342 |
|
|
decode_insn_o <= {`OR1K_OPCODE_NOP,26'd0};
|
343 |
|
|
|
344 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
345 |
|
|
if (rst)
|
346 |
|
|
fetch_req <= 1'b1;
|
347 |
|
|
else if (fetch_req & stepping_i & new_insn_ready)
|
348 |
|
|
// Deassert on ack
|
349 |
|
|
fetch_req <= 1'b0;
|
350 |
|
|
else if (!fetch_req & du_stall_i)
|
351 |
|
|
fetch_req <= 1'b0;
|
352 |
|
|
else if (ibus_err_i)
|
353 |
|
|
fetch_req <= 1'b0;
|
354 |
|
|
else if (sleep)
|
355 |
|
|
fetch_req <= 1'b0;
|
356 |
|
|
else if (next_insn_will_branch)
|
357 |
|
|
fetch_req <= 1'b0;
|
358 |
|
|
else if (execute_waiting_i)
|
359 |
|
|
/*
|
360 |
|
|
Put the execute wait signal through this register to break any long
|
361 |
|
|
chains of logic from the execute stage (LSU, ALU) which could result
|
362 |
|
|
from using it to just gate the req signal out.
|
363 |
|
|
TODO - actually check the impact of gating fetch_req_o with
|
364 |
|
|
execute_waiting_i
|
365 |
|
|
*/
|
366 |
|
|
fetch_req <= 1'b0;
|
367 |
|
|
else if (padv_deasserted)
|
368 |
|
|
fetch_req <= 1'b0;
|
369 |
|
|
else if (mini_cache_hit_ungated)
|
370 |
|
|
// We'll get this ungated signal immediately after we've
|
371 |
|
|
// terminated a burst, so we'll know if we really should
|
372 |
|
|
// fetch the branch target or whether it's in cache.
|
373 |
|
|
fetch_req <= 1'b0;
|
374 |
|
|
else
|
375 |
|
|
fetch_req <= 1'b1;
|
376 |
|
|
|
377 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
378 |
|
|
if (rst)
|
379 |
|
|
took_early_pc_onto_cache_hit <= 0;
|
380 |
|
|
else if (padv_i)
|
381 |
|
|
took_early_pc_onto_cache_hit <= took_early_calc_pc & mini_cache_hit &
|
382 |
|
|
!fetch_take_exception_branch_i;
|
383 |
|
|
else if (ctrl_insn_done_i)
|
384 |
|
|
took_early_pc_onto_cache_hit <= 0;
|
385 |
|
|
|
386 |
|
|
// This register signifies when:
|
387 |
|
|
// a) we had a branch to somewhere where we took the early calculated PC and
|
388 |
|
|
// that branch location was a hit in the cache
|
389 |
|
|
// b) the subsequent instruction wasn't in the cache, so we put the
|
390 |
|
|
// insn out to the decode stage, but wasn't immediately retired by the
|
391 |
|
|
// control stage, so we must wait until the next instruction is ready
|
392 |
|
|
// before it will be completed by the control stage
|
393 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
394 |
|
|
if (rst)
|
395 |
|
|
waited_with_early_pc_onto_cache_hit <= 0;
|
396 |
|
|
else if (took_branch_r | padv_i)
|
397 |
|
|
waited_with_early_pc_onto_cache_hit <= took_early_pc_onto_cache_hit &
|
398 |
|
|
!fetch_ready_o;
|
399 |
|
|
else if (ctrl_insn_done_i)
|
400 |
|
|
waited_with_early_pc_onto_cache_hit <= 0;
|
401 |
|
|
|
402 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
403 |
|
|
if (rst)
|
404 |
|
|
jump_insn_in_decode <= 0;
|
405 |
|
|
else if (sleep)
|
406 |
|
|
jump_insn_in_decode <= 0;
|
407 |
|
|
else if (!jump_insn_in_decode & next_insn_will_branch & new_insn_ready & padv_i)
|
408 |
|
|
jump_insn_in_decode <= 1;
|
409 |
|
|
else
|
410 |
|
|
jump_insn_in_decode <= 0;
|
411 |
|
|
|
412 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
413 |
|
|
if (rst)
|
414 |
|
|
took_early_calc_pc <= 0;
|
415 |
|
|
else if (sleep)
|
416 |
|
|
took_early_calc_pc <= 0;
|
417 |
|
|
else if (next_insn_will_branch & have_early_pc_next & padv_i)
|
418 |
|
|
took_early_calc_pc <= 1;
|
419 |
|
|
else
|
420 |
|
|
took_early_calc_pc <= 0;
|
421 |
|
|
|
422 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
423 |
|
|
if (rst)
|
424 |
|
|
took_early_calc_pc_r <= 0;
|
425 |
|
|
else
|
426 |
|
|
took_early_calc_pc_r <= {took_early_calc_pc_r[0], took_early_calc_pc};
|
427 |
|
|
|
428 |
|
|
always @(posedge clk)
|
429 |
|
|
padv_r <= padv_i;
|
430 |
|
|
|
431 |
|
|
/* Whether it was early branch or not, we've branched, and this
|
432 |
|
|
signal will be asserted the cycle after. */
|
433 |
|
|
always @(posedge clk)
|
434 |
|
|
begin
|
435 |
|
|
took_branch <= (branch_occur_i | fetch_take_exception_branch_i) &
|
436 |
|
|
fetch_ready_o;
|
437 |
|
|
took_branch_r <= took_branch;
|
438 |
|
|
end
|
439 |
|
|
|
440 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
441 |
|
|
if (rst)
|
442 |
|
|
decode_except_ibus_err_o <= 0;
|
443 |
|
|
else if ((padv_i | fetch_take_exception_branch_i) &
|
444 |
|
|
branch_occur_i | du_stall_i)
|
445 |
|
|
decode_except_ibus_err_o <= 0;
|
446 |
|
|
else if (fetch_req)
|
447 |
|
|
decode_except_ibus_err_o <= ibus_err_i;
|
448 |
|
|
|
449 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
450 |
|
|
if (rst)
|
451 |
|
|
sleep <= 1'b0;
|
452 |
|
|
else if (fetch_take_exception_branch_i | du_stall_i)
|
453 |
|
|
sleep <= 1'b0;
|
454 |
|
|
else if (will_go_to_sleep & !stepping_i)
|
455 |
|
|
sleep <= 1'b1;
|
456 |
|
|
|
457 |
|
|
// A signal to make sure the request out line stays high
|
458 |
|
|
// if we've already issued an instruction request and padv_i
|
459 |
|
|
// goes low.
|
460 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
461 |
|
|
if (rst)
|
462 |
|
|
complete_current_req <= 0;
|
463 |
|
|
else if (fetch_req & padv_deasserted & !new_insn_ready)
|
464 |
|
|
complete_current_req <= 1;
|
465 |
|
|
else if (new_insn_ready & complete_current_req)
|
466 |
|
|
complete_current_req <= 0;
|
467 |
|
|
|
468 |
|
|
// Mini cache logic
|
469 |
|
|
genvar i;
|
470 |
|
|
generate
|
471 |
|
|
/* verilator lint_off WIDTH */
|
472 |
|
|
if (FEATURE_INSTRUCTIONCACHE != "ENABLED")
|
473 |
|
|
/* verilator lint_on WIDTH */
|
474 |
|
|
begin : no_mini_cache
|
475 |
|
|
assign mini_cache_hit = 0;
|
476 |
|
|
assign mini_cache_hit_ungated = 0;
|
477 |
|
|
assign mini_cache_insn = {`OR1K_INSN_WIDTH{1'b0}};
|
478 |
|
|
assign fetch_quick_branch_o = 0;
|
479 |
|
|
end
|
480 |
|
|
else
|
481 |
|
|
begin : mini_cache
|
482 |
|
|
localparam NUMBER_MINI_CACHE_WORDS = (1<<OPTION_ICACHE_BLOCK_WIDTH);
|
483 |
|
|
localparam MINI_CACHE_TAG_END = OPTION_ICACHE_BLOCK_WIDTH+2;
|
484 |
|
|
|
485 |
|
|
reg mini_cache_tag_valid [0:NUMBER_MINI_CACHE_WORDS-1];
|
486 |
|
|
wire mini_cache_fill_condition;
|
487 |
|
|
wire invalidate;
|
488 |
|
|
reg [`OR1K_INSN_WIDTH-1:0] mini_cache [0:NUMBER_MINI_CACHE_WORDS-1];
|
489 |
|
|
reg [OPTION_OPERAND_WIDTH-1:MINI_CACHE_TAG_END] mini_cache_tag [0:NUMBER_MINI_CACHE_WORDS-1];
|
490 |
|
|
wire [OPTION_OPERAND_WIDTH-1:MINI_CACHE_TAG_END] pc_tag;
|
491 |
|
|
wire [OPTION_ICACHE_BLOCK_WIDTH-1:0] pc_word_sel;
|
492 |
|
|
wire [`OR1K_INSN_WIDTH-1:0] mini_cache_branch_dest_insn;
|
493 |
|
|
|
494 |
|
|
// This is the address we'll write into the tag
|
495 |
|
|
assign pc_word_sel = pc[OPTION_ICACHE_BLOCK_WIDTH+1:2];
|
496 |
|
|
assign pc_tag = pc[OPTION_OPERAND_WIDTH-1:MINI_CACHE_TAG_END];
|
497 |
|
|
|
498 |
|
|
assign mini_cache_hit_ungated = mini_cache_tag_valid[pc_word_sel] &
|
499 |
|
|
mini_cache_tag[pc_word_sel]==pc_tag;
|
500 |
|
|
|
501 |
|
|
assign mini_cache_hit = mini_cache_hit_ungated & !took_branch &
|
502 |
|
|
!fetch_take_exception_branch_i;
|
503 |
|
|
|
504 |
|
|
assign mini_cache_insn = mini_cache[pc_word_sel];
|
505 |
|
|
|
506 |
|
|
assign mini_cache_fill_condition = ibus_ack_i & !ibus_err_i &
|
507 |
|
|
!will_go_to_sleep;
|
508 |
|
|
|
509 |
|
|
assign invalidate = spr_bus_stb_i & spr_bus_we_i &
|
510 |
|
|
(spr_bus_addr_i == `OR1K_SPR_ICBIR_ADDR);
|
511 |
|
|
|
512 |
|
|
assign fetch_quick_branch_o = took_branch & mini_cache_hit;
|
513 |
|
|
|
514 |
|
|
assign spr_bus_ack_ic_o = 1'b1;
|
515 |
|
|
|
516 |
|
|
for (i=0;i<NUMBER_MINI_CACHE_WORDS;i=i+1)
|
517 |
|
|
begin : flop_cache_control
|
518 |
|
|
always @(posedge clk `OR_ASYNC_RST)
|
519 |
|
|
if (rst)
|
520 |
|
|
begin
|
521 |
|
|
mini_cache_tag[i] <= 'd0;
|
522 |
|
|
mini_cache_tag_valid[i] <= 1'b0;
|
523 |
|
|
end
|
524 |
|
|
else if (invalidate/* | !ic_enable*/ | du_stall_i)
|
525 |
|
|
begin
|
526 |
|
|
// Invalidate all tags on:
|
527 |
|
|
// 1) any write to the block-invalidate register
|
528 |
|
|
// 2) when the cache isn't enabled
|
529 |
|
|
// 3) whenever we're stalled - things may change
|
530 |
|
|
// under our feet and it helps make things
|
531 |
|
|
// easy when coming out of stall or stepping
|
532 |
|
|
mini_cache_tag_valid[i] <= 1'b0;
|
533 |
|
|
end
|
534 |
|
|
else if (mini_cache_fill_condition &
|
535 |
|
|
pc_word_sel==i[OPTION_ICACHE_BLOCK_WIDTH-1:0])
|
536 |
|
|
begin
|
537 |
|
|
mini_cache_tag[i] <= pc_tag;
|
538 |
|
|
mini_cache_tag_valid[i] <= 1'b1;
|
539 |
|
|
mini_cache[i] <= ibus_dat_i;
|
540 |
|
|
end
|
541 |
|
|
end
|
542 |
|
|
|
543 |
|
|
end // block: mini_cache
|
544 |
|
|
endgenerate
|
545 |
|
|
|
546 |
|
|
assign spr_bus_ack_ic_o = 1'b1;
|
547 |
|
|
assign spr_bus_dat_ic_o = {OPTION_OPERAND_WIDTH{1'b0}};
|
548 |
|
|
|
549 |
|
|
endmodule // mor1kx_fetch_prontoespresso
|