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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx_pcu.v] - Blame information for rev 48

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1 48 alirezamon 
/* ****************************************************************************
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  This Source Code Form is subject to the terms of the
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  Open Hardware Description License, v. 1.0. If a copy
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  of the OHDL was not distributed with this file, You
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  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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  Description: mor1kx Perfomance Counters Unit
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  Copyright (C) 2016 Authors
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  Author(s): Alexey Baturo <baturo.alexey@gmail.com>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_pcu
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  #(
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    parameter OPTION_PERFCOUNTERS_NUM = 7
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  )
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  (
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   input clk,
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   input rst,
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   // SPR Bus interface
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   input         spr_access_i,
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   input         spr_we_i,
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   input         spr_re_i,
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   input [15:0]  spr_addr_i,
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   input [31:0]  spr_dat_i,
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   output        spr_bus_ack,
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   output [31:0] spr_dat_o,
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   // Current cpu mode: user/supervisor
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   input         spr_sys_mode_i,
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   // Events that can occur
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   input         pcu_event_load_i,            // track load insn
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   input         pcu_event_store_i,           // track store insn
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   input         pcu_event_ifetch_i,          // track insn fetch
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   input         pcu_event_dcache_miss_i,     // track data cache miss
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   input         pcu_event_icache_miss_i,     // track insn cache miss
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   input         pcu_event_ifetch_stall_i,    // track SOME stall
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   input         pcu_event_lsu_stall_i,       // track LSU stall
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   input         pcu_event_brn_stall_i,       // track brn miss
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   input         pcu_event_dtlb_miss_i,       // track data tlb miss
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   input         pcu_event_itlb_miss_i,       // track insn tlb miss
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   input         pcu_event_datadep_stall_i    // track SOME stall
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   );
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   // Registers
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   reg [31:0]    pcu_pccr[0:OPTION_PERFCOUNTERS_NUM];
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   reg [31:0]    pcu_pcmr[0:OPTION_PERFCOUNTERS_NUM];
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   wire pcu_pccr_access;
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   wire pcu_pcmr_access;
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   // check if we access pcu
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   // TODO: generate this signals according to present units
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   assign pcu_pccr_access =
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     spr_access_i &
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     ((`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR0_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR1_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR2_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR3_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR4_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR5_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR6_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCCR7_ADDR)));
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   assign pcu_pcmr_access =
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     spr_access_i &
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     ((`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR0_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR1_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR2_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR3_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR4_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR5_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR6_ADDR)) |
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      (`SPR_OFFSET(spr_addr_i) == `SPR_OFFSET(`OR1K_SPR_PCMR7_ADDR)));
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   // put data on data bus
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   assign spr_bus_ack = spr_access_i;
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   assign spr_dat_o   = (spr_access_i & pcu_pccr_access & spr_re_i) ? pcu_pccr[spr_addr_i[2:0]] :
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                        (spr_access_i & pcu_pcmr_access & spr_re_i & spr_sys_mode_i) ? pcu_pcmr[spr_addr_i[2:0]] :
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                        0;
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   genvar pcu_num;
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   generate
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      for(pcu_num = 0; pcu_num < OPTION_PERFCOUNTERS_NUM + 1; pcu_num = pcu_num + 1) begin: pcu_generate
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         wire [`OR1K_PCMR_DDS:`OR1K_PCMR_LA] pcu_events_active;
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         wire [`OR1K_PCMR_DDS:`OR1K_PCMR_LA] pcu_events_hit;
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         assign pcu_events_active =
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            (pcu_event_load_i << `OR1K_PCMR_LA) |
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            (pcu_event_store_i << `OR1K_PCMR_SA) |
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            (pcu_event_ifetch_i << `OR1K_PCMR_IF) |
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            (pcu_event_dcache_miss_i << `OR1K_PCMR_DCM) |
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            (pcu_event_icache_miss_i << `OR1K_PCMR_ICM) |
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            (pcu_event_ifetch_stall_i << `OR1K_PCMR_IFS) |
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            (pcu_event_lsu_stall_i << `OR1K_PCMR_LSUS) |
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            (pcu_event_brn_stall_i << `OR1K_PCMR_BS) |
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            (pcu_event_dtlb_miss_i << `OR1K_PCMR_DTLBM) |
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            (pcu_event_itlb_miss_i << `OR1K_PCMR_ITLBM) |
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            (pcu_event_datadep_stall_i << `OR1K_PCMR_DDS);
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         assign pcu_events_hit =
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            pcu_events_active & pcu_pcmr[pcu_num];
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         always @(posedge clk `OR_ASYNC_RST) begin
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            if (rst) begin
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               pcu_pccr[pcu_num] <= 32'd0;
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               pcu_pcmr[pcu_num] <= 32'd0 | 1 << `OR1K_PCMR_CP;
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            // we could write pcu registers only in system mode
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            end else if (spr_we_i && spr_sys_mode_i) begin
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               if (pcu_pccr_access & (spr_addr_i[2:0] == pcu_num))
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                  pcu_pccr[pcu_num] <= spr_dat_i;
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               // WPE are not implemented, hence we do not update WPE part
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               if (pcu_pcmr_access && (spr_addr_i[2:0] == pcu_num)) begin
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                  pcu_pcmr[pcu_num][`OR1K_PCMR_DDS:`OR1K_PCMR_CISM] <=
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                     spr_dat_i[`OR1K_PCMR_DDS:`OR1K_PCMR_CISM];
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               end
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            end else if (((pcu_pcmr[pcu_num][`OR1K_PCMR_CISM] & spr_sys_mode_i) |
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                       (pcu_pcmr[pcu_num][`OR1K_PCMR_CIUM] & ~spr_sys_mode_i))) begin
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               pcu_pccr[pcu_num] <= pcu_pccr[pcu_num] +
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                  pcu_events_hit[`OR1K_PCMR_LA] +
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                  pcu_events_hit[`OR1K_PCMR_SA] +
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                  pcu_events_hit[`OR1K_PCMR_IF] +
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                  pcu_events_hit[`OR1K_PCMR_DCM] +
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                  pcu_events_hit[`OR1K_PCMR_ICM] +
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                  pcu_events_hit[`OR1K_PCMR_IFS] +
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                  pcu_events_hit[`OR1K_PCMR_LSUS] +
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                  pcu_events_hit[`OR1K_PCMR_BS] +
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                  pcu_events_hit[`OR1K_PCMR_DTLBM] +
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                  pcu_events_hit[`OR1K_PCMR_ITLBM] +
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                  pcu_events_hit[`OR1K_PCMR_DDS];
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            end
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         end
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      end
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   endgenerate
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endmodule // mor1kx_pcu

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