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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx_wb_mux_cappuccino.v] - Blame information for rev 48

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/* ****************************************************************************
  This Source Code Form is subject to the terms of the
  Open Hardware Description License, v. 1.0. If a copy
  of the OHDL was not distributed with this file, You
  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
 
  Description: RF writeback mux
 
  Choose between ALU and LSU input.
 
  Copyright (C) 2012 Authors
 
  Author(s): Julius Baxter <juliusbaxter@gmail.com>
 
***************************************************************************** */
 
`include "mor1kx-defines.v"
 
module mor1kx_wb_mux_cappuccino
  #(
    parameter OPTION_OPERAND_WIDTH = 32
    )
   (
    input                             clk,
    input                             rst,
 
    input [OPTION_OPERAND_WIDTH-1:0]  alu_result_i,
    input [OPTION_OPERAND_WIDTH-1:0]  lsu_result_i,
    input [OPTION_OPERAND_WIDTH-1:0]  mul_result_i,
    input [OPTION_OPERAND_WIDTH-1:0]  spr_i,
 
    output [OPTION_OPERAND_WIDTH-1:0] rf_result_o,
 
    input                             op_mul_i,
    input                             op_lsu_load_i,
    input                             op_mfspr_i
    );
 
   reg [OPTION_OPERAND_WIDTH-1:0]     rf_result;
   reg                                wb_op_mul;
 
   assign rf_result_o = wb_op_mul ? mul_result_i : rf_result;
 
   always @(posedge clk)
     if (op_mfspr_i)
       rf_result <= spr_i;
     else if (op_lsu_load_i)
       rf_result <= lsu_result_i;
     else
       rf_result <= alu_result_i;
 
   always @(posedge clk)
     wb_op_mul <= op_mul_i;
 
endmodule // mor1kx_wb_mux_cappuccino

Line No.	Rev	Author	Line
1	48	alirezamon	`/* ****************************************************************************`
2			`This Source Code Form is subject to the terms of the`
3			`Open Hardware Description License, v. 1.0. If a copy`
4			`of the OHDL was not distributed with this file, You`
5			`can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt`
6
7			`Description: RF writeback mux`
8
9			`Choose between ALU and LSU input.`
10
11			`Copyright (C) 2012 Authors`
12
13			`Author(s): Julius Baxter <juliusbaxter@gmail.com>`
14
15			`***************************************************************************** */`
16
17			`include "mor1kx-defines.v"
18
19			`module mor1kx_wb_mux_cappuccino`
20			`#(`
21			`parameter OPTION_OPERAND_WIDTH = 32`
22			`)`
23			`(`
24			`input clk,`
25			`input rst,`
26
27			`input [OPTION_OPERAND_WIDTH-1:0] alu_result_i,`
28			`input [OPTION_OPERAND_WIDTH-1:0] lsu_result_i,`
29			`input [OPTION_OPERAND_WIDTH-1:0] mul_result_i,`
30			`input [OPTION_OPERAND_WIDTH-1:0] spr_i,`
31
32			`output [OPTION_OPERAND_WIDTH-1:0] rf_result_o,`
33
34			`input op_mul_i,`
35			`input op_lsu_load_i,`
36			`input op_mfspr_i`
37			`);`
38
39			`reg [OPTION_OPERAND_WIDTH-1:0] rf_result;`
40			`reg wb_op_mul;`
41
42			`assign rf_result_o = wb_op_mul ? mul_result_i : rf_result;`
43
44			`always @(posedge clk)`
45			`if (op_mfspr_i)`
46			`rf_result <= spr_i;`
47			`else if (op_lsu_load_i)`
48			`rf_result <= lsu_result_i;`
49			`else`
50			`rf_result <= alu_result_i;`
51
52			`always @(posedge clk)`
53			`wb_op_mul <= op_mul_i;`
54
55			`endmodule // mor1kx_wb_mux_cappuccino`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx_wb_mux_cappuccino.v] - Blame information for rev 48