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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [mor1kx_wb_mux_espresso.v] - Blame information for rev 48

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1 48 alirezamon
/* ****************************************************************************
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  This Source Code Form is subject to the terms of the
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  Open Hardware Description License, v. 1.0. If a copy
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  of the OHDL was not distributed with this file, You
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  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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  Description: RF writeback mux for espresso pipeline
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  Choose between ALU and LSU input. All combinatorial
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  Copyright (C) 2012 Authors
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  Author(s): Julius Baxter <juliusbaxter@gmail.com>
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***************************************************************************** */
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`include "mor1kx-defines.v"
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module mor1kx_wb_mux_espresso
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  (/*AUTOARG*/
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   // Outputs
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   rf_result_o,
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   // Inputs
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   clk, rst, alu_result_i, lsu_result_i, ppc_i, pc_fetch_next_i,
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   spr_i, op_jal_i, op_lsu_load_i, op_mfspr_i
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   );
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   parameter OPTION_OPERAND_WIDTH = 32;
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   input clk, rst;
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   input [OPTION_OPERAND_WIDTH-1:0] alu_result_i;
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   input [OPTION_OPERAND_WIDTH-1:0] lsu_result_i;
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   input [OPTION_OPERAND_WIDTH-1:0] ppc_i;
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   input [OPTION_OPERAND_WIDTH-1:0] pc_fetch_next_i;
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   input [OPTION_OPERAND_WIDTH-1:0] spr_i;
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   output [OPTION_OPERAND_WIDTH-1:0] rf_result_o;
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   input                              op_jal_i;
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   input                              op_lsu_load_i;
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   input                              op_mfspr_i;
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   assign rf_result_o = op_lsu_load_i ? lsu_result_i :
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                        op_mfspr_i ? spr_i :
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                        // Use the PC we've calcuated from the fetch unit
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                        // to save inferring a 32-bit adder here like we
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                        // would if we did "ppc_i + 8"
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                        op_jal_i ? pc_fetch_next_i:
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                        alu_result_i;
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endmodule // mor1kx_wb_mux_espresso

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