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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [pfpu32/] [pfpu32_cmp.v] - Blame information for rev 48

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1 48 alirezamon 
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  pfpu32_cmp                                                 ////
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////  32-bit floating point comparision                          ////
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////                                                             ////
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////  Author: Rudolf Usselmann                                   ////
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////          rudi@asics.ws                                      ////
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////                                                             ////
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////  Modified by Julius Baxter, July, 2010                      ////
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////              julius.baxter@orsoc.se                         ////
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////                                                             ////
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////  Update for mor1kx, bug fixing and further development      ////
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////              Andrey Bacherov, 2014,                         ////
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////              avbacherov@opencores.org                       ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000 Rudolf Usselmann                         ////
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////                    rudi@asics.ws                            ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`include "mor1kx-defines.v"
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/* completely combinatorial module */
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module pfpu32_fcmp
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(
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  input                                     fpu_op_is_comp_i,
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  input [`OR1K_FPUOP_GENERIC_CMP_WIDTH-1:0] generic_cmp_opc_i, // ordered/unordered
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  input                                     unordered_cmp_bit_i, // is unorderd
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  // operand 'a' related inputs
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  input        signa_i,
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  input  [9:0] exp10a_i,
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  input [23:0] fract24a_i,
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  input        snana_i,
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  input        qnana_i,
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  input        infa_i,
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  input        zeroa_i,
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  // operand 'b' related inputs
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  input        signb_i,
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  input  [9:0] exp10b_i,
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  input [23:0] fract24b_i,
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  input        snanb_i,
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  input        qnanb_i,
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  input        infb_i,
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  input        zerob_i,
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  // support addsub
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  output addsub_agtb_o,
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  output addsub_aeqb_o,
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  // outputs
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  output cmp_flag_o, inv_o, inf_o, ready_o
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);
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// Full length ordered comparison opcodes
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localparam [`OR1K_FPUOP_WIDTH-1:0] FPCOP_SFEQ = `OR1K_FPCOP_SFEQ;
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localparam [`OR1K_FPUOP_WIDTH-1:0] FPCOP_SFNE = `OR1K_FPCOP_SFNE;
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localparam [`OR1K_FPUOP_WIDTH-1:0] FPCOP_SFGT = `OR1K_FPCOP_SFGT;
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localparam [`OR1K_FPUOP_WIDTH-1:0] FPCOP_SFGE = `OR1K_FPCOP_SFGE;
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localparam [`OR1K_FPUOP_WIDTH-1:0] FPCOP_SFLT = `OR1K_FPCOP_SFLT;
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localparam [`OR1K_FPUOP_WIDTH-1:0] FPCOP_SFLE = `OR1K_FPCOP_SFLE;
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// For ordered / unordered comparison
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localparam [`OR1K_FPUOP_GENERIC_CMP_WIDTH-1:0] GENERIC_SFEQ = FPCOP_SFEQ[`OR1K_FPUOP_GENERIC_CMP_SELECT];
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localparam [`OR1K_FPUOP_GENERIC_CMP_WIDTH-1:0] GENERIC_SFNE = FPCOP_SFNE[`OR1K_FPUOP_GENERIC_CMP_SELECT];
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localparam [`OR1K_FPUOP_GENERIC_CMP_WIDTH-1:0] GENERIC_SFGT = FPCOP_SFGT[`OR1K_FPUOP_GENERIC_CMP_SELECT];
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localparam [`OR1K_FPUOP_GENERIC_CMP_WIDTH-1:0] GENERIC_SFGE = FPCOP_SFGE[`OR1K_FPUOP_GENERIC_CMP_SELECT];
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localparam [`OR1K_FPUOP_GENERIC_CMP_WIDTH-1:0] GENERIC_SFLT = FPCOP_SFLT[`OR1K_FPUOP_GENERIC_CMP_SELECT];
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localparam [`OR1K_FPUOP_GENERIC_CMP_WIDTH-1:0] GENERIC_SFLE = FPCOP_SFLE[`OR1K_FPUOP_GENERIC_CMP_SELECT];
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////////////////////////////////////////////////////////////////////////
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//
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// Exception Logic
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//
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// Analysis of operands
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wire qnan = qnana_i | qnanb_i;
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wire snan = snana_i | snanb_i;
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wire anan = qnan | snan;
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//  Comparison is ordered/unordered EQ/NE
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wire eqne = (generic_cmp_opc_i == GENERIC_SFEQ) |
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            (generic_cmp_opc_i == GENERIC_SFNE);
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// Comparison is invalid if:
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//  1) sNaN is an operand of ordered/unordered EQ/NE comparison
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//  2)  NaN is an operand of ordered LT/LE/GT/GE comparison
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wire inv_cmp = (eqne & snan) | ((~eqne) & anan & (~unordered_cmp_bit_i));
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////////////////////////////////////////////////////////////////////////
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//
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// Comparison Logic
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//
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wire exp_gt = exp10a_i  > exp10b_i;
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wire exp_eq = exp10a_i == exp10b_i;
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wire exp_lt = (~exp_gt) & (~exp_eq); // exp10a_i  < exp10b_i;
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wire fract_gt = fract24a_i  > fract24b_i;
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wire fract_eq = fract24a_i == fract24b_i;
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wire fract_lt = (~fract_gt) & (~fract_eq); // fract24a_i  < fract24b_i;
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wire all_zero = zeroa_i & zerob_i;
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reg altb, blta, aeqb;
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always @( qnan or snan or infa_i or infb_i or signa_i or signb_i or
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          exp_eq or exp_gt or exp_lt or
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          fract_eq or fract_gt or fract_lt or all_zero)
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  casez( {qnan, snan, infa_i, infb_i, signa_i, signb_i,
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          exp_eq, exp_gt, exp_lt,
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          fract_eq, fract_gt, fract_lt, all_zero})
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    13'b1?_??_??_???_???_?: {blta, altb, aeqb} = 3'b000; // qnan
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    13'b?1_??_??_???_???_?: {blta, altb, aeqb} = 3'b000; // snan
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    13'b00_11_00_???_???_?: {blta, altb, aeqb} = 3'b001; // both op INF comparisson
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    13'b00_11_01_???_???_?: {blta, altb, aeqb} = 3'b100;
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    13'b00_11_10_???_???_?: {blta, altb, aeqb} = 3'b010;
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    13'b00_11_11_???_???_?: {blta, altb, aeqb} = 3'b001;
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    13'b00_10_00_???_???_?: {blta, altb, aeqb} = 3'b100; // opa_i INF comparisson
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    13'b00_10_01_???_???_?: {blta, altb, aeqb} = 3'b100;
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    13'b00_10_10_???_???_?: {blta, altb, aeqb} = 3'b010;
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    13'b00_10_11_???_???_?: {blta, altb, aeqb} = 3'b010;
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    13'b00_01_00_???_???_?: {blta, altb, aeqb} = 3'b010; // opb_i INF comparisson
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    13'b00_01_01_???_???_?: {blta, altb, aeqb} = 3'b100;
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    13'b00_01_10_???_???_?: {blta, altb, aeqb} = 3'b010;
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    13'b00_01_11_???_???_?: {blta, altb, aeqb} = 3'b100;
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    13'b00_00_10_???_???_0: {blta, altb, aeqb} = 3'b010; //compare base on sign
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    13'b00_00_01_???_???_0: {blta, altb, aeqb} = 3'b100; //compare base on sign
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    13'b00_00_??_???_???_1: {blta, altb, aeqb} = 3'b001; //compare base on sign both are zero
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    13'b00_00_00_010_???_?: {blta, altb, aeqb} = 3'b100; // cmp exp, equal sign
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    13'b00_00_00_001_???_?: {blta, altb, aeqb} = 3'b010;
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    13'b00_00_11_010_???_?: {blta, altb, aeqb} = 3'b010;
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    13'b00_00_11_001_???_?: {blta, altb, aeqb} = 3'b100;
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    13'b00_00_00_100_010_?: {blta, altb, aeqb} = 3'b100; // compare fractions, equal sign, equal exp
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    13'b00_00_00_100_001_?: {blta, altb, aeqb} = 3'b010;
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    13'b00_00_11_100_010_?: {blta, altb, aeqb} = 3'b010;
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    13'b00_00_11_100_001_?: {blta, altb, aeqb} = 3'b100;
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    13'b00_00_00_100_100_?: {blta, altb, aeqb} = 3'b001;
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    13'b00_00_11_100_100_?: {blta, altb, aeqb} = 3'b001;
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    default: {blta, altb, aeqb} = 3'b000;
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  endcase
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////////////////////////////////////////////////////////////////////////
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// Comparison cmp_flag generation
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reg  generic_cmp_flag; // ordered / unordered
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wire cmp_flag = (unordered_cmp_bit_i & anan) | generic_cmp_flag;
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// ---
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always @(altb or blta or aeqb or generic_cmp_opc_i) begin
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  case (generic_cmp_opc_i) // synthesis parallel_case
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    GENERIC_SFEQ: generic_cmp_flag = aeqb;
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    GENERIC_SFNE: generic_cmp_flag = ~aeqb;
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    GENERIC_SFGT: generic_cmp_flag = blta & ~aeqb;
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    GENERIC_SFGE: generic_cmp_flag = blta | aeqb;
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    GENERIC_SFLT: generic_cmp_flag = altb & ~aeqb;
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    GENERIC_SFLE: generic_cmp_flag = altb | aeqb;
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    default:      generic_cmp_flag = 1'b0;
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  endcase
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end // always@ *
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////////////////////////////////////////////////////////////////////////
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// output (latching is perfommed on FPU top level)
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assign addsub_agtb_o = exp_gt | (exp_eq & fract_gt);
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assign addsub_aeqb_o = exp_eq & fract_eq;
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assign cmp_flag_o = cmp_flag;
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assign inv_o      = inv_cmp;
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assign inf_o      = infa_i | infb_i;
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assign ready_o    = fpu_op_is_comp_i;
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endmodule // pfpu32_fcmp

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