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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [mor1kx-5.0/] [rtl/] [verilog/] [pfpu32/] [pfpu32_i2f.v] - Blame information for rev 48

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1 48 alirezamon 
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  pfpu32_i2f                                                 ////
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////  32-bit integer to floating point converter                 ////
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////                                                             ////
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////  Author: Andrey Bacherov                                    ////
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////          avbacherov@opencores.org                           ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2014 Andrey Bacherov                          ////
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////                    avbacherov@opencores.org                 ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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`include "mor1kx-defines.v"
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module pfpu32_i2f
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(
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   input             clk,
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   input             rst,
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   input             flush_i,  // flush pipe
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   input             adv_i,    // advance pipe
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   input             start_i,  // start conversion
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   input      [31:0] opa_i,
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   output reg        i2f_rdy_o,       // i2f is ready
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   output reg        i2f_sign_o,      // i2f signum
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   output reg  [3:0] i2f_shr_o,
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   output reg  [7:0] i2f_exp8shr_o,
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   output reg  [4:0] i2f_shl_o,
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   output reg  [7:0] i2f_exp8shl_o,
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   output reg  [7:0] i2f_exp8sh0_o,
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   output reg [31:0] i2f_fract32_o
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);
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  /*
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     Any stage's output is registered.
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     Definitions:
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       s??o_name - "S"tage number "??", "O"utput
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       s??t_name - "S"tage number "??", "T"emporary (internally)
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  */
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  // signum of input
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  wire s1t_signa = opa_i[31];
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  // magnitude (tow's complement for negative input)
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  wire [31:0] s1t_fract32 =
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      (opa_i ^ {32{s1t_signa}}) + {31'd0,s1t_signa};
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  // normalization shifts
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  reg [3:0] s1t_shrx;
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  reg [4:0] s1t_shlx;
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  // shift goal:
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  // 23 22                    0
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  // |  |                     |
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  // h  fffffffffffffffffffffff
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  // right shift
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  always @(s1t_fract32[31:24]) begin
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    casez(s1t_fract32[31:24])  // synopsys full_case parallel_case
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      8'b1???????:  s1t_shrx = 4'd8;
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      8'b01??????:  s1t_shrx = 4'd7;
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      8'b001?????:  s1t_shrx = 4'd6;
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      8'b0001????:  s1t_shrx = 4'd5;
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      8'b00001???:  s1t_shrx = 4'd4;
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      8'b000001??:  s1t_shrx = 4'd3;
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      8'b0000001?:  s1t_shrx = 4'd2;
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      8'b00000001:  s1t_shrx = 4'd1;
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      8'b00000000:  s1t_shrx = 4'd0;
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    endcase
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  end
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  // left shift
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  always @(s1t_fract32[23:0]) begin
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    casez(s1t_fract32[23:0])  // synopsys full_case parallel_case
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      24'b1???????????????????????:  s1t_shlx = 5'd0; // hidden '1' is in its plase
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      24'b01??????????????????????:  s1t_shlx = 5'd1;
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      24'b001?????????????????????:  s1t_shlx = 5'd2;
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      24'b0001????????????????????:  s1t_shlx = 5'd3;
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      24'b00001???????????????????:  s1t_shlx = 5'd4;
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      24'b000001??????????????????:  s1t_shlx = 5'd5;
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      24'b0000001?????????????????:  s1t_shlx = 5'd6;
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      24'b00000001????????????????:  s1t_shlx = 5'd7;
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      24'b000000001???????????????:  s1t_shlx = 5'd8;
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      24'b0000000001??????????????:  s1t_shlx = 5'd9;
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      24'b00000000001?????????????:  s1t_shlx = 5'd10;
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      24'b000000000001????????????:  s1t_shlx = 5'd11;
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      24'b0000000000001???????????:  s1t_shlx = 5'd12;
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      24'b00000000000001??????????:  s1t_shlx = 5'd13;
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      24'b000000000000001?????????:  s1t_shlx = 5'd14;
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      24'b0000000000000001????????:  s1t_shlx = 5'd15;
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      24'b00000000000000001???????:  s1t_shlx = 5'd16;
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      24'b000000000000000001??????:  s1t_shlx = 5'd17;
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      24'b0000000000000000001?????:  s1t_shlx = 5'd18;
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      24'b00000000000000000001????:  s1t_shlx = 5'd19;
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      24'b000000000000000000001???:  s1t_shlx = 5'd20;
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      24'b0000000000000000000001??:  s1t_shlx = 5'd21;
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      24'b00000000000000000000001?:  s1t_shlx = 5'd22;
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      24'b000000000000000000000001:  s1t_shlx = 5'd23;
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      24'b000000000000000000000000:  s1t_shlx = 5'd0;
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    endcase
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  end
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  // registering output
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  always @(posedge clk) begin
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    if(adv_i) begin
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        // computation related
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      i2f_sign_o    <= s1t_signa;
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      i2f_shr_o     <= s1t_shrx;
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      i2f_exp8shr_o <= 8'd150 + {4'd0,s1t_shrx};      // 150=127+23
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      i2f_shl_o     <= s1t_shlx;
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      i2f_exp8shl_o <= 8'd150 - {3'd0,s1t_shlx};
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      i2f_exp8sh0_o <= {8{s1t_fract32[23]}} & 8'd150; // "1" is in [23] / zero
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      i2f_fract32_o <= s1t_fract32;
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    end // advance
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  end // posedge clock
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  // ready is special case
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  always @(posedge clk `OR_ASYNC_RST) begin
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    if (rst)
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      i2f_rdy_o <= 1'b0;
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    else if(flush_i)
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      i2f_rdy_o <= 1'b0;
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    else if(adv_i)
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      i2f_rdy_o <= start_i;
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  end // posedge clock
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endmodule // pfpu32_i2f

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