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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_include.v] - Blame information for rev 48

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//   ==================================================================
//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
//   ------------------------------------------------------------------
//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
//   ALL RIGHTS RESERVED
//   ------------------------------------------------------------------
//
//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
//   Permission:
//
//      Lattice Semiconductor grants permission to use this code
//      pursuant to the terms of the Lattice Semiconductor Corporation
//      Open Source License Agreement.
//
//   Disclaimer:
//
//      Lattice Semiconductor provides no warranty regarding the use or
//      functionality of this code. It is the user's responsibility to
//      verify the user's design for consistency and functionality through
//      the use of formal verification methods.
//
//   --------------------------------------------------------------------
//
//                  Lattice Semiconductor Corporation
//                  5555 NE Moore Court
//                  Hillsboro, OR 97214
//                  U.S.A
//
//                  TEL: 1-800-Lattice (USA and Canada)
//                         503-286-8001 (other locations)
//
//                  web: http://www.latticesemi.com/
//                  email: techsupport@latticesemi.com
//
//   --------------------------------------------------------------------
//                         FILE DETAILS
// Project          : LatticeMico32
// File             : lm32_include.v
// Title            : CPU global macros
// Version          : 6.1.17
//                  : Initial Release
// Version          : 7.0SP2, 3.0
//                  : No Change
// Version          : 3.1
//                  : No Change
// Version          : 3.2
//                  : No Change
// Version          : 3.3
//                  : Support for extended configuration register
// =============================================================================
 
`ifdef LM32_INCLUDE_V
`else
`define LM32_INCLUDE_V
 
//
// Common configuration options
//
 
`include "lm32_config.v"
 
//
// End of common configuration options
//
 
`ifdef TRUE
`else
`define TRUE    1'b1
`define FALSE   1'b0
`define TRUE_N  1'b0
`define FALSE_N 1'b1
`endif
 
// Wishbone configuration
`define CFG_IWB_ENABLED
`define CFG_DWB_ENABLED
 
// Data-path width
`define LM32_WORD_WIDTH                 32
`define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
`define LM32_SHIFT_WIDTH                5
`define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
`define LM32_BYTE_SELECT_WIDTH          4
`define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
 
// Register file size
`define LM32_REGISTERS                  32
`define LM32_REG_IDX_WIDTH              5
`define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
 
// Standard register numbers
`define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
`define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
`define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
 
// Range of Program Counter. Two LSBs are always 0.
`define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
`define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
 
// Range of an instruction
`define LM32_INSTRUCTION_WIDTH          32
`define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
 
// Adder operation
`define LM32_ADDER_OP_ADD               1'b0
`define LM32_ADDER_OP_SUBTRACT          1'b1
 
// Shift direction
`define LM32_SHIFT_OP_RIGHT             1'b0
`define LM32_SHIFT_OP_LEFT              1'b1
 
// Bus errors
`define CFG_BUS_ERRORS_ENABLED
 
// Derive macro that indicates whether we have single-stepping or not
`ifdef CFG_ROM_DEBUG_ENABLED
`define LM32_SINGLE_STEP_ENABLED
`else
`ifdef CFG_HW_DEBUG_ENABLED
`define LM32_SINGLE_STEP_ENABLED
`endif
`endif
 
// Derive macro that indicates whether JTAG interface is required
`ifdef CFG_JTAG_UART_ENABLED
`define LM32_JTAG_ENABLED
`else
`ifdef CFG_DEBUG_ENABLED
`define LM32_JTAG_ENABLED
`else
`endif
`endif
 
// Derive macro that indicates whether ROM debug is required
`ifdef CFG_GDBSTUB_ENABLED
`define CFG_ROM_DEBUG_ENABLED
`endif
 
// Derive macro that indicates whether we have a barrel-shifter or not
`ifdef CFG_PL_BARREL_SHIFT_ENABLED
`define LM32_BARREL_SHIFT_ENABLED
`else // CFG_PL_BARREL_SHIFT_ENABLED
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
`define LM32_BARREL_SHIFT_ENABLED
`else
`define LM32_NO_BARREL_SHIFT
`endif
`endif // CFG_PL_BARREL_SHIFT_ENABLED
 
// Derive macro that indicates whether we have a multiplier or not
`ifdef CFG_PL_MULTIPLY_ENABLED
`define LM32_MULTIPLY_ENABLED
`else
`ifdef CFG_MC_MULTIPLY_ENABLED
`define LM32_MULTIPLY_ENABLED
`endif
`endif
 
// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
`ifdef CFG_MC_DIVIDE_ENABLED
`define LM32_MC_ARITHMETIC_ENABLED
`endif
`ifdef CFG_MC_MULTIPLY_ENABLED
`define LM32_MC_ARITHMETIC_ENABLED
`endif
`ifdef CFG_MC_BARREL_SHIFT_ENABLED
`define LM32_MC_ARITHMETIC_ENABLED
`endif
 
// Derive macro that indicates if we are using an EBR register file
`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
`define LM32_EBR_REGISTER_FILE
`endif
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
`define LM32_EBR_REGISTER_FILE
`endif
 
// Revision number
`define LM32_REVISION                   6'h02
 
// Logical operations - Function encoded directly in instruction
`define LM32_LOGIC_OP_RNG               3:0
 
// Conditions for conditional branches
`define LM32_CONDITION_WIDTH            3
`define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
`define LM32_CONDITION_E                3'b001
`define LM32_CONDITION_G                3'b010
`define LM32_CONDITION_GE               3'b011
`define LM32_CONDITION_GEU              3'b100
`define LM32_CONDITION_GU               3'b101
`define LM32_CONDITION_NE               3'b111
`define LM32_CONDITION_U1               3'b000
`define LM32_CONDITION_U2               3'b110
 
// Size of load or store instruction - Encoding corresponds to opcode
`define LM32_SIZE_WIDTH                 2
`define LM32_SIZE_RNG                   1:0
`define LM32_SIZE_BYTE                  2'b00
`define LM32_SIZE_HWORD                 2'b11
`define LM32_SIZE_WORD                  2'b10
`define LM32_ADDRESS_LSBS_WIDTH         2
 
// Width and range of a CSR index
`ifdef CFG_MMU_ENABLED
`define LM32_CSR_WIDTH                  5
`else
`ifdef CFG_DEBUG_ENABLED
`define LM32_CSR_WIDTH                  5
`else
`ifdef CFG_JTAG_ENABLED
`define LM32_CSR_WIDTH                  4
`else
`define LM32_CSR_WIDTH                  3
`endif
`endif
`endif
`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
 
// CSR indices
`define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
`define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
`define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
`define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
`define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
`define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
`define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
`define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
`ifdef CFG_DEBUG_ENABLED
`define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
`define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
`endif
`define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
`ifdef CFG_JTAG_ENABLED
`define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
`define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
`endif
`ifdef CFG_DEBUG_ENABLED
`define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
`define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
`define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
`define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
`define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
`define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
`define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
`define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
`endif
`ifdef CFG_MMU_ENABLED
`define LM32_CSR_PSW                    `LM32_CSR_WIDTH'h1d
`define LM32_CSR_TLBVADDR               `LM32_CSR_WIDTH'h1e
`define LM32_CSR_TLBPADDR               `LM32_CSR_WIDTH'h1f  // write only
`define LM32_CSR_TLBBADVADDR            `LM32_CSR_WIDTH'h1f  // read only
`endif
 
// Values for WPC CSR
`define LM32_WPC_C_RNG                  1:0
`define LM32_WPC_C_DISABLED             2'b00
`define LM32_WPC_C_READ                 2'b01
`define LM32_WPC_C_WRITE                2'b10
`define LM32_WPC_C_READ_WRITE           2'b11
 
// TLB operation codes
`define LM32_TLB_OP_RNG                 2:1
`define LM32_TLB_OP_NOOP                2'h0
`define LM32_TLB_OP_FLUSH               2'h1
`define LM32_TLB_OP_INVALIDATE          2'h2
 
// Exception IDs
`define LM32_EID_WIDTH                  4
`define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
`define LM32_EID_RESET                  `LM32_EID_WIDTH'h0
`define LM32_EID_BREAKPOINT             `LM32_EID_WIDTH'h1
`define LM32_EID_INST_BUS_ERROR         `LM32_EID_WIDTH'h2
`define LM32_EID_WATCHPOINT             `LM32_EID_WIDTH'h3
`define LM32_EID_DATA_BUS_ERROR         `LM32_EID_WIDTH'h4
`define LM32_EID_DIVIDE_BY_ZERO         `LM32_EID_WIDTH'h5
`define LM32_EID_INTERRUPT              `LM32_EID_WIDTH'h6
`define LM32_EID_SCALL                  `LM32_EID_WIDTH'h7
`define LM32_EID_ITLB_MISS              `LM32_EID_WIDTH'h8
`define LM32_EID_DTLB_MISS              `LM32_EID_WIDTH'h9
`define LM32_EID_DTLB_FAULT             `LM32_EID_WIDTH'ha
`define LM32_EID_PRIVILEGE              `LM32_EID_WIDTH'hb
 
// Exception Base Address
`define LM32_EBA_WIDTH                  (`LM32_PC_WIDTH-`LM32_EID_WIDTH-3)
`define LM32_EBA_RNG                    (`LM32_PC_WIDTH+2-1):(`LM32_EID_WIDTH+3+2)
 
// Pipeline result selection mux controls
 
`define LM32_D_RESULT_SEL_0_RNG          0:0
`define LM32_D_RESULT_SEL_0_REG_0        1'b0
`define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
 
`define LM32_D_RESULT_SEL_1_RNG          1:0
`define LM32_D_RESULT_SEL_1_ZERO         2'b00
`define LM32_D_RESULT_SEL_1_REG_1        2'b01
`define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
 
`define LM32_USER_OPCODE_WIDTH           11
`define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
 
// Derive a macro to indicate if either of the caches are implemented
`ifdef CFG_ICACHE_ENABLED
`define LM32_CACHE_ENABLED
`else
`ifdef CFG_DCACHE_ENABLED
`define LM32_CACHE_ENABLED
`endif
`endif
 
/////////////////////////////////////////////////////
// Interrupts
/////////////////////////////////////////////////////
 
// Always enable interrupts
`define CFG_INTERRUPTS_ENABLED
 
// Currently this is fixed to 32 and should not be changed
`define CFG_INTERRUPTS                  32
`define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
`define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
 
/////////////////////////////////////////////////////
// General
/////////////////////////////////////////////////////
 
// Sub-word range types
`define LM32_BYTE_WIDTH                 8
`define LM32_BYTE_RNG                   7:0
`define LM32_HWORD_WIDTH                16
`define LM32_HWORD_RNG                  15:0
 
// Word sub-byte indicies
`define LM32_BYTE_0_RNG                  7:0
`define LM32_BYTE_1_RNG                  15:8
`define LM32_BYTE_2_RNG                  23:16
`define LM32_BYTE_3_RNG                  31:24
 
// Word sub-halfword indices
`define LM32_HWORD_0_RNG                 15:0
`define LM32_HWORD_1_RNG                 31:16
 
// Use a synchronous reset
`define CFG_RESET_SENSITIVITY
 
// Wishbone defines
// Refer to Wishbone System-on-Chip Interconnection Architecture
// These should probably be moved to a Wishbone common file
 
// Wishbone cycle types
`define LM32_CTYPE_WIDTH                3
`define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
`define LM32_CTYPE_CLASSIC              3'b000
`define LM32_CTYPE_CONSTANT             3'b001
`define LM32_CTYPE_INCREMENTING         3'b010
`define LM32_CTYPE_END                  3'b111
 
// Wishbone burst types
`define LM32_BTYPE_WIDTH                2
`define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
`define LM32_BTYPE_LINEAR               2'b00
`define LM32_BTYPE_4_BEAT               2'b01
`define LM32_BTYPE_8_BEAT               2'b10
`define LM32_BTYPE_16_BEAT              2'b11
 
`endif

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_include.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`// ==================================================================`
2			`// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<`
3			`// ------------------------------------------------------------------`
4			`// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation`
5			`// ALL RIGHTS RESERVED`
6			`// ------------------------------------------------------------------`
7			`//`
8			`// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.`
9			`//`
10			`// Permission:`
11			`//`
12			`// Lattice Semiconductor grants permission to use this code`
13			`// pursuant to the terms of the Lattice Semiconductor Corporation`
14			`// Open Source License Agreement.`
15			`//`
16			`// Disclaimer:`
17			`//`
18			`// Lattice Semiconductor provides no warranty regarding the use or`
19			`// functionality of this code. It is the user's responsibility to`
20			`// verify the user's design for consistency and functionality through`
21			`// the use of formal verification methods.`
22			`//`
23			`// --------------------------------------------------------------------`
24			`//`
25			`// Lattice Semiconductor Corporation`
26			`// 5555 NE Moore Court`
27			`// Hillsboro, OR 97214`
28			`// U.S.A`
29			`//`
30			`// TEL: 1-800-Lattice (USA and Canada)`
31			`// 503-286-8001 (other locations)`
32			`//`
33			`// web: http://www.latticesemi.com/`
34			`// email: techsupport@latticesemi.com`
35			`//`
36			`// --------------------------------------------------------------------`
37			`// FILE DETAILS`
38			`// Project : LatticeMico32`
39			`// File : lm32_include.v`
40			`// Title : CPU global macros`
41			`// Version : 6.1.17`
42			`// : Initial Release`
43			`// Version : 7.0SP2, 3.0`
44			`// : No Change`
45			`// Version : 3.1`
46			`// : No Change`
47			`// Version : 3.2`
48			`// : No Change`
49			`// Version : 3.3`
50			`// : Support for extended configuration register`
51			`// =============================================================================`
52
53			`ifdef LM32_INCLUDE_V
54			`else
55			`define LM32_INCLUDE_V
56
57			`//`
58			`// Common configuration options`
59			`//`
60
61			`include "lm32_config.v"
62
63			`//`
64			`// End of common configuration options`
65			`//`
66
67			`ifdef TRUE
68			`else
69			`define TRUE 1'b1
70			`define FALSE 1'b0
71			`define TRUE_N 1'b0
72			`define FALSE_N 1'b1
73			`endif
74
75			`// Wishbone configuration`
76			`define CFG_IWB_ENABLED
77			`define CFG_DWB_ENABLED
78
79			`// Data-path width`
80			`define LM32_WORD_WIDTH 32
81			`define LM32_WORD_RNG (`LM32_WORD_WIDTH-1):0
82			`define LM32_SHIFT_WIDTH 5
83			`define LM32_SHIFT_RNG (`LM32_SHIFT_WIDTH-1):0
84			`define LM32_BYTE_SELECT_WIDTH 4
85			`define LM32_BYTE_SELECT_RNG (`LM32_BYTE_SELECT_WIDTH-1):0
86
87			`// Register file size`
88			`define LM32_REGISTERS 32
89			`define LM32_REG_IDX_WIDTH 5
90			`define LM32_REG_IDX_RNG (`LM32_REG_IDX_WIDTH-1):0
91
92			`// Standard register numbers`
93			`define LM32_RA_REG `LM32_REG_IDX_WIDTH'd29
94			`define LM32_EA_REG `LM32_REG_IDX_WIDTH'd30
95			`define LM32_BA_REG `LM32_REG_IDX_WIDTH'd31
96
97			`// Range of Program Counter. Two LSBs are always 0.`
98			`define LM32_PC_WIDTH (`LM32_WORD_WIDTH-2)
99			`define LM32_PC_RNG (`LM32_PC_WIDTH+2-1):2
100
101			`// Range of an instruction`
102			`define LM32_INSTRUCTION_WIDTH 32
103			`define LM32_INSTRUCTION_RNG (`LM32_INSTRUCTION_WIDTH-1):0
104
105			`// Adder operation`
106			`define LM32_ADDER_OP_ADD 1'b0
107			`define LM32_ADDER_OP_SUBTRACT 1'b1
108
109			`// Shift direction`
110			`define LM32_SHIFT_OP_RIGHT 1'b0
111			`define LM32_SHIFT_OP_LEFT 1'b1
112
113			`// Bus errors`
114			`define CFG_BUS_ERRORS_ENABLED
115
116			`// Derive macro that indicates whether we have single-stepping or not`
117			`ifdef CFG_ROM_DEBUG_ENABLED
118			`define LM32_SINGLE_STEP_ENABLED
119			`else
120			`ifdef CFG_HW_DEBUG_ENABLED
121			`define LM32_SINGLE_STEP_ENABLED
122			`endif
123			`endif
124
125			`// Derive macro that indicates whether JTAG interface is required`
126			`ifdef CFG_JTAG_UART_ENABLED
127			`define LM32_JTAG_ENABLED
128			`else
129			`ifdef CFG_DEBUG_ENABLED
130			`define LM32_JTAG_ENABLED
131			`else
132			`endif
133			`endif
134
135			`// Derive macro that indicates whether ROM debug is required`
136			`ifdef CFG_GDBSTUB_ENABLED
137			`define CFG_ROM_DEBUG_ENABLED
138			`endif
139
140			`// Derive macro that indicates whether we have a barrel-shifter or not`
141			`ifdef CFG_PL_BARREL_SHIFT_ENABLED
142			`define LM32_BARREL_SHIFT_ENABLED
143			`else // CFG_PL_BARREL_SHIFT_ENABLED
144			`ifdef CFG_MC_BARREL_SHIFT_ENABLED
145			`define LM32_BARREL_SHIFT_ENABLED
146			`else
147			`define LM32_NO_BARREL_SHIFT
148			`endif
149			`endif // CFG_PL_BARREL_SHIFT_ENABLED
150
151			`// Derive macro that indicates whether we have a multiplier or not`
152			`ifdef CFG_PL_MULTIPLY_ENABLED
153			`define LM32_MULTIPLY_ENABLED
154			`else
155			`ifdef CFG_MC_MULTIPLY_ENABLED
156			`define LM32_MULTIPLY_ENABLED
157			`endif
158			`endif
159
160			`// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required`
161			`ifdef CFG_MC_DIVIDE_ENABLED
162			`define LM32_MC_ARITHMETIC_ENABLED
163			`endif
164			`ifdef CFG_MC_MULTIPLY_ENABLED
165			`define LM32_MC_ARITHMETIC_ENABLED
166			`endif
167			`ifdef CFG_MC_BARREL_SHIFT_ENABLED
168			`define LM32_MC_ARITHMETIC_ENABLED
169			`endif
170
171			`// Derive macro that indicates if we are using an EBR register file`
172			`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
173			`define LM32_EBR_REGISTER_FILE
174			`endif
175			`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
176			`define LM32_EBR_REGISTER_FILE
177			`endif
178
179			`// Revision number`
180			`define LM32_REVISION 6'h02
181
182			`// Logical operations - Function encoded directly in instruction`
183			`define LM32_LOGIC_OP_RNG 3:0
184
185			`// Conditions for conditional branches`
186			`define LM32_CONDITION_WIDTH 3
187			`define LM32_CONDITION_RNG (`LM32_CONDITION_WIDTH-1):0
188			`define LM32_CONDITION_E 3'b001
189			`define LM32_CONDITION_G 3'b010
190			`define LM32_CONDITION_GE 3'b011
191			`define LM32_CONDITION_GEU 3'b100
192			`define LM32_CONDITION_GU 3'b101
193			`define LM32_CONDITION_NE 3'b111
194			`define LM32_CONDITION_U1 3'b000
195			`define LM32_CONDITION_U2 3'b110
196
197			`// Size of load or store instruction - Encoding corresponds to opcode`
198			`define LM32_SIZE_WIDTH 2
199			`define LM32_SIZE_RNG 1:0
200			`define LM32_SIZE_BYTE 2'b00
201			`define LM32_SIZE_HWORD 2'b11
202			`define LM32_SIZE_WORD 2'b10
203			`define LM32_ADDRESS_LSBS_WIDTH 2
204
205			`// Width and range of a CSR index`
206			`ifdef CFG_MMU_ENABLED
207			`define LM32_CSR_WIDTH 5
208			`else
209			`ifdef CFG_DEBUG_ENABLED
210			`define LM32_CSR_WIDTH 5
211			`else
212			`ifdef CFG_JTAG_ENABLED
213			`define LM32_CSR_WIDTH 4
214			`else
215			`define LM32_CSR_WIDTH 3
216			`endif
217			`endif
218			`endif
219			`define LM32_CSR_RNG (`LM32_CSR_WIDTH-1):0
220
221			`// CSR indices`
222			`define LM32_CSR_IE `LM32_CSR_WIDTH'h0
223			`define LM32_CSR_IM `LM32_CSR_WIDTH'h1
224			`define LM32_CSR_IP `LM32_CSR_WIDTH'h2
225			`define LM32_CSR_ICC `LM32_CSR_WIDTH'h3
226			`define LM32_CSR_DCC `LM32_CSR_WIDTH'h4
227			`define LM32_CSR_CC `LM32_CSR_WIDTH'h5
228			`define LM32_CSR_CFG `LM32_CSR_WIDTH'h6
229			`define LM32_CSR_EBA `LM32_CSR_WIDTH'h7
230			`ifdef CFG_DEBUG_ENABLED
231			`define LM32_CSR_DC `LM32_CSR_WIDTH'h8
232			`define LM32_CSR_DEBA `LM32_CSR_WIDTH'h9
233			`endif
234			`define LM32_CSR_CFG2 `LM32_CSR_WIDTH'ha
235			`ifdef CFG_JTAG_ENABLED
236			`define LM32_CSR_JTX `LM32_CSR_WIDTH'he
237			`define LM32_CSR_JRX `LM32_CSR_WIDTH'hf
238			`endif
239			`ifdef CFG_DEBUG_ENABLED
240			`define LM32_CSR_BP0 `LM32_CSR_WIDTH'h10
241			`define LM32_CSR_BP1 `LM32_CSR_WIDTH'h11
242			`define LM32_CSR_BP2 `LM32_CSR_WIDTH'h12
243			`define LM32_CSR_BP3 `LM32_CSR_WIDTH'h13
244			`define LM32_CSR_WP0 `LM32_CSR_WIDTH'h18
245			`define LM32_CSR_WP1 `LM32_CSR_WIDTH'h19
246			`define LM32_CSR_WP2 `LM32_CSR_WIDTH'h1a
247			`define LM32_CSR_WP3 `LM32_CSR_WIDTH'h1b
248			`endif
249			`ifdef CFG_MMU_ENABLED
250			`define LM32_CSR_PSW `LM32_CSR_WIDTH'h1d
251			`define LM32_CSR_TLBVADDR `LM32_CSR_WIDTH'h1e
252			`define LM32_CSR_TLBPADDR `LM32_CSR_WIDTH'h1f // write only
253			`define LM32_CSR_TLBBADVADDR `LM32_CSR_WIDTH'h1f // read only
254			`endif
255
256			`// Values for WPC CSR`
257			`define LM32_WPC_C_RNG 1:0
258			`define LM32_WPC_C_DISABLED 2'b00
259			`define LM32_WPC_C_READ 2'b01
260			`define LM32_WPC_C_WRITE 2'b10
261			`define LM32_WPC_C_READ_WRITE 2'b11
262
263			`// TLB operation codes`
264			`define LM32_TLB_OP_RNG 2:1
265			`define LM32_TLB_OP_NOOP 2'h0
266			`define LM32_TLB_OP_FLUSH 2'h1
267			`define LM32_TLB_OP_INVALIDATE 2'h2
268
269			`// Exception IDs`
270			`define LM32_EID_WIDTH 4
271			`define LM32_EID_RNG (`LM32_EID_WIDTH-1):0
272			`define LM32_EID_RESET `LM32_EID_WIDTH'h0
273			`define LM32_EID_BREAKPOINT `LM32_EID_WIDTH'h1
274			`define LM32_EID_INST_BUS_ERROR `LM32_EID_WIDTH'h2
275			`define LM32_EID_WATCHPOINT `LM32_EID_WIDTH'h3
276			`define LM32_EID_DATA_BUS_ERROR `LM32_EID_WIDTH'h4
277			`define LM32_EID_DIVIDE_BY_ZERO `LM32_EID_WIDTH'h5
278			`define LM32_EID_INTERRUPT `LM32_EID_WIDTH'h6
279			`define LM32_EID_SCALL `LM32_EID_WIDTH'h7
280			`define LM32_EID_ITLB_MISS `LM32_EID_WIDTH'h8
281			`define LM32_EID_DTLB_MISS `LM32_EID_WIDTH'h9
282			`define LM32_EID_DTLB_FAULT `LM32_EID_WIDTH'ha
283			`define LM32_EID_PRIVILEGE `LM32_EID_WIDTH'hb
284
285			`// Exception Base Address`
286			`define LM32_EBA_WIDTH (`LM32_PC_WIDTH-`LM32_EID_WIDTH-3)
287			`define LM32_EBA_RNG (`LM32_PC_WIDTH+2-1):(`LM32_EID_WIDTH+3+2)
288
289			`// Pipeline result selection mux controls`
290
291			`define LM32_D_RESULT_SEL_0_RNG 0:0
292			`define LM32_D_RESULT_SEL_0_REG_0 1'b0
293			`define LM32_D_RESULT_SEL_0_NEXT_PC 1'b1
294
295			`define LM32_D_RESULT_SEL_1_RNG 1:0
296			`define LM32_D_RESULT_SEL_1_ZERO 2'b00
297			`define LM32_D_RESULT_SEL_1_REG_1 2'b01
298			`define LM32_D_RESULT_SEL_1_IMMEDIATE 2'b10
299
300			`define LM32_USER_OPCODE_WIDTH 11
301			`define LM32_USER_OPCODE_RNG (`LM32_USER_OPCODE_WIDTH-1):0
302
303			`// Derive a macro to indicate if either of the caches are implemented`
304			`ifdef CFG_ICACHE_ENABLED
305			`define LM32_CACHE_ENABLED
306			`else
307			`ifdef CFG_DCACHE_ENABLED
308			`define LM32_CACHE_ENABLED
309			`endif
310			`endif
311
312			`/////////////////////////////////////////////////////`
313			`// Interrupts`
314			`/////////////////////////////////////////////////////`
315
316			`// Always enable interrupts`
317			`define CFG_INTERRUPTS_ENABLED
318
319			`// Currently this is fixed to 32 and should not be changed`
320			`define CFG_INTERRUPTS 32
321			`define LM32_INTERRUPT_WIDTH `CFG_INTERRUPTS
322			`define LM32_INTERRUPT_RNG (`LM32_INTERRUPT_WIDTH-1):0
323
324			`/////////////////////////////////////////////////////`
325			`// General`
326			`/////////////////////////////////////////////////////`
327
328			`// Sub-word range types`
329			`define LM32_BYTE_WIDTH 8
330			`define LM32_BYTE_RNG 7:0
331			`define LM32_HWORD_WIDTH 16
332			`define LM32_HWORD_RNG 15:0
333
334			`// Word sub-byte indicies`
335			`define LM32_BYTE_0_RNG 7:0
336			`define LM32_BYTE_1_RNG 15:8
337			`define LM32_BYTE_2_RNG 23:16
338			`define LM32_BYTE_3_RNG 31:24
339
340			`// Word sub-halfword indices`
341			`define LM32_HWORD_0_RNG 15:0
342			`define LM32_HWORD_1_RNG 31:16
343
344			`// Use a synchronous reset`
345			`define CFG_RESET_SENSITIVITY
346
347			`// Wishbone defines`
348			`// Refer to Wishbone System-on-Chip Interconnection Architecture`
349			`// These should probably be moved to a Wishbone common file`
350
351			`// Wishbone cycle types`
352			`define LM32_CTYPE_WIDTH 3
353			`define LM32_CTYPE_RNG (`LM32_CTYPE_WIDTH-1):0
354			`define LM32_CTYPE_CLASSIC 3'b000
355			`define LM32_CTYPE_CONSTANT 3'b001
356			`define LM32_CTYPE_INCREMENTING 3'b010
357			`define LM32_CTYPE_END 3'b111
358
359			`// Wishbone burst types`
360			`define LM32_BTYPE_WIDTH 2
361			`define LM32_BTYPE_RNG (`LM32_BTYPE_WIDTH-1):0
362			`define LM32_BTYPE_LINEAR 2'b00
363			`define LM32_BTYPE_4_BEAT 2'b01
364			`define LM32_BTYPE_8_BEAT 2'b10
365			`define LM32_BTYPE_16_BEAT 2'b11
366
367			`endif