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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_interrupt.v] - Blame information for rev 48

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//   ==================================================================
//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
//   ------------------------------------------------------------------
//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
//   ALL RIGHTS RESERVED
//   ------------------------------------------------------------------
//
//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
//   Permission:
//
//      Lattice Semiconductor grants permission to use this code
//      pursuant to the terms of the Lattice Semiconductor Corporation
//      Open Source License Agreement.
//
//   Disclaimer:
//
//      Lattice Semiconductor provides no warranty regarding the use or
//      functionality of this code. It is the user's responsibility to
//      verify the user's design for consistency and functionality through
//      the use of formal verification methods.
//
//   --------------------------------------------------------------------
//
//                  Lattice Semiconductor Corporation
//                  5555 NE Moore Court
//                  Hillsboro, OR 97214
//                  U.S.A
//
//                  TEL: 1-800-Lattice (USA and Canada)
//                         503-286-8001 (other locations)
//
//                  web: http://www.latticesemi.com/
//                  email: techsupport@latticesemi.com
//
//   --------------------------------------------------------------------
//                         FILE DETAILS
// Project          : LatticeMico32
// File             : lm32_interrupt.v
// Title            : Interrupt logic
// Dependencies     : lm32_include.v
// Version          : 6.1.17
//                  : Initial Release
// Version          : 7.0SP2, 3.0
//                  : No Change
// Version          : 3.1
//                  : No Change
// =============================================================================
 
`include "lm32_include.v"
 
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
 
module lm32_interrupt (
    // ----- Inputs -------
    clk_i,
    rst_i,
    // From external devices
    interrupt,
    // From pipeline
    stall_x,
`ifdef CFG_DEBUG_ENABLED
    non_debug_exception,
    debug_exception,
`else
    exception,
`endif
    eret_q_x,
`ifdef CFG_DEBUG_ENABLED
    bret_q_x,
`endif
    csr,
    csr_write_data,
    csr_write_enable,
    // ----- Outputs -------
    interrupt_exception,
    // To pipeline
    csr_read_data
    );
 
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
 
parameter interrupts = `CFG_INTERRUPTS;         // Number of interrupts
 
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
 
input clk_i;                                    // Clock
input rst_i;                                    // Reset
 
input [interrupts-1:0] interrupt;               // Interrupt pins
 
input stall_x;                                  // Stall X pipeline stage
 
`ifdef CFG_DEBUG_ENABLED
input non_debug_exception;                      // Non-debug related exception has been raised
input debug_exception;                          // Debug-related exception has been raised
`else
input exception;                                // Exception has been raised
`endif
input eret_q_x;                                 // Return from exception
`ifdef CFG_DEBUG_ENABLED
input bret_q_x;                                 // Return from breakpoint
`endif
 
input [`LM32_CSR_RNG] csr;                      // CSR read/write index
input [`LM32_WORD_RNG] csr_write_data;          // Data to write to specified CSR
input csr_write_enable;                         // CSR write enable
 
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
 
output interrupt_exception;                     // Request to raide an interrupt exception
wire   interrupt_exception;
 
output [`LM32_WORD_RNG] csr_read_data;          // Data read from CSR
reg    [`LM32_WORD_RNG] csr_read_data;
 
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
 
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
wire [interrupts-1:0] asserted;                 // Which interrupts are currently being asserted
//pragma attribute asserted preserve_signal true
`endif
wire [interrupts-1:0] interrupt_n_exception;
 
// Interrupt CSRs
 
reg ie;                                         // Interrupt enable
reg eie;                                        // Exception interrupt enable
`ifdef CFG_DEBUG_ENABLED
reg bie;                                        // Breakpoint interrupt enable
`endif
`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
wire [interrupts-1:0] ip;                       // Interrupt pending
`else
reg [interrupts-1:0] ip;                        // Interrupt pending
`endif
reg [interrupts-1:0] im;                        // Interrupt mask
 
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
 
// Determine which interrupts have occured and are unmasked
assign interrupt_n_exception = ip & im;
 
// Determine if any unmasked interrupts have occured
assign interrupt_exception = (|interrupt_n_exception) & ie;
 
// Determine which interrupts are currently being asserted or are already pending
`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
assign ip = interrupt;
`else
assign asserted = ip | interrupt;
`endif
 
assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
                           bie,
`else
                           1'b0,
`endif
                           eie,
                           ie
                          };
assign ip_csr_read_data = ip;
assign im_csr_read_data = im;
generate
    if (interrupts > 1)
    begin
// CSR read
always @(*)
begin
    case (csr)
`ifdef CFG_MMU_ENABLED
    `LM32_CSR_PSW,
`endif
    `LM32_CSR_IE:  csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
                                    bie,
`else
                                    1'b0,
`endif
                                    eie,
                                    ie
                                   };
    `LM32_CSR_IP:  csr_read_data = ip;
    `LM32_CSR_IM:  csr_read_data = im;
    default:       csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
    endcase
end
    end
    else
    begin
// CSR read
always @(*)
begin
    case (csr)
    `LM32_CSR_IE:  csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
`ifdef CFG_DEBUG_ENABLED
                                    bie,
`else
                                    1'b0,
`endif
                                    eie,
                                    ie
                                   };
    `LM32_CSR_IP:  csr_read_data = ip;
    default:       csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
    endcase
end
    end
endgenerate
 
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
 
generate
    if (interrupts > 1)
    begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        ie <= `FALSE;
        eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
        bie <= `FALSE;
`endif
        im <= {interrupts{1'b0}};
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
        ip <= {interrupts{1'b0}};
`endif
    end
    else
    begin
        // Set IP bit when interrupt line is asserted
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
        ip <= asserted;
`endif
`ifdef CFG_DEBUG_ENABLED
        if (non_debug_exception == `TRUE)
        begin
            // Save and then clear interrupt enable
            eie <= ie;
            ie <= `FALSE;
        end
        else if (debug_exception == `TRUE)
        begin
            // Save and then clear interrupt enable
            bie <= ie;
            ie <= `FALSE;
        end
`else
        if (exception == `TRUE)
        begin
            // Save and then clear interrupt enable
            eie <= ie;
            ie <= `FALSE;
        end
`endif
        else if (stall_x == `FALSE)
        begin
            if (eret_q_x == `TRUE)
                // Restore interrupt enable
                ie <= eie;
`ifdef CFG_DEBUG_ENABLED
            else if (bret_q_x == `TRUE)
                // Restore interrupt enable
                ie <= bie;
`endif
            else if (csr_write_enable == `TRUE)
            begin
                // Handle wcsr write
                if (   (csr == `LM32_CSR_IE)
`ifdef CFG_MMU_ENABLED
                    || (csr == `LM32_CSR_PSW)
`endif
                   )
                begin
                    ie <= csr_write_data[0];
                    eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
                    bie <= csr_write_data[2];
`endif
                end
                if (csr == `LM32_CSR_IM)
                    im <= csr_write_data[interrupts-1:0];
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
                if (csr == `LM32_CSR_IP)
                    ip <= asserted & ~csr_write_data[interrupts-1:0];
`endif
            end
        end
    end
end
    end
else
    begin
// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        ie <= `FALSE;
        eie <= `FALSE;
`ifdef CFG_DEBUG_ENABLED
        bie <= `FALSE;
`endif
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
        ip <= {interrupts{1'b0}};
`endif
    end
    else
    begin
        // Set IP bit when interrupt line is asserted
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
        ip <= asserted;
`endif
`ifdef CFG_DEBUG_ENABLED
        if (non_debug_exception == `TRUE)
        begin
            // Save and then clear interrupt enable
            eie <= ie;
            ie <= `FALSE;
        end
        else if (debug_exception == `TRUE)
        begin
            // Save and then clear interrupt enable
            bie <= ie;
            ie <= `FALSE;
        end
`else
        if (exception == `TRUE)
        begin
            // Save and then clear interrupt enable
            eie <= ie;
            ie <= `FALSE;
        end
`endif
        else if (stall_x == `FALSE)
        begin
            if (eret_q_x == `TRUE)
                // Restore interrupt enable
                ie <= eie;
`ifdef CFG_DEBUG_ENABLED
            else if (bret_q_x == `TRUE)
                // Restore interrupt enable
                ie <= bie;
`endif
            else if (csr_write_enable == `TRUE)
            begin
                // Handle wcsr write
                if (   (csr == `LM32_CSR_IE)
`ifdef CFG_MMU_ENABLED
                    || (csr == `LM32_CSR_PSW)
`endif
                   )
                begin
                    ie <= csr_write_data[0];
                    eie <= csr_write_data[1];
`ifdef CFG_DEBUG_ENABLED
                    bie <= csr_write_data[2];
`endif
                end
`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
                if (csr == `LM32_CSR_IP)
                    ip <= asserted & ~csr_write_data[interrupts-1:0];
`endif
            end
        end
    end
end
    end
endgenerate
 
endmodule
 

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_interrupt.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`// ==================================================================`
2			`// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<`
3			`// ------------------------------------------------------------------`
4			`// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation`
5			`// ALL RIGHTS RESERVED`
6			`// ------------------------------------------------------------------`
7			`//`
8			`// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.`
9			`//`
10			`// Permission:`
11			`//`
12			`// Lattice Semiconductor grants permission to use this code`
13			`// pursuant to the terms of the Lattice Semiconductor Corporation`
14			`// Open Source License Agreement.`
15			`//`
16			`// Disclaimer:`
17			`//`
18			`// Lattice Semiconductor provides no warranty regarding the use or`
19			`// functionality of this code. It is the user's responsibility to`
20			`// verify the user's design for consistency and functionality through`
21			`// the use of formal verification methods.`
22			`//`
23			`// --------------------------------------------------------------------`
24			`//`
25			`// Lattice Semiconductor Corporation`
26			`// 5555 NE Moore Court`
27			`// Hillsboro, OR 97214`
28			`// U.S.A`
29			`//`
30			`// TEL: 1-800-Lattice (USA and Canada)`
31			`// 503-286-8001 (other locations)`
32			`//`
33			`// web: http://www.latticesemi.com/`
34			`// email: techsupport@latticesemi.com`
35			`//`
36			`// --------------------------------------------------------------------`
37			`// FILE DETAILS`
38			`// Project : LatticeMico32`
39			`// File : lm32_interrupt.v`
40			`// Title : Interrupt logic`
41			`// Dependencies : lm32_include.v`
42			`// Version : 6.1.17`
43			`// : Initial Release`
44			`// Version : 7.0SP2, 3.0`
45			`// : No Change`
46			`// Version : 3.1`
47			`// : No Change`
48			`// =============================================================================`
49
50			`include "lm32_include.v"
51
52			`/////////////////////////////////////////////////////`
53			`// Module interface`
54			`/////////////////////////////////////////////////////`
55
56			`module lm32_interrupt (`
57			`// ----- Inputs -------`
58			`clk_i,`
59			`rst_i,`
60			`// From external devices`
61			`interrupt,`
62			`// From pipeline`
63			`stall_x,`
64			`ifdef CFG_DEBUG_ENABLED
65			`non_debug_exception,`
66			`debug_exception,`
67			`else
68			`exception,`
69			`endif
70			`eret_q_x,`
71			`ifdef CFG_DEBUG_ENABLED
72			`bret_q_x,`
73			`endif
74			`csr,`
75			`csr_write_data,`
76			`csr_write_enable,`
77			`// ----- Outputs -------`
78			`interrupt_exception,`
79			`// To pipeline`
80			`csr_read_data`
81			`);`
82
83			`/////////////////////////////////////////////////////`
84			`// Parameters`
85			`/////////////////////////////////////////////////////`
86
87			parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
88
89			`/////////////////////////////////////////////////////`
90			`// Inputs`
91			`/////////////////////////////////////////////////////`
92
93			`input clk_i; // Clock`
94			`input rst_i; // Reset`
95
96			`input [interrupts-1:0] interrupt; // Interrupt pins`
97
98			`input stall_x; // Stall X pipeline stage`
99
100			`ifdef CFG_DEBUG_ENABLED
101			`input non_debug_exception; // Non-debug related exception has been raised`
102			`input debug_exception; // Debug-related exception has been raised`
103			`else
104			`input exception; // Exception has been raised`
105			`endif
106			`input eret_q_x; // Return from exception`
107			`ifdef CFG_DEBUG_ENABLED
108			`input bret_q_x; // Return from breakpoint`
109			`endif
110
111			input [`LM32_CSR_RNG] csr; // CSR read/write index
112			input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
113			`input csr_write_enable; // CSR write enable`
114
115			`/////////////////////////////////////////////////////`
116			`// Outputs`
117			`/////////////////////////////////////////////////////`
118
119			`output interrupt_exception; // Request to raide an interrupt exception`
120			`wire interrupt_exception;`
121
122			output [`LM32_WORD_RNG] csr_read_data; // Data read from CSR
123			reg [`LM32_WORD_RNG] csr_read_data;
124
125			`/////////////////////////////////////////////////////`
126			`// Internal nets and registers`
127			`/////////////////////////////////////////////////////`
128
129			`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
130			`wire [interrupts-1:0] asserted; // Which interrupts are currently being asserted`
131			`//pragma attribute asserted preserve_signal true`
132			`endif
133			`wire [interrupts-1:0] interrupt_n_exception;`
134
135			`// Interrupt CSRs`
136
137			`reg ie; // Interrupt enable`
138			`reg eie; // Exception interrupt enable`
139			`ifdef CFG_DEBUG_ENABLED
140			`reg bie; // Breakpoint interrupt enable`
141			`endif
142			`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
143			`wire [interrupts-1:0] ip; // Interrupt pending`
144			`else
145			`reg [interrupts-1:0] ip; // Interrupt pending`
146			`endif
147			`reg [interrupts-1:0] im; // Interrupt mask`
148
149			`/////////////////////////////////////////////////////`
150			`// Combinational Logic`
151			`/////////////////////////////////////////////////////`
152
153			`// Determine which interrupts have occured and are unmasked`
154			`assign interrupt_n_exception = ip & im;`
155
156			`// Determine if any unmasked interrupts have occured`
157			`assign interrupt_exception = (\|interrupt_n_exception) & ie;`
158
159			`// Determine which interrupts are currently being asserted or are already pending`
160			`ifdef CFG_LEVEL_SENSITIVE_INTERRUPTS
161			`assign ip = interrupt;`
162			`else
163			`assign asserted = ip \| interrupt;`
164			`endif
165
166			assign ie_csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
167			`ifdef CFG_DEBUG_ENABLED
168			`bie,`
169			`else
170			`1'b0,`
171			`endif
172			`eie,`
173			`ie`
174			`};`
175			`assign ip_csr_read_data = ip;`
176			`assign im_csr_read_data = im;`
177			`generate`
178			`if (interrupts > 1)`
179			`begin`
180			`// CSR read`
181			`always @(*)`
182			`begin`
183			`case (csr)`
184			`ifdef CFG_MMU_ENABLED
185			`LM32_CSR_PSW,
186			`endif
187			`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
188			`ifdef CFG_DEBUG_ENABLED
189			`bie,`
190			`else
191			`1'b0,`
192			`endif
193			`eie,`
194			`ie`
195			`};`
196			`LM32_CSR_IP: csr_read_data = ip;
197			`LM32_CSR_IM: csr_read_data = im;
198			default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
199			`endcase`
200			`end`
201			`end`
202			`else`
203			`begin`
204			`// CSR read`
205			`always @(*)`
206			`begin`
207			`case (csr)`
208			`LM32_CSR_IE: csr_read_data = {{`LM32_WORD_WIDTH-3{1'b0}},
209			`ifdef CFG_DEBUG_ENABLED
210			`bie,`
211			`else
212			`1'b0,`
213			`endif
214			`eie,`
215			`ie`
216			`};`
217			`LM32_CSR_IP: csr_read_data = ip;
218			default: csr_read_data = {`LM32_WORD_WIDTH{1'bx}};
219			`endcase`
220			`end`
221			`end`
222			`endgenerate`
223
224			`/////////////////////////////////////////////////////`
225			`// Sequential Logic`
226			`/////////////////////////////////////////////////////`
227
228			`generate`
229			`if (interrupts > 1)`
230			`begin`
231			`// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs`
232			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
233			`begin`
234			if (rst_i == `TRUE)
235			`begin`
236			ie <= `FALSE;
237			eie <= `FALSE;
238			`ifdef CFG_DEBUG_ENABLED
239			bie <= `FALSE;
240			`endif
241			`im <= {interrupts{1'b0}};`
242			`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
243			`ip <= {interrupts{1'b0}};`
244			`endif
245			`end`
246			`else`
247			`begin`
248			`// Set IP bit when interrupt line is asserted`
249			`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
250			`ip <= asserted;`
251			`endif
252			`ifdef CFG_DEBUG_ENABLED
253			if (non_debug_exception == `TRUE)
254			`begin`
255			`// Save and then clear interrupt enable`
256			`eie <= ie;`
257			ie <= `FALSE;
258			`end`
259			else if (debug_exception == `TRUE)
260			`begin`
261			`// Save and then clear interrupt enable`
262			`bie <= ie;`
263			ie <= `FALSE;
264			`end`
265			`else
266			if (exception == `TRUE)
267			`begin`
268			`// Save and then clear interrupt enable`
269			`eie <= ie;`
270			ie <= `FALSE;
271			`end`
272			`endif
273			else if (stall_x == `FALSE)
274			`begin`
275			if (eret_q_x == `TRUE)
276			`// Restore interrupt enable`
277			`ie <= eie;`
278			`ifdef CFG_DEBUG_ENABLED
279			else if (bret_q_x == `TRUE)
280			`// Restore interrupt enable`
281			`ie <= bie;`
282			`endif
283			else if (csr_write_enable == `TRUE)
284			`begin`
285			`// Handle wcsr write`
286			if ( (csr == `LM32_CSR_IE)
287			`ifdef CFG_MMU_ENABLED
288			\|\| (csr == `LM32_CSR_PSW)
289			`endif
290			`)`
291			`begin`
292			`ie <= csr_write_data[0];`
293			`eie <= csr_write_data[1];`
294			`ifdef CFG_DEBUG_ENABLED
295			`bie <= csr_write_data[2];`
296			`endif
297			`end`
298			if (csr == `LM32_CSR_IM)
299			`im <= csr_write_data[interrupts-1:0];`
300			`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
301			if (csr == `LM32_CSR_IP)
302			`ip <= asserted & ~csr_write_data[interrupts-1:0];`
303			`endif
304			`end`
305			`end`
306			`end`
307			`end`
308			`end`
309			`else`
310			`begin`
311			`// IE, IM, IP - Interrupt Enable, Interrupt Mask and Interrupt Pending CSRs`
312			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
313			`begin`
314			if (rst_i == `TRUE)
315			`begin`
316			ie <= `FALSE;
317			eie <= `FALSE;
318			`ifdef CFG_DEBUG_ENABLED
319			bie <= `FALSE;
320			`endif
321			`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
322			`ip <= {interrupts{1'b0}};`
323			`endif
324			`end`
325			`else`
326			`begin`
327			`// Set IP bit when interrupt line is asserted`
328			`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
329			`ip <= asserted;`
330			`endif
331			`ifdef CFG_DEBUG_ENABLED
332			if (non_debug_exception == `TRUE)
333			`begin`
334			`// Save and then clear interrupt enable`
335			`eie <= ie;`
336			ie <= `FALSE;
337			`end`
338			else if (debug_exception == `TRUE)
339			`begin`
340			`// Save and then clear interrupt enable`
341			`bie <= ie;`
342			ie <= `FALSE;
343			`end`
344			`else
345			if (exception == `TRUE)
346			`begin`
347			`// Save and then clear interrupt enable`
348			`eie <= ie;`
349			ie <= `FALSE;
350			`end`
351			`endif
352			else if (stall_x == `FALSE)
353			`begin`
354			if (eret_q_x == `TRUE)
355			`// Restore interrupt enable`
356			`ie <= eie;`
357			`ifdef CFG_DEBUG_ENABLED
358			else if (bret_q_x == `TRUE)
359			`// Restore interrupt enable`
360			`ie <= bie;`
361			`endif
362			else if (csr_write_enable == `TRUE)
363			`begin`
364			`// Handle wcsr write`
365			if ( (csr == `LM32_CSR_IE)
366			`ifdef CFG_MMU_ENABLED
367			\|\| (csr == `LM32_CSR_PSW)
368			`endif
369			`)`
370			`begin`
371			`ie <= csr_write_data[0];`
372			`eie <= csr_write_data[1];`
373			`ifdef CFG_DEBUG_ENABLED
374			`bie <= csr_write_data[2];`
375			`endif
376			`end`
377			`ifndef CFG_LEVEL_SENSITIVE_INTERRUPTS
378			if (csr == `LM32_CSR_IP)
379			`ip <= asserted & ~csr_write_data[interrupts-1:0];`
380			`endif
381			`end`
382			`end`
383			`end`
384			`end`
385			`end`
386			`endgenerate`
387
388			`endmodule`
389