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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_jtag.v] - Blame information for rev 48

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//   ==================================================================
//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
//   ------------------------------------------------------------------
//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
//   ALL RIGHTS RESERVED
//   ------------------------------------------------------------------
//
//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
//   Permission:
//
//      Lattice Semiconductor grants permission to use this code
//      pursuant to the terms of the Lattice Semiconductor Corporation
//      Open Source License Agreement.
//
//   Disclaimer:
//
//      Lattice Semiconductor provides no warranty regarding the use or
//      functionality of this code. It is the user's responsibility to
//      verify the user's design for consistency and functionality through
//      the use of formal verification methods.
//
//   --------------------------------------------------------------------
//
//                  Lattice Semiconductor Corporation
//                  5555 NE Moore Court
//                  Hillsboro, OR 97214
//                  U.S.A
//
//                  TEL: 1-800-Lattice (USA and Canada)
//                         503-286-8001 (other locations)
//
//                  web: http://www.latticesemi.com/
//                  email: techsupport@latticesemi.com
//
//   --------------------------------------------------------------------
//                         FILE DETAILS
// Project          : LatticeMico32
// File             : lm32_jtag.v
// Title            : JTAG interface
// Dependencies     : lm32_include.v
// Version          : 6.1.17
//                  : Initial Release
// Version          : 7.0SP2, 3.0
//                  : No Change
// Version          : 3.1
//                  : No Change
// =============================================================================
 
`include "lm32_include.v"
 
`ifdef CFG_JTAG_ENABLED
 
`define LM32_DP                             3'b000
`define LM32_TX                             3'b001
`define LM32_RX                             3'b010
 
// LM32 Debug Protocol commands IDs
`define LM32_DP_RNG                         3:0
`define LM32_DP_READ_MEMORY                 4'b0001
`define LM32_DP_WRITE_MEMORY                4'b0010
`define LM32_DP_READ_SEQUENTIAL             4'b0011
`define LM32_DP_WRITE_SEQUENTIAL            4'b0100
`define LM32_DP_WRITE_CSR                   4'b0101
`define LM32_DP_BREAK                       4'b0110
`define LM32_DP_RESET                       4'b0111
 
// States for FSM
`define LM32_JTAG_STATE_RNG                 3:0
`define LM32_JTAG_STATE_READ_COMMAND        4'h0
`define LM32_JTAG_STATE_READ_BYTE_0         4'h1
`define LM32_JTAG_STATE_READ_BYTE_1         4'h2
`define LM32_JTAG_STATE_READ_BYTE_2         4'h3
`define LM32_JTAG_STATE_READ_BYTE_3         4'h4
`define LM32_JTAG_STATE_READ_BYTE_4         4'h5
`define LM32_JTAG_STATE_PROCESS_COMMAND     4'h6
`define LM32_JTAG_STATE_WAIT_FOR_MEMORY     4'h7
`define LM32_JTAG_STATE_WAIT_FOR_CSR        4'h8
 
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
 
module lm32_jtag (
    // ----- Inputs -------
    clk_i,
    rst_i,
    jtag_clk,
    jtag_update,
    jtag_reg_q,
    jtag_reg_addr_q,
`ifdef CFG_JTAG_UART_ENABLED
    csr,
    csr_write_enable,
    csr_write_data,
    stall_x,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
    jtag_read_data,
    jtag_access_complete,
`endif
`ifdef CFG_DEBUG_ENABLED
    exception_q_w,
`endif
    // ----- Outputs -------
`ifdef CFG_JTAG_UART_ENABLED
    jtx_csr_read_data,
    jrx_csr_read_data,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
    jtag_csr_write_enable,
    jtag_csr_write_data,
    jtag_csr,
    jtag_read_enable,
    jtag_write_enable,
    jtag_write_data,
    jtag_address,
`endif
`ifdef CFG_DEBUG_ENABLED
    jtag_break,
    jtag_reset,
`endif
    jtag_reg_d,
    jtag_reg_addr_d
    );
 
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
 
input clk_i;                                            // Clock
input rst_i;                                            // Reset
 
input jtag_clk;                                         // JTAG clock
input jtag_update;                                      // JTAG data register has been updated
input [`LM32_BYTE_RNG] jtag_reg_q;                      // JTAG data register
input [2:0] jtag_reg_addr_q;                            // JTAG data register
 
`ifdef CFG_JTAG_UART_ENABLED
input [`LM32_CSR_RNG] csr;                              // CSR to write
input csr_write_enable;                                 // CSR write enable
input [`LM32_WORD_RNG] csr_write_data;                  // Data to write to specified CSR
input stall_x;                                          // Stall instruction in X stage
`endif
`ifdef CFG_HW_DEBUG_ENABLED
input [`LM32_BYTE_RNG] jtag_read_data;                  // Data read from requested address
input jtag_access_complete;                             // Memory access if complete
`endif
`ifdef CFG_DEBUG_ENABLED
input exception_q_w;                                    // Indicates an exception has occured in W stage
`endif
 
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
 
`ifdef CFG_JTAG_UART_ENABLED
output [`LM32_WORD_RNG] jtx_csr_read_data;              // Value of JTX CSR for rcsr instructions
wire   [`LM32_WORD_RNG] jtx_csr_read_data;
output [`LM32_WORD_RNG] jrx_csr_read_data;              // Value of JRX CSR for rcsr instructions
wire   [`LM32_WORD_RNG] jrx_csr_read_data;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
output jtag_csr_write_enable;                           // CSR write enable
reg    jtag_csr_write_enable;
output [`LM32_WORD_RNG] jtag_csr_write_data;            // Data to write to specified CSR
wire   [`LM32_WORD_RNG] jtag_csr_write_data;
output [`LM32_CSR_RNG] jtag_csr;                        // CSR to write
wire   [`LM32_CSR_RNG] jtag_csr;
output jtag_read_enable;                                // Memory read enable
reg    jtag_read_enable;
output jtag_write_enable;                               // Memory write enable
reg    jtag_write_enable;
output [`LM32_BYTE_RNG] jtag_write_data;                // Data to write to specified address
wire   [`LM32_BYTE_RNG] jtag_write_data;
output [`LM32_WORD_RNG] jtag_address;                   // Memory read/write address
wire   [`LM32_WORD_RNG] jtag_address;
`endif
`ifdef CFG_DEBUG_ENABLED
output jtag_break;                                      // Request to raise a breakpoint exception
reg    jtag_break;
output jtag_reset;                                      // Request to raise a reset exception
reg    jtag_reset;
`endif
output [`LM32_BYTE_RNG] jtag_reg_d;
reg    [`LM32_BYTE_RNG] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire   [2:0] jtag_reg_addr_d;
 
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
 
reg rx_toggle;                          // Clock-domain crossing registers
reg rx_toggle_r;                        // Registered version of rx_toggle
reg rx_toggle_r_r;                      // Registered version of rx_toggle_r
reg rx_toggle_r_r_r;                    // Registered version of rx_toggle_r_r
 
reg [`LM32_BYTE_RNG] rx_byte;
reg [2:0] rx_addr;
 
`ifdef CFG_JTAG_UART_ENABLED
reg [`LM32_BYTE_RNG] uart_tx_byte;      // UART TX data
reg uart_tx_valid;                      // TX data is valid
reg [`LM32_BYTE_RNG] uart_rx_byte;      // UART RX data
reg uart_rx_valid;                      // RX data is valid
`endif
 
reg [`LM32_DP_RNG] command;             // The last received command
`ifdef CFG_HW_DEBUG_ENABLED
reg [`LM32_BYTE_RNG] jtag_byte_0;       // Registers to hold command paramaters
reg [`LM32_BYTE_RNG] jtag_byte_1;
reg [`LM32_BYTE_RNG] jtag_byte_2;
reg [`LM32_BYTE_RNG] jtag_byte_3;
reg [`LM32_BYTE_RNG] jtag_byte_4;
reg processing;                         // Indicates if we're still processing a memory read/write
`endif
 
reg [`LM32_JTAG_STATE_RNG] state;       // Current state of FSM
 
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
 
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_write_data = jtag_byte_4;
`endif
 
// Generate status flags for reading via the JTAG interface
`ifdef CFG_JTAG_UART_ENABLED
assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
`else
assign jtag_reg_addr_d[1:0] = 2'b00;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_reg_addr_d[2] = processing;
`else
assign jtag_reg_addr_d[2] = 1'b0;
`endif
 
`ifdef CFG_JTAG_UART_ENABLED
assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
`endif
 
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
 
// Toggle a flag when a JTAG write occurs
 
always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
  rx_toggle <= 1'b0;
else
  rx_toggle <= ~rx_toggle;
end
 
always @(*)
begin
    rx_byte = jtag_reg_q;
    rx_addr = jtag_reg_addr_q;
end
 
// Clock domain crossing from JTAG clock domain to CPU clock domain
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        rx_toggle_r <= 1'b0;
        rx_toggle_r_r <= 1'b0;
        rx_toggle_r_r_r <= 1'b0;
    end
    else
    begin
        rx_toggle_r <= rx_toggle;
        rx_toggle_r_r <= rx_toggle_r;
        rx_toggle_r_r_r <= rx_toggle_r_r;
    end
end
 
// LM32 debug protocol state machine
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
    if (rst_i == `TRUE)
    begin
        state <= `LM32_JTAG_STATE_READ_COMMAND;
        command <= 4'b0000;
        jtag_reg_d <= 8'h00;
`ifdef CFG_HW_DEBUG_ENABLED
        processing <= `FALSE;
        jtag_csr_write_enable <= `FALSE;
        jtag_read_enable <= `FALSE;
        jtag_write_enable <= `FALSE;
`endif
`ifdef CFG_DEBUG_ENABLED
        jtag_break <= `FALSE;
        jtag_reset <= `FALSE;
`endif
`ifdef CFG_JTAG_UART_ENABLED
        uart_tx_byte <= 8'h00;
        uart_tx_valid <= `FALSE;
        uart_rx_byte <= 8'h00;
        uart_rx_valid <= `FALSE;
`endif
    end
    else
    begin
`ifdef CFG_JTAG_UART_ENABLED
        if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
        begin
            case (csr)
            `LM32_CSR_JTX:
            begin
                // Set flag indicating data is available
                uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
                uart_tx_valid <= `TRUE;
            end
            `LM32_CSR_JRX:
            begin
                // Clear flag indidicating data has been received
                uart_rx_valid <= `FALSE;
            end
            endcase
        end
`endif
`ifdef CFG_DEBUG_ENABLED
        // When an exception has occured, clear the requests
        if (exception_q_w == `TRUE)
        begin
            jtag_break <= `FALSE;
            jtag_reset <= `FALSE;
        end
`endif
        case (state)
        `LM32_JTAG_STATE_READ_COMMAND:
        begin
            // Wait for rx register to toggle which indicates new data is available
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                command <= rx_byte[7:4];
                case (rx_addr)
`ifdef CFG_DEBUG_ENABLED
                `LM32_DP:
                begin
                    case (rx_byte[7:4])
`ifdef CFG_HW_DEBUG_ENABLED
                    `LM32_DP_READ_MEMORY:
                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
                    `LM32_DP_READ_SEQUENTIAL:
                    begin
                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
                        state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
                    end
                    `LM32_DP_WRITE_MEMORY:
                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
                    `LM32_DP_WRITE_SEQUENTIAL:
                    begin
                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
                        state <= 5;
                    end
                    `LM32_DP_WRITE_CSR:
                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
`endif
                    `LM32_DP_BREAK:
                    begin
`ifdef CFG_JTAG_UART_ENABLED
                        uart_rx_valid <= `FALSE;
                        uart_tx_valid <= `FALSE;
`endif
                        jtag_break <= `TRUE;
                    end
                    `LM32_DP_RESET:
                    begin
`ifdef CFG_JTAG_UART_ENABLED
                        uart_rx_valid <= `FALSE;
                        uart_tx_valid <= `FALSE;
`endif
                        jtag_reset <= `TRUE;
                    end
                    endcase
                end
`endif
`ifdef CFG_JTAG_UART_ENABLED
                `LM32_TX:
                begin
                    uart_rx_byte <= rx_byte;
                    uart_rx_valid <= `TRUE;
                end
                `LM32_RX:
                begin
                    jtag_reg_d <= uart_tx_byte;
                    uart_tx_valid <= `FALSE;
                end
`endif
                default:
                    ;
                endcase
            end
        end
`ifdef CFG_HW_DEBUG_ENABLED
        `LM32_JTAG_STATE_READ_BYTE_0:
        begin
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                jtag_byte_0 <= rx_byte;
                state <= `LM32_JTAG_STATE_READ_BYTE_1;
            end
        end
        `LM32_JTAG_STATE_READ_BYTE_1:
        begin
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                jtag_byte_1 <= rx_byte;
                state <= `LM32_JTAG_STATE_READ_BYTE_2;
            end
        end
        `LM32_JTAG_STATE_READ_BYTE_2:
        begin
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                jtag_byte_2 <= rx_byte;
                state <= `LM32_JTAG_STATE_READ_BYTE_3;
            end
        end
        `LM32_JTAG_STATE_READ_BYTE_3:
        begin
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                jtag_byte_3 <= rx_byte;
                if (command == `LM32_DP_READ_MEMORY)
                    state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
                else
                    state <= `LM32_JTAG_STATE_READ_BYTE_4;
            end
        end
        `LM32_JTAG_STATE_READ_BYTE_4:
        begin
            if (rx_toggle_r_r != rx_toggle_r_r_r)
            begin
                jtag_byte_4 <= rx_byte;
                state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
            end
        end
        `LM32_JTAG_STATE_PROCESS_COMMAND:
        begin
            case (command)
            `LM32_DP_READ_MEMORY,
            `LM32_DP_READ_SEQUENTIAL:
            begin
                jtag_read_enable <= `TRUE;
                processing <= `TRUE;
                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
            end
            `LM32_DP_WRITE_MEMORY,
            `LM32_DP_WRITE_SEQUENTIAL:
            begin
                jtag_write_enable <= `TRUE;
                processing <= `TRUE;
                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
            end
            `LM32_DP_WRITE_CSR:
            begin
                jtag_csr_write_enable <= `TRUE;
                processing <= `TRUE;
                state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
            end
            endcase
        end
        `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
        begin
            if (jtag_access_complete == `TRUE)
            begin
                jtag_read_enable <= `FALSE;
                jtag_reg_d <= jtag_read_data;
                jtag_write_enable <= `FALSE;
                processing <= `FALSE;
                state <= `LM32_JTAG_STATE_READ_COMMAND;
            end
        end
        `LM32_JTAG_STATE_WAIT_FOR_CSR:
        begin
            jtag_csr_write_enable <= `FALSE;
            processing <= `FALSE;
            state <= `LM32_JTAG_STATE_READ_COMMAND;
        end
`endif
        endcase
    end
end
 
endmodule
 
`endif

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_jtag.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`// ==================================================================`
2			`// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<`
3			`// ------------------------------------------------------------------`
4			`// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation`
5			`// ALL RIGHTS RESERVED`
6			`// ------------------------------------------------------------------`
7			`//`
8			`// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.`
9			`//`
10			`// Permission:`
11			`//`
12			`// Lattice Semiconductor grants permission to use this code`
13			`// pursuant to the terms of the Lattice Semiconductor Corporation`
14			`// Open Source License Agreement.`
15			`//`
16			`// Disclaimer:`
17			`//`
18			`// Lattice Semiconductor provides no warranty regarding the use or`
19			`// functionality of this code. It is the user's responsibility to`
20			`// verify the user's design for consistency and functionality through`
21			`// the use of formal verification methods.`
22			`//`
23			`// --------------------------------------------------------------------`
24			`//`
25			`// Lattice Semiconductor Corporation`
26			`// 5555 NE Moore Court`
27			`// Hillsboro, OR 97214`
28			`// U.S.A`
29			`//`
30			`// TEL: 1-800-Lattice (USA and Canada)`
31			`// 503-286-8001 (other locations)`
32			`//`
33			`// web: http://www.latticesemi.com/`
34			`// email: techsupport@latticesemi.com`
35			`//`
36			`// --------------------------------------------------------------------`
37			`// FILE DETAILS`
38			`// Project : LatticeMico32`
39			`// File : lm32_jtag.v`
40			`// Title : JTAG interface`
41			`// Dependencies : lm32_include.v`
42			`// Version : 6.1.17`
43			`// : Initial Release`
44			`// Version : 7.0SP2, 3.0`
45			`// : No Change`
46			`// Version : 3.1`
47			`// : No Change`
48			`// =============================================================================`
49
50			`include "lm32_include.v"
51
52			`ifdef CFG_JTAG_ENABLED
53
54			`define LM32_DP 3'b000
55			`define LM32_TX 3'b001
56			`define LM32_RX 3'b010
57
58			`// LM32 Debug Protocol commands IDs`
59			`define LM32_DP_RNG 3:0
60			`define LM32_DP_READ_MEMORY 4'b0001
61			`define LM32_DP_WRITE_MEMORY 4'b0010
62			`define LM32_DP_READ_SEQUENTIAL 4'b0011
63			`define LM32_DP_WRITE_SEQUENTIAL 4'b0100
64			`define LM32_DP_WRITE_CSR 4'b0101
65			`define LM32_DP_BREAK 4'b0110
66			`define LM32_DP_RESET 4'b0111
67
68			`// States for FSM`
69			`define LM32_JTAG_STATE_RNG 3:0
70			`define LM32_JTAG_STATE_READ_COMMAND 4'h0
71			`define LM32_JTAG_STATE_READ_BYTE_0 4'h1
72			`define LM32_JTAG_STATE_READ_BYTE_1 4'h2
73			`define LM32_JTAG_STATE_READ_BYTE_2 4'h3
74			`define LM32_JTAG_STATE_READ_BYTE_3 4'h4
75			`define LM32_JTAG_STATE_READ_BYTE_4 4'h5
76			`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6
77			`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7
78			`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8
79
80			`/////////////////////////////////////////////////////`
81			`// Module interface`
82			`/////////////////////////////////////////////////////`
83
84			`module lm32_jtag (`
85			`// ----- Inputs -------`
86			`clk_i,`
87			`rst_i,`
88			`jtag_clk,`
89			`jtag_update,`
90			`jtag_reg_q,`
91			`jtag_reg_addr_q,`
92			`ifdef CFG_JTAG_UART_ENABLED
93			`csr,`
94			`csr_write_enable,`
95			`csr_write_data,`
96			`stall_x,`
97			`endif
98			`ifdef CFG_HW_DEBUG_ENABLED
99			`jtag_read_data,`
100			`jtag_access_complete,`
101			`endif
102			`ifdef CFG_DEBUG_ENABLED
103			`exception_q_w,`
104			`endif
105			`// ----- Outputs -------`
106			`ifdef CFG_JTAG_UART_ENABLED
107			`jtx_csr_read_data,`
108			`jrx_csr_read_data,`
109			`endif
110			`ifdef CFG_HW_DEBUG_ENABLED
111			`jtag_csr_write_enable,`
112			`jtag_csr_write_data,`
113			`jtag_csr,`
114			`jtag_read_enable,`
115			`jtag_write_enable,`
116			`jtag_write_data,`
117			`jtag_address,`
118			`endif
119			`ifdef CFG_DEBUG_ENABLED
120			`jtag_break,`
121			`jtag_reset,`
122			`endif
123			`jtag_reg_d,`
124			`jtag_reg_addr_d`
125			`);`
126
127			`/////////////////////////////////////////////////////`
128			`// Inputs`
129			`/////////////////////////////////////////////////////`
130
131			`input clk_i; // Clock`
132			`input rst_i; // Reset`
133
134			`input jtag_clk; // JTAG clock`
135			`input jtag_update; // JTAG data register has been updated`
136			input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register
137			`input [2:0] jtag_reg_addr_q; // JTAG data register`
138
139			`ifdef CFG_JTAG_UART_ENABLED
140			input [`LM32_CSR_RNG] csr; // CSR to write
141			`input csr_write_enable; // CSR write enable`
142			input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
143			`input stall_x; // Stall instruction in X stage`
144			`endif
145			`ifdef CFG_HW_DEBUG_ENABLED
146			input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address
147			`input jtag_access_complete; // Memory access if complete`
148			`endif
149			`ifdef CFG_DEBUG_ENABLED
150			`input exception_q_w; // Indicates an exception has occured in W stage`
151			`endif
152
153			`/////////////////////////////////////////////////////`
154			`// Outputs`
155			`/////////////////////////////////////////////////////`
156
157			`ifdef CFG_JTAG_UART_ENABLED
158			output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions
159			wire [`LM32_WORD_RNG] jtx_csr_read_data;
160			output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions
161			wire [`LM32_WORD_RNG] jrx_csr_read_data;
162			`endif
163			`ifdef CFG_HW_DEBUG_ENABLED
164			`output jtag_csr_write_enable; // CSR write enable`
165			`reg jtag_csr_write_enable;`
166			output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
167			wire [`LM32_WORD_RNG] jtag_csr_write_data;
168			output [`LM32_CSR_RNG] jtag_csr; // CSR to write
169			wire [`LM32_CSR_RNG] jtag_csr;
170			`output jtag_read_enable; // Memory read enable`
171			`reg jtag_read_enable;`
172			`output jtag_write_enable; // Memory write enable`
173			`reg jtag_write_enable;`
174			output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address
175			wire [`LM32_BYTE_RNG] jtag_write_data;
176			output [`LM32_WORD_RNG] jtag_address; // Memory read/write address
177			wire [`LM32_WORD_RNG] jtag_address;
178			`endif
179			`ifdef CFG_DEBUG_ENABLED
180			`output jtag_break; // Request to raise a breakpoint exception`
181			`reg jtag_break;`
182			`output jtag_reset; // Request to raise a reset exception`
183			`reg jtag_reset;`
184			`endif
185			output [`LM32_BYTE_RNG] jtag_reg_d;
186			reg [`LM32_BYTE_RNG] jtag_reg_d;
187			`output [2:0] jtag_reg_addr_d;`
188			`wire [2:0] jtag_reg_addr_d;`
189
190			`/////////////////////////////////////////////////////`
191			`// Internal nets and registers`
192			`/////////////////////////////////////////////////////`
193
194			`reg rx_toggle; // Clock-domain crossing registers`
195			`reg rx_toggle_r; // Registered version of rx_toggle`
196			`reg rx_toggle_r_r; // Registered version of rx_toggle_r`
197			`reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r`
198
199			reg [`LM32_BYTE_RNG] rx_byte;
200			`reg [2:0] rx_addr;`
201
202			`ifdef CFG_JTAG_UART_ENABLED
203			reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data
204			`reg uart_tx_valid; // TX data is valid`
205			reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data
206			`reg uart_rx_valid; // RX data is valid`
207			`endif
208
209			reg [`LM32_DP_RNG] command; // The last received command
210			`ifdef CFG_HW_DEBUG_ENABLED
211			reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters
212			reg [`LM32_BYTE_RNG] jtag_byte_1;
213			reg [`LM32_BYTE_RNG] jtag_byte_2;
214			reg [`LM32_BYTE_RNG] jtag_byte_3;
215			reg [`LM32_BYTE_RNG] jtag_byte_4;
216			`reg processing; // Indicates if we're still processing a memory read/write`
217			`endif
218
219			reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM
220
221			`/////////////////////////////////////////////////////`
222			`// Combinational Logic`
223			`/////////////////////////////////////////////////////`
224
225			`ifdef CFG_HW_DEBUG_ENABLED
226			`assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};`
227			assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
228			`assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};`
229			`assign jtag_write_data = jtag_byte_4;`
230			`endif
231
232			`// Generate status flags for reading via the JTAG interface`
233			`ifdef CFG_JTAG_UART_ENABLED
234			`assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};`
235			`else
236			`assign jtag_reg_addr_d[1:0] = 2'b00;`
237			`endif
238			`ifdef CFG_HW_DEBUG_ENABLED
239			`assign jtag_reg_addr_d[2] = processing;`
240			`else
241			`assign jtag_reg_addr_d[2] = 1'b0;`
242			`endif
243
244			`ifdef CFG_JTAG_UART_ENABLED
245			assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
246			assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
247			`endif
248
249			`/////////////////////////////////////////////////////`
250			`// Sequential Logic`
251			`/////////////////////////////////////////////////////`
252
253			`// Toggle a flag when a JTAG write occurs`
254
255			always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
256			`begin`
257			if (rst_i == `TRUE)
258			`rx_toggle <= 1'b0;`
259			`else`
260			`rx_toggle <= ~rx_toggle;`
261			`end`
262
263			`always @(*)`
264			`begin`
265			`rx_byte = jtag_reg_q;`
266			`rx_addr = jtag_reg_addr_q;`
267			`end`
268
269			`// Clock domain crossing from JTAG clock domain to CPU clock domain`
270			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
271			`begin`
272			if (rst_i == `TRUE)
273			`begin`
274			`rx_toggle_r <= 1'b0;`
275			`rx_toggle_r_r <= 1'b0;`
276			`rx_toggle_r_r_r <= 1'b0;`
277			`end`
278			`else`
279			`begin`
280			`rx_toggle_r <= rx_toggle;`
281			`rx_toggle_r_r <= rx_toggle_r;`
282			`rx_toggle_r_r_r <= rx_toggle_r_r;`
283			`end`
284			`end`
285
286			`// LM32 debug protocol state machine`
287			always @(posedge clk_i `CFG_RESET_SENSITIVITY)
288			`begin`
289			if (rst_i == `TRUE)
290			`begin`
291			state <= `LM32_JTAG_STATE_READ_COMMAND;
292			`command <= 4'b0000;`
293			`jtag_reg_d <= 8'h00;`
294			`ifdef CFG_HW_DEBUG_ENABLED
295			processing <= `FALSE;
296			jtag_csr_write_enable <= `FALSE;
297			jtag_read_enable <= `FALSE;
298			jtag_write_enable <= `FALSE;
299			`endif
300			`ifdef CFG_DEBUG_ENABLED
301			jtag_break <= `FALSE;
302			jtag_reset <= `FALSE;
303			`endif
304			`ifdef CFG_JTAG_UART_ENABLED
305			`uart_tx_byte <= 8'h00;`
306			uart_tx_valid <= `FALSE;
307			`uart_rx_byte <= 8'h00;`
308			uart_rx_valid <= `FALSE;
309			`endif
310			`end`
311			`else`
312			`begin`
313			`ifdef CFG_JTAG_UART_ENABLED
314			if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
315			`begin`
316			`case (csr)`
317			`LM32_CSR_JTX:
318			`begin`
319			`// Set flag indicating data is available`
320			uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
321			uart_tx_valid <= `TRUE;
322			`end`
323			`LM32_CSR_JRX:
324			`begin`
325			`// Clear flag indidicating data has been received`
326			uart_rx_valid <= `FALSE;
327			`end`
328			`endcase`
329			`end`
330			`endif
331			`ifdef CFG_DEBUG_ENABLED
332			`// When an exception has occured, clear the requests`
333			if (exception_q_w == `TRUE)
334			`begin`
335			jtag_break <= `FALSE;
336			jtag_reset <= `FALSE;
337			`end`
338			`endif
339			`case (state)`
340			`LM32_JTAG_STATE_READ_COMMAND:
341			`begin`
342			`// Wait for rx register to toggle which indicates new data is available`
343			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
344			`begin`
345			`command <= rx_byte[7:4];`
346			`case (rx_addr)`
347			`ifdef CFG_DEBUG_ENABLED
348			`LM32_DP:
349			`begin`
350			`case (rx_byte[7:4])`
351			`ifdef CFG_HW_DEBUG_ENABLED
352			`LM32_DP_READ_MEMORY:
353			state <= `LM32_JTAG_STATE_READ_BYTE_0;
354			`LM32_DP_READ_SEQUENTIAL:
355			`begin`
356			`{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;`
357			state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
358			`end`
359			`LM32_DP_WRITE_MEMORY:
360			state <= `LM32_JTAG_STATE_READ_BYTE_0;
361			`LM32_DP_WRITE_SEQUENTIAL:
362			`begin`
363			`{jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;`
364			`state <= 5;`
365			`end`
366			`LM32_DP_WRITE_CSR:
367			state <= `LM32_JTAG_STATE_READ_BYTE_0;
368			`endif
369			`LM32_DP_BREAK:
370			`begin`
371			`ifdef CFG_JTAG_UART_ENABLED
372			uart_rx_valid <= `FALSE;
373			uart_tx_valid <= `FALSE;
374			`endif
375			jtag_break <= `TRUE;
376			`end`
377			`LM32_DP_RESET:
378			`begin`
379			`ifdef CFG_JTAG_UART_ENABLED
380			uart_rx_valid <= `FALSE;
381			uart_tx_valid <= `FALSE;
382			`endif
383			jtag_reset <= `TRUE;
384			`end`
385			`endcase`
386			`end`
387			`endif
388			`ifdef CFG_JTAG_UART_ENABLED
389			`LM32_TX:
390			`begin`
391			`uart_rx_byte <= rx_byte;`
392			uart_rx_valid <= `TRUE;
393			`end`
394			`LM32_RX:
395			`begin`
396			`jtag_reg_d <= uart_tx_byte;`
397			uart_tx_valid <= `FALSE;
398			`end`
399			`endif
400			`default:`
401			`;`
402			`endcase`
403			`end`
404			`end`
405			`ifdef CFG_HW_DEBUG_ENABLED
406			`LM32_JTAG_STATE_READ_BYTE_0:
407			`begin`
408			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
409			`begin`
410			`jtag_byte_0 <= rx_byte;`
411			state <= `LM32_JTAG_STATE_READ_BYTE_1;
412			`end`
413			`end`
414			`LM32_JTAG_STATE_READ_BYTE_1:
415			`begin`
416			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
417			`begin`
418			`jtag_byte_1 <= rx_byte;`
419			state <= `LM32_JTAG_STATE_READ_BYTE_2;
420			`end`
421			`end`
422			`LM32_JTAG_STATE_READ_BYTE_2:
423			`begin`
424			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
425			`begin`
426			`jtag_byte_2 <= rx_byte;`
427			state <= `LM32_JTAG_STATE_READ_BYTE_3;
428			`end`
429			`end`
430			`LM32_JTAG_STATE_READ_BYTE_3:
431			`begin`
432			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
433			`begin`
434			`jtag_byte_3 <= rx_byte;`
435			if (command == `LM32_DP_READ_MEMORY)
436			state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
437			`else`
438			state <= `LM32_JTAG_STATE_READ_BYTE_4;
439			`end`
440			`end`
441			`LM32_JTAG_STATE_READ_BYTE_4:
442			`begin`
443			`if (rx_toggle_r_r != rx_toggle_r_r_r)`
444			`begin`
445			`jtag_byte_4 <= rx_byte;`
446			state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
447			`end`
448			`end`
449			`LM32_JTAG_STATE_PROCESS_COMMAND:
450			`begin`
451			`case (command)`
452			`LM32_DP_READ_MEMORY,
453			`LM32_DP_READ_SEQUENTIAL:
454			`begin`
455			jtag_read_enable <= `TRUE;
456			processing <= `TRUE;
457			state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
458			`end`
459			`LM32_DP_WRITE_MEMORY,
460			`LM32_DP_WRITE_SEQUENTIAL:
461			`begin`
462			jtag_write_enable <= `TRUE;
463			processing <= `TRUE;
464			state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
465			`end`
466			`LM32_DP_WRITE_CSR:
467			`begin`
468			jtag_csr_write_enable <= `TRUE;
469			processing <= `TRUE;
470			state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
471			`end`
472			`endcase`
473			`end`
474			`LM32_JTAG_STATE_WAIT_FOR_MEMORY:
475			`begin`
476			if (jtag_access_complete == `TRUE)
477			`begin`
478			jtag_read_enable <= `FALSE;
479			`jtag_reg_d <= jtag_read_data;`
480			jtag_write_enable <= `FALSE;
481			processing <= `FALSE;
482			state <= `LM32_JTAG_STATE_READ_COMMAND;
483			`end`
484			`end`
485			`LM32_JTAG_STATE_WAIT_FOR_CSR:
486			`begin`
487			jtag_csr_write_enable <= `FALSE;
488			processing <= `FALSE;
489			state <= `LM32_JTAG_STATE_READ_COMMAND;
490			`end`
491			`endif
492			`endcase`
493			`end`
494			`end`
495
496			`endmodule`
497
498			`endif