OpenCores
URL https://opencores.org/ocsvn/an-fpga-implementation-of-low-latency-noc-based-mpsoc/an-fpga-implementation-of-low-latency-noc-based-mpsoc/trunk

Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_logic_op.v] - Blame information for rev 48

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 48 alirezamon 
//   ==================================================================
2 
//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
3 
//   ------------------------------------------------------------------
4 
//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
5 
//   ALL RIGHTS RESERVED
6 
//   ------------------------------------------------------------------
7 
//
8 
//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
9 
//
10 
//   Permission:
11 
//
12 
//      Lattice Semiconductor grants permission to use this code
13 
//      pursuant to the terms of the Lattice Semiconductor Corporation
14 
//      Open Source License Agreement.
15 
//
16 
//   Disclaimer:
17 
//
18 
//      Lattice Semiconductor provides no warranty regarding the use or
19 
//      functionality of this code. It is the user's responsibility to
20 
//      verify the user's design for consistency and functionality through
21 
//      the use of formal verification methods.
22 
//
23 
//   --------------------------------------------------------------------
24 
//
25 
//                  Lattice Semiconductor Corporation
26 
//                  5555 NE Moore Court
27 
//                  Hillsboro, OR 97214
28 
//                  U.S.A
29 
//
30 
//                  TEL: 1-800-Lattice (USA and Canada)
31 
//                         503-286-8001 (other locations)
32 
//
33 
//                  web: http://www.latticesemi.com/
34 
//                  email: techsupport@latticesemi.com
35 
//
36 
//   --------------------------------------------------------------------
37 
//                         FILE DETAILS
38 
// Project          : LatticeMico32
39 
// File             : lm32_logic_op.v
40 
// Title            : Logic operations (and / or / not etc)
41 
// Dependencies     : lm32_include.v
42 
// Version          : 6.1.17
43 
//                  : Initial Release
44 
// Version          : 7.0SP2, 3.0
45 
//                  : No Change
46 
// Version          : 3.1
47 
//                  : No Change
48 
// =============================================================================
49 
 
50 
`include "lm32_include.v"
51 
 
52 
/////////////////////////////////////////////////////
53 
// Module interface
54 
/////////////////////////////////////////////////////
55 
 
56 
module lm32_logic_op (
57 
    // ----- Inputs -------
58 
    logic_op_x,
59 
    operand_0_x,
60 
    operand_1_x,
61 
    // ----- Outputs -------
62 
    logic_result_x
63 
    );
64 
 
65 
/////////////////////////////////////////////////////
66 
// Inputs
67 
/////////////////////////////////////////////////////
68 
 
69 
input [`LM32_LOGIC_OP_RNG] logic_op_x;
70 
input [`LM32_WORD_RNG] operand_0_x;
71 
input [`LM32_WORD_RNG] operand_1_x;
72 
 
73 
/////////////////////////////////////////////////////
74 
// Outputs
75 
/////////////////////////////////////////////////////
76 
 
77 
output [`LM32_WORD_RNG] logic_result_x;
78 
reg    [`LM32_WORD_RNG] logic_result_x;
79 
 
80 
/////////////////////////////////////////////////////
81 
// Internal nets and registers
82 
/////////////////////////////////////////////////////
83 
 
84 
integer logic_idx;
85 
 
86 
/////////////////////////////////////////////////////
87 
// Combinational Logic
88 
/////////////////////////////////////////////////////
89 
 
90 
always @(*)
91 
begin
92 
    for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1)
93 
        logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}];
94 
end
95 
 
96 
endmodule
97 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.