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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_top.v] - Blame information for rev 48

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//   ==================================================================
//   >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
//   ------------------------------------------------------------------
//   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
//   ALL RIGHTS RESERVED
//   ------------------------------------------------------------------
//
//   IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
//   Permission:
//
//      Lattice Semiconductor grants permission to use this code
//      pursuant to the terms of the Lattice Semiconductor Corporation
//      Open Source License Agreement.
//
//   Disclaimer:
//
//      Lattice Semiconductor provides no warranty regarding the use or
//      functionality of this code. It is the user's responsibility to
//      verify the user's design for consistency and functionality through
//      the use of formal verification methods.
//
//   --------------------------------------------------------------------
//
//                  Lattice Semiconductor Corporation
//                  5555 NE Moore Court
//                  Hillsboro, OR 97214
//                  U.S.A
//
//                  TEL: 1-800-Lattice (USA and Canada)
//                         503-286-8001 (other locations)
//
//                  web: http://www.latticesemi.com/
//                  email: techsupport@latticesemi.com
//
//   --------------------------------------------------------------------
//                         FILE DETAILS
// Project          : LatticeMico32
// File             : lm32_top.v
// Title            : Top-level of CPU.
// Dependencies     : lm32_include.v
// Version          : 6.1.17
//                  : removed SPI - 04/12/07
// Version          : 7.0SP2, 3.0
//                  : No Change
// Version          : 3.1
//                  : No Change
// =============================================================================
 
`include "lm32_include.v"
 
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
 
module lm32_top (
    // ----- Inputs -------
    clk_i,
    rst_i,
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
    at_debug,
`endif
`endif
    // From external devices
`ifdef CFG_INTERRUPTS_ENABLED
    interrupt,
`endif
    // From user logic
`ifdef CFG_USER_ENABLED
    user_result,
    user_complete,
`endif
`ifdef CFG_IWB_ENABLED
    // Instruction Wishbone master
    I_DAT_I,
    I_ACK_I,
    I_ERR_I,
    I_RTY_I,
`endif
`ifdef CFG_EXTERNAL_BREAK_ENABLED
    ext_break,
`endif
    // Data Wishbone master
    D_DAT_I,
    D_ACK_I,
    D_ERR_I,
    D_RTY_I,
    // ----- Outputs -------
`ifdef CFG_USER_ENABLED
    user_valid,
    user_opcode,
    user_operand_0,
    user_operand_1,
`endif
`ifdef CFG_IWB_ENABLED
    // Instruction Wishbone master
    I_DAT_O,
    I_ADR_O,
    I_CYC_O,
    I_SEL_O,
    I_STB_O,
    I_WE_O,
    I_CTI_O,
    I_LOCK_O,
    I_BTE_O,
`endif
    // Data Wishbone master
    D_DAT_O,
    D_ADR_O,
    D_CYC_O,
    D_SEL_O,
    D_STB_O,
    D_WE_O,
    D_CTI_O,
    D_LOCK_O,
    D_BTE_O
    );
 
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
 
input clk_i;                                    // Clock
input rst_i;                                    // Reset
 
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
input at_debug;                                 // GPIO input that maps EBA to DEBA
`endif
`endif
 
`ifdef CFG_INTERRUPTS_ENABLED
input [`LM32_INTERRUPT_RNG] interrupt;          // Interrupt pins
`endif
 
`ifdef CFG_USER_ENABLED
input [`LM32_WORD_RNG] user_result;             // User-defined instruction result
input user_complete;                            // Indicates the user-defined instruction result is valid
`endif
 
`ifdef CFG_IWB_ENABLED
input [`LM32_WORD_RNG] I_DAT_I;                 // Instruction Wishbone interface read data
input I_ACK_I;                                  // Instruction Wishbone interface acknowledgement
input I_ERR_I;                                  // Instruction Wishbone interface error
input I_RTY_I;                                  // Instruction Wishbone interface retry
`endif
 
input [`LM32_WORD_RNG] D_DAT_I;                 // Data Wishbone interface read data
input D_ACK_I;                                  // Data Wishbone interface acknowledgement
input D_ERR_I;                                  // Data Wishbone interface error
input D_RTY_I;                                  // Data Wishbone interface retry
 
`ifdef CFG_EXTERNAL_BREAK_ENABLED
input ext_break;
`endif
 
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
 
`ifdef CFG_USER_ENABLED
output user_valid;                              // Indicates that user_opcode and user_operand_* are valid
wire   user_valid;
output [`LM32_USER_OPCODE_RNG] user_opcode;     // User-defined instruction opcode
reg    [`LM32_USER_OPCODE_RNG] user_opcode;
output [`LM32_WORD_RNG] user_operand_0;         // First operand for user-defined instruction
wire   [`LM32_WORD_RNG] user_operand_0;
output [`LM32_WORD_RNG] user_operand_1;         // Second operand for user-defined instruction
wire   [`LM32_WORD_RNG] user_operand_1;
`endif
 
`ifdef CFG_IWB_ENABLED
output [`LM32_WORD_RNG] I_DAT_O;                // Instruction Wishbone interface write data
wire   [`LM32_WORD_RNG] I_DAT_O;
output [`LM32_WORD_RNG] I_ADR_O;                // Instruction Wishbone interface address
wire   [`LM32_WORD_RNG] I_ADR_O;
output I_CYC_O;                                 // Instruction Wishbone interface cycle
wire   I_CYC_O;
output [`LM32_BYTE_SELECT_RNG] I_SEL_O;         // Instruction Wishbone interface byte select
wire   [`LM32_BYTE_SELECT_RNG] I_SEL_O;
output I_STB_O;                                 // Instruction Wishbone interface strobe
wire   I_STB_O;
output I_WE_O;                                  // Instruction Wishbone interface write enable
wire   I_WE_O;
output [`LM32_CTYPE_RNG] I_CTI_O;               // Instruction Wishbone interface cycle type
wire   [`LM32_CTYPE_RNG] I_CTI_O;
output I_LOCK_O;                                // Instruction Wishbone interface lock bus
wire   I_LOCK_O;
output [`LM32_BTYPE_RNG] I_BTE_O;               // Instruction Wishbone interface burst type
wire   [`LM32_BTYPE_RNG] I_BTE_O;
`endif
 
output [`LM32_WORD_RNG] D_DAT_O;                // Data Wishbone interface write data
wire   [`LM32_WORD_RNG] D_DAT_O;
output [`LM32_WORD_RNG] D_ADR_O;                // Data Wishbone interface address
wire   [`LM32_WORD_RNG] D_ADR_O;
output D_CYC_O;                                 // Data Wishbone interface cycle
wire   D_CYC_O;
output [`LM32_BYTE_SELECT_RNG] D_SEL_O;         // Data Wishbone interface byte select
wire   [`LM32_BYTE_SELECT_RNG] D_SEL_O;
output D_STB_O;                                 // Data Wishbone interface strobe
wire   D_STB_O;
output D_WE_O;                                  // Data Wishbone interface write enable
wire   D_WE_O;
output [`LM32_CTYPE_RNG] D_CTI_O;               // Data Wishbone interface cycle type
wire   [`LM32_CTYPE_RNG] D_CTI_O;
output D_LOCK_O;                                // Date Wishbone interface lock bus
wire   D_LOCK_O;
output [`LM32_BTYPE_RNG] D_BTE_O;               // Data Wishbone interface burst type
wire   [`LM32_BTYPE_RNG] D_BTE_O;
 
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
 
`ifdef CFG_JTAG_ENABLED
// Signals between JTAG interface and CPU
wire [`LM32_BYTE_RNG] jtag_reg_d;
wire [`LM32_BYTE_RNG] jtag_reg_q;
wire jtag_update;
wire [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_q;
wire jtck;
wire jrstn;
`endif
 
// TODO: get the trace signals out
`ifdef CFG_TRACE_ENABLED
// PC trace signals
wire [`LM32_PC_RNG] trace_pc;                   // PC to trace (address of next non-sequential instruction)
wire trace_pc_valid;                            // Indicates that a new trace PC is valid
wire trace_exception;                           // Indicates an exception has occured
wire [`LM32_EID_RNG] trace_eid;                 // Indicates what type of exception has occured
wire trace_eret;                                // Indicates an eret instruction has been executed
`ifdef CFG_DEBUG_ENABLED
wire trace_bret;                                // Indicates a bret instruction has been executed
`endif
`endif
 
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
 
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
 
// LM32 CPU
lm32_cpu cpu (
    // ----- Inputs -------
    .clk_i                 (clk_i),
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
    .clk_n_i               (clk_n),
`endif
    .rst_i                 (rst_i),
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
    .at_debug              (at_debug),
`endif
`endif
    // From external devices
`ifdef CFG_INTERRUPTS_ENABLED
    .interrupt             (interrupt),
`endif
    // From user logic
`ifdef CFG_USER_ENABLED
    .user_result           (user_result),
    .user_complete         (user_complete),
`endif
`ifdef CFG_JTAG_ENABLED
    // From JTAG
    .jtag_clk              (jtck),
    .jtag_update           (jtag_update),
    .jtag_reg_q            (jtag_reg_q),
    .jtag_reg_addr_q       (jtag_reg_addr_q),
`endif
`ifdef CFG_EXTERNAL_BREAK_ENABLED
    .ext_break             (ext_break),
`endif
`ifdef CFG_IWB_ENABLED
     // Instruction Wishbone master
    .I_DAT_I               (I_DAT_I),
    .I_ACK_I               (I_ACK_I),
    .I_ERR_I               (I_ERR_I),
    .I_RTY_I               (I_RTY_I),
`endif
    // Data Wishbone master
    .D_DAT_I               (D_DAT_I),
    .D_ACK_I               (D_ACK_I),
    .D_ERR_I               (D_ERR_I),
    .D_RTY_I               (D_RTY_I),
    // ----- Outputs -------
`ifdef CFG_TRACE_ENABLED
    .trace_pc              (trace_pc),
    .trace_pc_valid        (trace_pc_valid),
    .trace_exception       (trace_exception),
    .trace_eid             (trace_eid),
    .trace_eret            (trace_eret),
`ifdef CFG_DEBUG_ENABLED
    .trace_bret            (trace_bret),
`endif
`endif
`ifdef CFG_JTAG_ENABLED
    .jtag_reg_d            (jtag_reg_d),
    .jtag_reg_addr_d       (jtag_reg_addr_d),
`endif
`ifdef CFG_USER_ENABLED
    .user_valid            (user_valid),
    .user_opcode           (user_opcode),
    .user_operand_0        (user_operand_0),
    .user_operand_1        (user_operand_1),
`endif
`ifdef CFG_IWB_ENABLED
    // Instruction Wishbone master
    .I_DAT_O               (I_DAT_O),
    .I_ADR_O               (I_ADR_O),
    .I_CYC_O               (I_CYC_O),
    .I_SEL_O               (I_SEL_O),
    .I_STB_O               (I_STB_O),
    .I_WE_O                (I_WE_O),
    .I_CTI_O               (I_CTI_O),
    .I_LOCK_O              (I_LOCK_O),
    .I_BTE_O               (I_BTE_O),
    `endif
    // Data Wishbone master
    .D_DAT_O               (D_DAT_O),
    .D_ADR_O               (D_ADR_O),
    .D_CYC_O               (D_CYC_O),
    .D_SEL_O               (D_SEL_O),
    .D_STB_O               (D_STB_O),
    .D_WE_O                (D_WE_O),
    .D_CTI_O               (D_CTI_O),
    .D_LOCK_O              (D_LOCK_O),
    .D_BTE_O               (D_BTE_O)
    );
 
`ifdef CFG_JTAG_ENABLED
// JTAG cores
jtag_cores jtag_cores (
    // ----- Inputs -----
    .reg_d                 (jtag_reg_d),
    .reg_addr_d            (jtag_reg_addr_d),
    // ----- Outputs -----
    .reg_update            (jtag_update),
    .reg_q                 (jtag_reg_q),
    .reg_addr_q            (jtag_reg_addr_q),
    .jtck                  (jtck),
    .jrstn                 (jrstn)
    );
`endif
 
endmodule

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [new_lm32/] [rtl/] [lm32_top.v] - Blame information for rev 48

Line No.	Rev	Author	Line
1	48	alirezamon	`// ==================================================================`
2			`// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<`
3			`// ------------------------------------------------------------------`
4			`// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation`
5			`// ALL RIGHTS RESERVED`
6			`// ------------------------------------------------------------------`
7			`//`
8			`// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.`
9			`//`
10			`// Permission:`
11			`//`
12			`// Lattice Semiconductor grants permission to use this code`
13			`// pursuant to the terms of the Lattice Semiconductor Corporation`
14			`// Open Source License Agreement.`
15			`//`
16			`// Disclaimer:`
17			`//`
18			`// Lattice Semiconductor provides no warranty regarding the use or`
19			`// functionality of this code. It is the user's responsibility to`
20			`// verify the user's design for consistency and functionality through`
21			`// the use of formal verification methods.`
22			`//`
23			`// --------------------------------------------------------------------`
24			`//`
25			`// Lattice Semiconductor Corporation`
26			`// 5555 NE Moore Court`
27			`// Hillsboro, OR 97214`
28			`// U.S.A`
29			`//`
30			`// TEL: 1-800-Lattice (USA and Canada)`
31			`// 503-286-8001 (other locations)`
32			`//`
33			`// web: http://www.latticesemi.com/`
34			`// email: techsupport@latticesemi.com`
35			`//`
36			`// --------------------------------------------------------------------`
37			`// FILE DETAILS`
38			`// Project : LatticeMico32`
39			`// File : lm32_top.v`
40			`// Title : Top-level of CPU.`
41			`// Dependencies : lm32_include.v`
42			`// Version : 6.1.17`
43			`// : removed SPI - 04/12/07`
44			`// Version : 7.0SP2, 3.0`
45			`// : No Change`
46			`// Version : 3.1`
47			`// : No Change`
48			`// =============================================================================`
49
50			`include "lm32_include.v"
51
52			`/////////////////////////////////////////////////////`
53			`// Module interface`
54			`/////////////////////////////////////////////////////`
55
56			`module lm32_top (`
57			`// ----- Inputs -------`
58			`clk_i,`
59			`rst_i,`
60			`ifdef CFG_DEBUG_ENABLED
61			`ifdef CFG_ALTERNATE_EBA
62			`at_debug,`
63			`endif
64			`endif
65			`// From external devices`
66			`ifdef CFG_INTERRUPTS_ENABLED
67			`interrupt,`
68			`endif
69			`// From user logic`
70			`ifdef CFG_USER_ENABLED
71			`user_result,`
72			`user_complete,`
73			`endif
74			`ifdef CFG_IWB_ENABLED
75			`// Instruction Wishbone master`
76			`I_DAT_I,`
77			`I_ACK_I,`
78			`I_ERR_I,`
79			`I_RTY_I,`
80			`endif
81			`ifdef CFG_EXTERNAL_BREAK_ENABLED
82			`ext_break,`
83			`endif
84			`// Data Wishbone master`
85			`D_DAT_I,`
86			`D_ACK_I,`
87			`D_ERR_I,`
88			`D_RTY_I,`
89			`// ----- Outputs -------`
90			`ifdef CFG_USER_ENABLED
91			`user_valid,`
92			`user_opcode,`
93			`user_operand_0,`
94			`user_operand_1,`
95			`endif
96			`ifdef CFG_IWB_ENABLED
97			`// Instruction Wishbone master`
98			`I_DAT_O,`
99			`I_ADR_O,`
100			`I_CYC_O,`
101			`I_SEL_O,`
102			`I_STB_O,`
103			`I_WE_O,`
104			`I_CTI_O,`
105			`I_LOCK_O,`
106			`I_BTE_O,`
107			`endif
108			`// Data Wishbone master`
109			`D_DAT_O,`
110			`D_ADR_O,`
111			`D_CYC_O,`
112			`D_SEL_O,`
113			`D_STB_O,`
114			`D_WE_O,`
115			`D_CTI_O,`
116			`D_LOCK_O,`
117			`D_BTE_O`
118			`);`
119
120			`/////////////////////////////////////////////////////`
121			`// Inputs`
122			`/////////////////////////////////////////////////////`
123
124			`input clk_i; // Clock`
125			`input rst_i; // Reset`
126
127			`ifdef CFG_DEBUG_ENABLED
128			`ifdef CFG_ALTERNATE_EBA
129			`input at_debug; // GPIO input that maps EBA to DEBA`
130			`endif
131			`endif
132
133			`ifdef CFG_INTERRUPTS_ENABLED
134			input [`LM32_INTERRUPT_RNG] interrupt; // Interrupt pins
135			`endif
136
137			`ifdef CFG_USER_ENABLED
138			input [`LM32_WORD_RNG] user_result; // User-defined instruction result
139			`input user_complete; // Indicates the user-defined instruction result is valid`
140			`endif
141
142			`ifdef CFG_IWB_ENABLED
143			input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
144			`input I_ACK_I; // Instruction Wishbone interface acknowledgement`
145			`input I_ERR_I; // Instruction Wishbone interface error`
146			`input I_RTY_I; // Instruction Wishbone interface retry`
147			`endif
148
149			input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
150			`input D_ACK_I; // Data Wishbone interface acknowledgement`
151			`input D_ERR_I; // Data Wishbone interface error`
152			`input D_RTY_I; // Data Wishbone interface retry`
153
154			`ifdef CFG_EXTERNAL_BREAK_ENABLED
155			`input ext_break;`
156			`endif
157
158			`/////////////////////////////////////////////////////`
159			`// Outputs`
160			`/////////////////////////////////////////////////////`
161
162			`ifdef CFG_USER_ENABLED
163			`output user_valid; // Indicates that user_opcode and user_operand_* are valid`
164			`wire user_valid;`
165			output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
166			reg [`LM32_USER_OPCODE_RNG] user_opcode;
167			output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
168			wire [`LM32_WORD_RNG] user_operand_0;
169			output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
170			wire [`LM32_WORD_RNG] user_operand_1;
171			`endif
172
173			`ifdef CFG_IWB_ENABLED
174			output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
175			wire [`LM32_WORD_RNG] I_DAT_O;
176			output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
177			wire [`LM32_WORD_RNG] I_ADR_O;
178			`output I_CYC_O; // Instruction Wishbone interface cycle`
179			`wire I_CYC_O;`
180			output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
181			wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
182			`output I_STB_O; // Instruction Wishbone interface strobe`
183			`wire I_STB_O;`
184			`output I_WE_O; // Instruction Wishbone interface write enable`
185			`wire I_WE_O;`
186			output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
187			wire [`LM32_CTYPE_RNG] I_CTI_O;
188			`output I_LOCK_O; // Instruction Wishbone interface lock bus`
189			`wire I_LOCK_O;`
190			output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
191			wire [`LM32_BTYPE_RNG] I_BTE_O;
192			`endif
193
194			output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
195			wire [`LM32_WORD_RNG] D_DAT_O;
196			output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
197			wire [`LM32_WORD_RNG] D_ADR_O;
198			`output D_CYC_O; // Data Wishbone interface cycle`
199			`wire D_CYC_O;`
200			output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
201			wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
202			`output D_STB_O; // Data Wishbone interface strobe`
203			`wire D_STB_O;`
204			`output D_WE_O; // Data Wishbone interface write enable`
205			`wire D_WE_O;`
206			output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
207			wire [`LM32_CTYPE_RNG] D_CTI_O;
208			`output D_LOCK_O; // Date Wishbone interface lock bus`
209			`wire D_LOCK_O;`
210			output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
211			wire [`LM32_BTYPE_RNG] D_BTE_O;
212
213			`/////////////////////////////////////////////////////`
214			`// Internal nets and registers`
215			`/////////////////////////////////////////////////////`
216
217			`ifdef CFG_JTAG_ENABLED
218			`// Signals between JTAG interface and CPU`
219			wire [`LM32_BYTE_RNG] jtag_reg_d;
220			wire [`LM32_BYTE_RNG] jtag_reg_q;
221			`wire jtag_update;`
222			`wire [2:0] jtag_reg_addr_d;`
223			`wire [2:0] jtag_reg_addr_q;`
224			`wire jtck;`
225			`wire jrstn;`
226			`endif
227
228			`// TODO: get the trace signals out`
229			`ifdef CFG_TRACE_ENABLED
230			`// PC trace signals`
231			wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction)
232			`wire trace_pc_valid; // Indicates that a new trace PC is valid`
233			`wire trace_exception; // Indicates an exception has occured`
234			wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
235			`wire trace_eret; // Indicates an eret instruction has been executed`
236			`ifdef CFG_DEBUG_ENABLED
237			`wire trace_bret; // Indicates a bret instruction has been executed`
238			`endif
239			`endif
240
241			`/////////////////////////////////////////////////////`
242			`// Functions`
243			`/////////////////////////////////////////////////////`
244
245			`/////////////////////////////////////////////////////`
246			`// Instantiations`
247			`/////////////////////////////////////////////////////`
248
249			`// LM32 CPU`
250			`lm32_cpu cpu (`
251			`// ----- Inputs -------`
252			`.clk_i (clk_i),`
253			`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
254			`.clk_n_i (clk_n),`
255			`endif
256			`.rst_i (rst_i),`
257			`ifdef CFG_DEBUG_ENABLED
258			`ifdef CFG_ALTERNATE_EBA
259			`.at_debug (at_debug),`
260			`endif
261			`endif
262			`// From external devices`
263			`ifdef CFG_INTERRUPTS_ENABLED
264			`.interrupt (interrupt),`
265			`endif
266			`// From user logic`
267			`ifdef CFG_USER_ENABLED
268			`.user_result (user_result),`
269			`.user_complete (user_complete),`
270			`endif
271			`ifdef CFG_JTAG_ENABLED
272			`// From JTAG`
273			`.jtag_clk (jtck),`
274			`.jtag_update (jtag_update),`
275			`.jtag_reg_q (jtag_reg_q),`
276			`.jtag_reg_addr_q (jtag_reg_addr_q),`
277			`endif
278			`ifdef CFG_EXTERNAL_BREAK_ENABLED
279			`.ext_break (ext_break),`
280			`endif
281			`ifdef CFG_IWB_ENABLED
282			`// Instruction Wishbone master`
283			`.I_DAT_I (I_DAT_I),`
284			`.I_ACK_I (I_ACK_I),`
285			`.I_ERR_I (I_ERR_I),`
286			`.I_RTY_I (I_RTY_I),`
287			`endif
288			`// Data Wishbone master`
289			`.D_DAT_I (D_DAT_I),`
290			`.D_ACK_I (D_ACK_I),`
291			`.D_ERR_I (D_ERR_I),`
292			`.D_RTY_I (D_RTY_I),`
293			`// ----- Outputs -------`
294			`ifdef CFG_TRACE_ENABLED
295			`.trace_pc (trace_pc),`
296			`.trace_pc_valid (trace_pc_valid),`
297			`.trace_exception (trace_exception),`
298			`.trace_eid (trace_eid),`
299			`.trace_eret (trace_eret),`
300			`ifdef CFG_DEBUG_ENABLED
301			`.trace_bret (trace_bret),`
302			`endif
303			`endif
304			`ifdef CFG_JTAG_ENABLED
305			`.jtag_reg_d (jtag_reg_d),`
306			`.jtag_reg_addr_d (jtag_reg_addr_d),`
307			`endif
308			`ifdef CFG_USER_ENABLED
309			`.user_valid (user_valid),`
310			`.user_opcode (user_opcode),`
311			`.user_operand_0 (user_operand_0),`
312			`.user_operand_1 (user_operand_1),`
313			`endif
314			`ifdef CFG_IWB_ENABLED
315			`// Instruction Wishbone master`
316			`.I_DAT_O (I_DAT_O),`
317			`.I_ADR_O (I_ADR_O),`
318			`.I_CYC_O (I_CYC_O),`
319			`.I_SEL_O (I_SEL_O),`
320			`.I_STB_O (I_STB_O),`
321			`.I_WE_O (I_WE_O),`
322			`.I_CTI_O (I_CTI_O),`
323			`.I_LOCK_O (I_LOCK_O),`
324			`.I_BTE_O (I_BTE_O),`
325			`endif
326			`// Data Wishbone master`
327			`.D_DAT_O (D_DAT_O),`
328			`.D_ADR_O (D_ADR_O),`
329			`.D_CYC_O (D_CYC_O),`
330			`.D_SEL_O (D_SEL_O),`
331			`.D_STB_O (D_STB_O),`
332			`.D_WE_O (D_WE_O),`
333			`.D_CTI_O (D_CTI_O),`
334			`.D_LOCK_O (D_LOCK_O),`
335			`.D_BTE_O (D_BTE_O)`
336			`);`
337
338			`ifdef CFG_JTAG_ENABLED
339			`// JTAG cores`
340			`jtag_cores jtag_cores (`
341			`// ----- Inputs -----`
342			`.reg_d (jtag_reg_d),`
343			`.reg_addr_d (jtag_reg_addr_d),`
344			`// ----- Outputs -----`
345			`.reg_update (jtag_update),`
346			`.reg_q (jtag_reg_q),`
347			`.reg_addr_q (jtag_reg_addr_q),`
348			`.jtck (jtck),`
349			`.jrstn (jrstn)`
350			`);`
351			`endif
352
353			`endmodule`