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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [or1200/] [sw/] [or1200/] [crt0.S] - Blame information for rev 38

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#include "spr-defs.h"
//#include "board.h"
 
/* ======================================================= [ macros ] === */
 
#define REDZONE 128
#define EXCEPTION_STACK_SIZE (128 + REDZONE)
 
#define CLEAR_GPR(gpr) \
        l.or    gpr, r0, r0
 
#define ENTRY(symbol)    \
        .global symbol ; \
symbol:
 
#define LOAD_SYMBOL_2_GPR(gpr,symbol)  \
        .global symbol ;               \
        l.movhi gpr, hi(symbol) ;      \
        l.ori   gpr, gpr, lo(symbol)
 
        // Really goes to configurable interrupt handler
#define EXCEPTION_HANDLER            \
        l.addi  r1, r1, -EXCEPTION_STACK_SIZE;          \
        l.sw    4(r1), r3;             \
        l.sw    8(r1), r4;             \
        l.mfspr r3,r0,SPR_NPC;          \
        l.mfspr r4,r0,SPR_EPCR_BASE;   \
        l.j default_exception_handler; \
        l.nop
 
/* =================================================== [ exceptions ] === */
        .section .vectors, "ax"
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
        .org 0x100
        l.movhi r0, 0
        l.movhi r1, 0
        l.movhi r2, 0
        l.movhi r3, 0
        l.movhi r4, 0
        l.movhi r5, 0
        l.movhi r6, 0
        l.movhi r7, 0
        l.movhi r8, 0
        l.movhi r9, 0
        l.movhi r10, 0
        l.movhi r11, 0
        l.movhi r12, 0
        l.movhi r13, 0
        l.movhi r14, 0
        l.movhi r15, 0
        l.movhi r16, 0
        l.movhi r17, 0
        l.movhi r18, 0
        l.movhi r19, 0
        l.movhi r20, 0
        l.movhi r21, 0
        l.movhi r22, 0
        l.movhi r23, 0
        l.movhi r24, 0
        l.movhi r25, 0
        l.movhi r26, 0
        l.movhi r27, 0
        l.movhi r28, 0
        l.movhi r29, 0
        l.movhi r30, 0
        l.movhi r31, 0
 
        /* Clear status register, set supervisor mode */
        l.ori r1, r0, SPR_SR_SM
        l.mtspr r0, r1, SPR_SR
        /* Clear timer  */
        l.mtspr r0, r0, SPR_TTMR
        /* Early Stack initilization */
        LOAD_SYMBOL_2_GPR(r1, _stack)
        l.addi  r2, r0, -3
        l.and   r1, r1, r2
 
        /* Jump to program initialisation code */
        LOAD_SYMBOL_2_GPR(r4, _start)
        l.jr    r4
        l.nop
 
/* ---[ 0x200: BUS exception ]------------------------------------------- */
        .org 0x200
        EXCEPTION_HANDLER
 
/* ---[ 0x300: Data Page Fault exception ]------------------------------- */
        .org 0x300
        EXCEPTION_HANDLER
 
/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
        .org 0x400
        EXCEPTION_HANDLER
 
/* ---[ 0x500: Timer exception ]----------------------------------------- */
        .org 0x500
        EXCEPTION_HANDLER
 
/* ---[ 0x600: Aligment exception ]-------------------------------------- */
        .org 0x600
        EXCEPTION_HANDLER
 
/* ---[ 0x700: Illegal insn exception ]---------------------------------- */
        .org 0x700
        EXCEPTION_HANDLER
 
/* ---[ 0x800: External interrupt exception ]---------------------------- */
        .org 0x800
        EXCEPTION_HANDLER
 
/* ---[ 0x900: DTLB miss exception ]------------------------------------- */
        .org 0x900
        EXCEPTION_HANDLER
 
/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
        .org 0xa00
        EXCEPTION_HANDLER
 
/* ---[ 0xb00: Range exception ]----------------------------------------- */
        .org 0xb00
        EXCEPTION_HANDLER
 
/* ---[ 0xc00: Syscall exception ]--------------------------------------- */
        .org 0xc00
        EXCEPTION_HANDLER
 
/* ---[ 0xd00: FPU exception ]------------------------------------------- */
        .org 0xd00
        EXCEPTION_HANDLER
 
/* ---[ 0xe00: Trap exception ]------------------------------------------ */
        .org 0xe00
        EXCEPTION_HANDLER
 
/* ---[ 0xf00 - 0x1400: Reserved exceptions ]---------------------------- */
/*
        .org 0xf00
        EXCEPTION_HANDLER
 
        .org 0x1000
        EXCEPTION_HANDLER
 
        .org 0x1100
        EXCEPTION_HANDLER
 
        .org 0x1200
        EXCEPTION_HANDLER
 
        .org 0x1300
        EXCEPTION_HANDLER
 
        .org 0x1400
        EXCEPTION_HANDLER
 
*/
/* ---[ 0x1500 - 0x1800: Implementation-specific exceptions ]------------ */
/*
        .org 0x1500
        EXCEPTION_HANDLER
 
        .org 0x1600
        EXCEPTION_HANDLER
 
        .org 0x1700
        EXCEPTION_HANDLER
 
        .org 0x1800
        EXCEPTION_HANDLER
*/
/* ---[ 0x1500 - 0x1F00: Custom exceptions ]----------------------------- */
/*
        .org 0x1900
        EXCEPTION_HANDLER
 
        .org 0x1a00
        EXCEPTION_HANDLER
 
        .org 0x1b00
        EXCEPTION_HANDLER
 
        .org 0x1c00
        EXCEPTION_HANDLER
 
        .org 0x1d00
        EXCEPTION_HANDLER
 
        .org 0x1e00
        EXCEPTION_HANDLER
 
        .org 0x1f00
        EXCEPTION_HANDLER
*/
 
/* ========================================================= [ entry ] === */
        .section .text
 
ENTRY(_start)
 
        /* Cache initialisation */
        l.jal _cache_init
        l.nop
 
        /* Clear BSS */
        LOAD_SYMBOL_2_GPR(r5, _bss_start)
        LOAD_SYMBOL_2_GPR(r6, _bss_end)
1:
        l.sw    (0)(r5), r0
        l.sfltu r5, r6
        l.bf    1b
        l.addi  r5, r5, 4
 
        /* Jump to main program entry point (argc = argv = 0) */
        CLEAR_GPR(r3)
        CLEAR_GPR(r4)
 
        l.nop   0x5
        l.jal   main
        l.nop
 
        /* If program exits, call exit routine */
        l.nop   0x6
        l.addi  r3, r11, 0
        l.jal   exit
        l.nop
 
 
/* ====================================== [ default exception handler ] === */
 
default_exception_handler:
        l.sw    0x00(r1), r2
        l.sw    0x0c(r1), r5
        l.sw    0x10(r1), r6
        l.sw    0x14(r1), r7
        l.sw    0x18(r1), r8
        l.sw    0x1c(r1), r9
        l.sw    0x20(r1), r10
        l.sw    0x24(r1), r11
        l.sw    0x28(r1), r12
        l.sw    0x2c(r1), r13
        l.sw    0x30(r1), r14
        l.sw    0x34(r1), r15
        l.sw    0x38(r1), r16
        l.sw    0x3c(r1), r17
        l.sw    0x40(r1), r18
        l.sw    0x44(r1), r19
        l.sw    0x48(r1), r20
        l.sw    0x4c(r1), r21
        l.sw    0x50(r1), r22
        l.sw    0x54(r1), r23
        l.sw    0x58(r1), r24
        l.sw    0x5c(r1), r25
        l.sw    0x60(r1), r26
        l.sw    0x64(r1), r27
        l.sw    0x68(r1), r28
        l.sw    0x6c(r1), r29
        l.sw    0x70(r1), r30
        l.sw    0x74(r1), r31
 
        l.jal   default_exception_handler_c
        l.nop
 
        l.lwz    r2, 0x00(r1)
        l.lwz    r3, 0x04(r1)
        l.lwz    r4, 0x08(r1)
        l.lwz    r5, 0x0c(r1)
        l.lwz    r6, 0x10(r1)
        l.lwz    r7, 0x14(r1)
        l.lwz    r8, 0x18(r1)
        l.lwz    r9, 0x1c(r1)
        l.lwz    r10, 0x20(r1)
        l.lwz    r11, 0x24(r1)
        l.lwz    r12, 0x28(r1)
        l.lwz    r13, 0x2c(r1)
        l.lwz    r14, 0x30(r1)
        l.lwz    r15, 0x34(r1)
        l.lwz    r16, 0x38(r1)
        l.lwz    r17, 0x3c(r1)
        l.lwz    r18, 0x40(r1)
        l.lwz    r19, 0x44(r1)
        l.lwz    r20, 0x48(r1)
        l.lwz    r21, 0x4c(r1)
        l.lwz    r22, 0x50(r1)
        l.lwz    r23, 0x54(r1)
        l.lwz    r24, 0x58(r1)
        l.lwz    r25, 0x5c(r1)
        l.lwz    r26, 0x60(r1)
        l.lwz    r27, 0x64(r1)
        l.lwz    r28, 0x68(r1)
        l.lwz    r29, 0x6c(r1)
        l.lwz    r30, 0x70(r1)
        l.lwz    r31, 0x74(r1)
 
        l.addi  r1, r1, EXCEPTION_STACK_SIZE
 
        l.rfe
        l.nop
 

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [or1200/] [sw/] [or1200/] [crt0.S] - Blame information for rev 38

Line No.	Rev	Author	Line
1	38	alirezamon	`#include "spr-defs.h"`
2			`//#include "board.h"`
3
4			`/* ======================================================= [ macros ] === */`
5
6			`#define REDZONE 128`
7			`#define EXCEPTION_STACK_SIZE (128 + REDZONE)`
8
9			`#define CLEAR_GPR(gpr) \`
10			`l.or gpr, r0, r0`
11
12			`#define ENTRY(symbol) \`
13			`.global symbol ; \`
14			`symbol:`
15
16			`#define LOAD_SYMBOL_2_GPR(gpr,symbol) \`
17			`.global symbol ; \`
18			`l.movhi gpr, hi(symbol) ; \`
19			`l.ori gpr, gpr, lo(symbol)`
20
21			`// Really goes to configurable interrupt handler`
22			`#define EXCEPTION_HANDLER \`
23			`l.addi r1, r1, -EXCEPTION_STACK_SIZE; \`
24			`l.sw 4(r1), r3; \`
25			`l.sw 8(r1), r4; \`
26			`l.mfspr r3,r0,SPR_NPC; \`
27			`l.mfspr r4,r0,SPR_EPCR_BASE; \`
28			`l.j default_exception_handler; \`
29			`l.nop`
30
31			`/* =================================================== [ exceptions ] === */`
32			`.section .vectors, "ax"`
33
34			`/* ---[ 0x100: RESET exception ]----------------------------------------- */`
35			`.org 0x100`
36			`l.movhi r0, 0`
37			`l.movhi r1, 0`
38			`l.movhi r2, 0`
39			`l.movhi r3, 0`
40			`l.movhi r4, 0`
41			`l.movhi r5, 0`
42			`l.movhi r6, 0`
43			`l.movhi r7, 0`
44			`l.movhi r8, 0`
45			`l.movhi r9, 0`
46			`l.movhi r10, 0`
47			`l.movhi r11, 0`
48			`l.movhi r12, 0`
49			`l.movhi r13, 0`
50			`l.movhi r14, 0`
51			`l.movhi r15, 0`
52			`l.movhi r16, 0`
53			`l.movhi r17, 0`
54			`l.movhi r18, 0`
55			`l.movhi r19, 0`
56			`l.movhi r20, 0`
57			`l.movhi r21, 0`
58			`l.movhi r22, 0`
59			`l.movhi r23, 0`
60			`l.movhi r24, 0`
61			`l.movhi r25, 0`
62			`l.movhi r26, 0`
63			`l.movhi r27, 0`
64			`l.movhi r28, 0`
65			`l.movhi r29, 0`
66			`l.movhi r30, 0`
67			`l.movhi r31, 0`
68
69			`/* Clear status register, set supervisor mode */`
70			`l.ori r1, r0, SPR_SR_SM`
71			`l.mtspr r0, r1, SPR_SR`
72			`/* Clear timer */`
73			`l.mtspr r0, r0, SPR_TTMR`
74			`/* Early Stack initilization */`
75			`LOAD_SYMBOL_2_GPR(r1, _stack)`
76			`l.addi r2, r0, -3`
77			`l.and r1, r1, r2`
78
79			`/* Jump to program initialisation code */`
80			`LOAD_SYMBOL_2_GPR(r4, _start)`
81			`l.jr r4`
82			`l.nop`
83
84			`/* ---[ 0x200: BUS exception ]------------------------------------------- */`
85			`.org 0x200`
86			`EXCEPTION_HANDLER`
87
88			`/* ---[ 0x300: Data Page Fault exception ]------------------------------- */`
89			`.org 0x300`
90			`EXCEPTION_HANDLER`
91
92			`/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */`
93			`.org 0x400`
94			`EXCEPTION_HANDLER`
95
96			`/* ---[ 0x500: Timer exception ]----------------------------------------- */`
97			`.org 0x500`
98			`EXCEPTION_HANDLER`
99
100			`/* ---[ 0x600: Aligment exception ]-------------------------------------- */`
101			`.org 0x600`
102			`EXCEPTION_HANDLER`
103
104			`/* ---[ 0x700: Illegal insn exception ]---------------------------------- */`
105			`.org 0x700`
106			`EXCEPTION_HANDLER`
107
108			`/* ---[ 0x800: External interrupt exception ]---------------------------- */`
109			`.org 0x800`
110			`EXCEPTION_HANDLER`
111
112			`/* ---[ 0x900: DTLB miss exception ]------------------------------------- */`
113			`.org 0x900`
114			`EXCEPTION_HANDLER`
115
116			`/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */`
117			`.org 0xa00`
118			`EXCEPTION_HANDLER`
119
120			`/* ---[ 0xb00: Range exception ]----------------------------------------- */`
121			`.org 0xb00`
122			`EXCEPTION_HANDLER`
123
124			`/* ---[ 0xc00: Syscall exception ]--------------------------------------- */`
125			`.org 0xc00`
126			`EXCEPTION_HANDLER`
127
128			`/* ---[ 0xd00: FPU exception ]------------------------------------------- */`
129			`.org 0xd00`
130			`EXCEPTION_HANDLER`
131
132			`/* ---[ 0xe00: Trap exception ]------------------------------------------ */`
133			`.org 0xe00`
134			`EXCEPTION_HANDLER`
135
136			`/* ---[ 0xf00 - 0x1400: Reserved exceptions ]---------------------------- */`
137			`/*`
138			`.org 0xf00`
139			`EXCEPTION_HANDLER`
140
141			`.org 0x1000`
142			`EXCEPTION_HANDLER`
143
144			`.org 0x1100`
145			`EXCEPTION_HANDLER`
146
147			`.org 0x1200`
148			`EXCEPTION_HANDLER`
149
150			`.org 0x1300`
151			`EXCEPTION_HANDLER`
152
153			`.org 0x1400`
154			`EXCEPTION_HANDLER`
155
156			`*/`
157			`/* ---[ 0x1500 - 0x1800: Implementation-specific exceptions ]------------ */`
158			`/*`
159			`.org 0x1500`
160			`EXCEPTION_HANDLER`
161
162			`.org 0x1600`
163			`EXCEPTION_HANDLER`
164
165			`.org 0x1700`
166			`EXCEPTION_HANDLER`
167
168			`.org 0x1800`
169			`EXCEPTION_HANDLER`
170			`*/`
171			`/* ---[ 0x1500 - 0x1F00: Custom exceptions ]----------------------------- */`
172			`/*`
173			`.org 0x1900`
174			`EXCEPTION_HANDLER`
175
176			`.org 0x1a00`
177			`EXCEPTION_HANDLER`
178
179			`.org 0x1b00`
180			`EXCEPTION_HANDLER`
181
182			`.org 0x1c00`
183			`EXCEPTION_HANDLER`
184
185			`.org 0x1d00`
186			`EXCEPTION_HANDLER`
187
188			`.org 0x1e00`
189			`EXCEPTION_HANDLER`
190
191			`.org 0x1f00`
192			`EXCEPTION_HANDLER`
193			`*/`
194
195			`/* ========================================================= [ entry ] === */`
196			`.section .text`
197
198			`ENTRY(_start)`
199
200			`/* Cache initialisation */`
201			`l.jal _cache_init`
202			`l.nop`
203
204			`/* Clear BSS */`
205			`LOAD_SYMBOL_2_GPR(r5, _bss_start)`
206			`LOAD_SYMBOL_2_GPR(r6, _bss_end)`
207			`1:`
208			`l.sw (0)(r5), r0`
209			`l.sfltu r5, r6`
210			`l.bf 1b`
211			`l.addi r5, r5, 4`
212
213			`/* Jump to main program entry point (argc = argv = 0) */`
214			`CLEAR_GPR(r3)`
215			`CLEAR_GPR(r4)`
216
217			`l.nop 0x5`
218			`l.jal main`
219			`l.nop`
220
221			`/* If program exits, call exit routine */`
222			`l.nop 0x6`
223			`l.addi r3, r11, 0`
224			`l.jal exit`
225			`l.nop`
226
227
228			`/* ====================================== [ default exception handler ] === */`
229
230			`default_exception_handler:`
231			`l.sw 0x00(r1), r2`
232			`l.sw 0x0c(r1), r5`
233			`l.sw 0x10(r1), r6`
234			`l.sw 0x14(r1), r7`
235			`l.sw 0x18(r1), r8`
236			`l.sw 0x1c(r1), r9`
237			`l.sw 0x20(r1), r10`
238			`l.sw 0x24(r1), r11`
239			`l.sw 0x28(r1), r12`
240			`l.sw 0x2c(r1), r13`
241			`l.sw 0x30(r1), r14`
242			`l.sw 0x34(r1), r15`
243			`l.sw 0x38(r1), r16`
244			`l.sw 0x3c(r1), r17`
245			`l.sw 0x40(r1), r18`
246			`l.sw 0x44(r1), r19`
247			`l.sw 0x48(r1), r20`
248			`l.sw 0x4c(r1), r21`
249			`l.sw 0x50(r1), r22`
250			`l.sw 0x54(r1), r23`
251			`l.sw 0x58(r1), r24`
252			`l.sw 0x5c(r1), r25`
253			`l.sw 0x60(r1), r26`
254			`l.sw 0x64(r1), r27`
255			`l.sw 0x68(r1), r28`
256			`l.sw 0x6c(r1), r29`
257			`l.sw 0x70(r1), r30`
258			`l.sw 0x74(r1), r31`
259
260			`l.jal default_exception_handler_c`
261			`l.nop`
262
263			`l.lwz r2, 0x00(r1)`
264			`l.lwz r3, 0x04(r1)`
265			`l.lwz r4, 0x08(r1)`
266			`l.lwz r5, 0x0c(r1)`
267			`l.lwz r6, 0x10(r1)`
268			`l.lwz r7, 0x14(r1)`
269			`l.lwz r8, 0x18(r1)`
270			`l.lwz r9, 0x1c(r1)`
271			`l.lwz r10, 0x20(r1)`
272			`l.lwz r11, 0x24(r1)`
273			`l.lwz r12, 0x28(r1)`
274			`l.lwz r13, 0x2c(r1)`
275			`l.lwz r14, 0x30(r1)`
276			`l.lwz r15, 0x34(r1)`
277			`l.lwz r16, 0x38(r1)`
278			`l.lwz r17, 0x3c(r1)`
279			`l.lwz r18, 0x40(r1)`
280			`l.lwz r19, 0x44(r1)`
281			`l.lwz r20, 0x48(r1)`
282			`l.lwz r21, 0x4c(r1)`
283			`l.lwz r22, 0x50(r1)`
284			`l.lwz r23, 0x54(r1)`
285			`l.lwz r24, 0x58(r1)`
286			`l.lwz r25, 0x5c(r1)`
287			`l.lwz r26, 0x60(r1)`
288			`l.lwz r27, 0x64(r1)`
289			`l.lwz r28, 0x68(r1)`
290			`l.lwz r29, 0x6c(r1)`
291			`l.lwz r30, 0x70(r1)`
292			`l.lwz r31, 0x74(r1)`
293
294			`l.addi r1, r1, EXCEPTION_STACK_SIZE`
295
296			`l.rfe`
297			`l.nop`
298