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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [or1200/] [verilog/] [src/] [or1200_dpram_32x32.v] - Blame information for rev 38

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1 38 alirezamon 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  Generic Double-Port Synchronous RAM                         ////
4 
////                                                              ////
5 
////  This file is part of memory library available from          ////
6 
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  This block is a wrapper with common double-port             ////
10 
////  synchronous memory interface for different                  ////
11 
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
12 
////  interface it also provides behavioral model of generic      ////
13 
////  double-port synchronous RAM.                                ////
14 
////  It should be used in all OPENCORES designs that want to be  ////
15 
////  portable accross different target technologies and          ////
16 
////  independent of target memory.                               ////
17 
////                                                              ////
18 
////  Supported ASIC RAMs are:                                    ////
19 
////  - Artisan Double-Port Sync RAM                              ////
20 
////  - Avant! Two-Port Sync RAM (*)                              ////
21 
////  - Virage 2-port Sync RAM                                    ////
22 
////                                                              ////
23 
////  Supported FPGA RAMs are:                                    ////
24 
////  - Xilinx Virtex RAMB16                                      ////
25 
////  - Xilinx Virtex RAMB4                                       ////
26 
////  - Altera LPM                                                ////
27 
////                                                              ////
28 
////  To Do:                                                      ////
29 
////   - fix Avant!                                               ////
30 
////   - xilinx rams need external tri-state logic                ////
31 
////   - add additional RAMs                                      ////
32 
////                                                              ////
33 
////  Author(s):                                                  ////
34 
////      - Damjan Lampret, lampret@opencores.org                 ////
35 
////                                                              ////
36 
//////////////////////////////////////////////////////////////////////
37 
////                                                              ////
38 
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
39 
////                                                              ////
40 
//// This source file may be used and distributed without         ////
41 
//// restriction provided that this copyright statement is not    ////
42 
//// removed from the file and that any derivative work contains  ////
43 
//// the original copyright notice and the associated disclaimer. ////
44 
////                                                              ////
45 
//// This source file is free software; you can redistribute it   ////
46 
//// and/or modify it under the terms of the GNU Lesser General   ////
47 
//// Public License as published by the Free Software Foundation; ////
48 
//// either version 2.1 of the License, or (at your option) any   ////
49 
//// later version.                                               ////
50 
////                                                              ////
51 
//// This source is distributed in the hope that it will be       ////
52 
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
53 
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
54 
//// PURPOSE.  See the GNU Lesser General Public License for more ////
55 
//// details.                                                     ////
56 
////                                                              ////
57 
//// You should have received a copy of the GNU Lesser General    ////
58 
//// Public License along with this source; if not, download it   ////
59 
//// from http://www.opencores.org/lgpl.shtml                     ////
60 
////                                                              ////
61 
//////////////////////////////////////////////////////////////////////
62 
//
63 
// CVS Revision History
64 
//
65 
// $Log: or1200_dpram_32x32.v,v $
66 
// Revision 2.0  2010/06/30 11:00:00  ORSoC
67 
// Minor update:
68 
// Coding style changed.
69 
//
70 
// Revision 1.10  2005/10/19 11:37:56  jcastillo
71 
// Added support for RAMB16 Xilinx4/Spartan3 primitives
72 
//
73 
// Revision 1.9  2004/06/08 18:15:48  lampret
74 
// Changed behavior of the simulation generic models
75 
//
76 
// Revision 1.8  2004/04/05 08:29:57  lampret
77 
// Merged branch_qmem into main tree.
78 
//
79 
// Revision 1.7.4.1  2003/07/08 15:36:37  lampret
80 
// Added embedded memory QMEM.
81 
//
82 
// Revision 1.7  2003/04/07 01:19:07  lampret
83 
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
84 
//
85 
// Revision 1.6  2002/03/28 19:25:42  lampret
86 
// Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.
87 
//
88 
// Revision 1.5  2002/02/01 19:56:54  lampret
89 
// Fixed combinational loops.
90 
//
91 
// Revision 1.4  2002/01/23 07:52:36  lampret
92 
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
93 
//
94 
// Revision 1.3  2002/01/19 14:10:22  lampret
95 
// Fixed OR1200_XILINX_RAM32X1D.
96 
//
97 
// Revision 1.2  2002/01/15 06:12:22  lampret
98 
// Fixed module name when compiling with OR1200_XILINX_RAM32X1D
99 
//
100 
// Revision 1.1  2002/01/03 08:16:15  lampret
101 
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
102 
//
103 
// Revision 1.10  2001/11/05 14:48:00  lampret
104 
// Added missing endif
105 
//
106 
// Revision 1.9  2001/11/02 18:57:14  lampret
107 
// Modified virtual silicon instantiations.
108 
//
109 
// Revision 1.8  2001/10/22 19:39:56  lampret
110 
// Fixed parameters in generic sprams.
111 
//
112 
// Revision 1.7  2001/10/21 17:57:16  lampret
113 
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
114 
//
115 
// Revision 1.6  2001/10/14 13:12:09  lampret
116 
// MP3 version.
117 
//
118 
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
119 
// no message
120 
//
121 
// Revision 1.1  2001/08/09 13:39:33  lampret
122 
// Major clean-up.
123 
//
124 
// Revision 1.2  2001/07/30 05:38:02  lampret
125 
// Adding empty directories required by HDL coding guidelines
126 
//
127 
//
128 
 
129 
// synopsys translate_off
130 
`include "timescale.v"
131 
// synopsys translate_on
132 
`include "or1200_defines.v"
133 
 
134 
module or1200_dpram_32x32(
135 
        // Generic synchronous double-port RAM interface
136 
        clk_a, rst_a, ce_a, oe_a, addr_a, do_a,
137 
        clk_b, rst_b, ce_b, we_b, addr_b, di_b
138 
);
139 
 
140 
//
141 
// Default address and data buses width
142 
//
143 
parameter aw = 5;
144 
parameter dw = 32;
145 
 
146 
//
147 
// Generic synchronous double-port RAM interface
148 
//
149 
input                   clk_a;  // Clock
150 
input                   rst_a;  // Reset
151 
input                   ce_a;   // Chip enable input
152 
input                   oe_a;   // Output enable input
153 
input   [aw-1:0] addr_a; // address bus inputs
154 
output  [dw-1:0] do_a;   // output data bus
155 
input                   clk_b;  // Clock
156 
input                   rst_b;  // Reset
157 
input                   ce_b;   // Chip enable input
158 
input                   we_b;   // Write enable input
159 
input   [aw-1:0] addr_b; // address bus inputs
160 
input   [dw-1:0] di_b;   // input data bus
161 
 
162 
//
163 
// Internal wires and registers
164 
//
165 
 
166 
`ifdef OR1200_ARTISAN_SDP
167 
 
168 
//
169 
// Instantiation of ASIC memory:
170 
//
171 
// Artisan Synchronous Double-Port RAM (ra2sh)
172 
//
173 
`ifdef UNUSED
174 
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
175 
`else
176 
art_hsdp_32x32 artisan_sdp(
177 
`endif
178 
        .qa(do_a),
179 
        .clka(clk_a),
180 
        .cena(~ce_a),
181 
        .wena(1'b1),
182 
        .aa(addr_a),
183 
        .da(32'h00000000),
184 
        .oena(~oe_a),
185 
        .qb(),
186 
        .clkb(clk_b),
187 
        .cenb(~ce_b),
188 
        .wenb(~we_b),
189 
        .ab(addr_b),
190 
        .db(di_b),
191 
        .oenb(1'b1)
192 
);
193 
 
194 
`else
195 
 
196 
`ifdef OR1200_AVANT_ATP
197 
 
198 
//
199 
// Instantiation of ASIC memory:
200 
//
201 
// Avant! Asynchronous Two-Port RAM
202 
//
203 
avant_atp avant_atp(
204 
        .web(~we),
205 
        .reb(),
206 
        .oeb(~oe),
207 
        .rcsb(),
208 
        .wcsb(),
209 
        .ra(addr),
210 
        .wa(addr),
211 
        .di(di),
212 
        .doq(doq)
213 
);
214 
 
215 
`else
216 
 
217 
`ifdef OR1200_VIRAGE_STP
218 
 
219 
//
220 
// Instantiation of ASIC memory:
221 
//
222 
// Virage Synchronous 2-port R/W RAM
223 
//
224 
virage_stp virage_stp(
225 
        .QA(do_a),
226 
        .QB(),
227 
 
228 
        .ADRA(addr_a),
229 
        .DA(32'h00000000),
230 
        .WEA(1'b0),
231 
        .OEA(oe_a),
232 
        .MEA(ce_a),
233 
        .CLKA(clk_a),
234 
 
235 
        .ADRB(addr_b),
236 
        .DB(di_b),
237 
        .WEB(we_b),
238 
        .OEB(1'b1),
239 
        .MEB(ce_b),
240 
        .CLKB(clk_b)
241 
);
242 
 
243 
`else
244 
 
245 
`ifdef OR1200_VIRTUALSILICON_STP_T1
246 
 
247 
//
248 
// Instantiation of ASIC memory:
249 
//
250 
// Virtual Silicon Two-port R/W SRAM Type 1
251 
//
252 
`ifdef UNUSED
253 
vs_hdtp_64x32 #(1<<aw, aw-1, dw-1) vs_ssp(
254 
`else
255 
vs_hdtp_64x32 vs_ssp(
256 
`endif
257 
        .P1CK(clk_a),
258 
        .P1CEN(~ce_a),
259 
        .P1WEN(1'b1),
260 
        .P1OEN(~oe_a),
261 
        .P1ADR({1'b0, addr_a}),
262 
        .P1DI(32'h0000_0000),
263 
        .P1DOUT(do_a),
264 
 
265 
        .P2CK(clk_b),
266 
        .P2CEN(~ce_b),
267 
        .P2WEN(~ce_b),
268 
        .P2OEN(1'b1),
269 
        .P2ADR({1'b0, addr_b}),
270 
        .P2DI(di_b),
271 
        .P2DOUT()
272 
);
273 
 
274 
`else
275 
 
276 
`ifdef OR1200_VIRTUALSILICON_STP_T2
277 
 
278 
//
279 
// Instantiation of ASIC memory:
280 
//
281 
// Virtual Silicon Two-port R/W SRAM Type 2
282 
//
283 
`ifdef UNUSED
284 
vs_hdtp_32x32 #(1<<aw, aw-1, dw-1) vs_ssp(
285 
`else
286 
vs_hdtp_32x32 vs_ssp(
287 
`endif
288 
        .RCK(clk_a),
289 
        .REN(~ce_a),
290 
        .OEN(~oe_a),
291 
        .RADR(addr_a),
292 
        .DOUT(do_a),
293 
 
294 
        .WCK(clk_b),
295 
        .WEN(~ce_b),
296 
        .WADR(addr_b),
297 
        .DI(di_b)
298 
);
299 
 
300 
`else
301 
 
302 
`ifdef OR1200_XILINX_RAM32X1D
303 
 
304 
//
305 
// Instantiation of FPGA memory:
306 
//
307 
// Virtex/Spartan2
308 
//
309 
 
310 
reg     [4:0]    addr_a_r;
311 
 
312 
always @(posedge clk_a or `OR1200_RST_EVENT rst_a)
313 
        if (rst_a == `OR1200_RST_VALUE)
314 
                addr_a_r <=  5'b00000;
315 
        else if (ce_a)
316 
                addr_a_r <=  addr_a;
317 
 
318 
//
319 
// Block 0
320 
//
321 
or1200_xcv_ram32x8d xcv_ram32x8d_0 (
322 
        .DPO(do_a[7:0]),
323 
        .SPO(),
324 
        .A(addr_b),
325 
        .D(di_b[7:0]),
326 
        .DPRA(addr_a_r),
327 
        .WCLK(clk_b),
328 
        .WE(we_b)
329 
);
330 
 
331 
//
332 
// Block 1
333 
//
334 
or1200_xcv_ram32x8d xcv_ram32x8d_1 (
335 
        .DPO(do_a[15:8]),
336 
        .SPO(),
337 
        .A(addr_b),
338 
        .D(di_b[15:8]),
339 
        .DPRA(addr_a_r),
340 
        .WCLK(clk_b),
341 
        .WE(we_b)
342 
);
343 
 
344 
 
345 
//
346 
// Block 2
347 
//
348 
or1200_xcv_ram32x8d xcv_ram32x8d_2 (
349 
        .DPO(do_a[23:16]),
350 
        .SPO(),
351 
        .A(addr_b),
352 
        .D(di_b[23:16]),
353 
        .DPRA(addr_a_r),
354 
        .WCLK(clk_b),
355 
        .WE(we_b)
356 
);
357 
 
358 
//
359 
// Block 3
360 
//
361 
or1200_xcv_ram32x8d xcv_ram32x8d_3 (
362 
        .DPO(do_a[31:24]),
363 
        .SPO(),
364 
        .A(addr_b),
365 
        .D(di_b[31:24]),
366 
        .DPRA(addr_a_r),
367 
        .WCLK(clk_b),
368 
        .WE(we_b)
369 
);
370 
 
371 
`else
372 
 
373 
`ifdef OR1200_XILINX_RAMB4
374 
 
375 
//
376 
// Instantiation of FPGA memory:
377 
//
378 
// Virtex/Spartan2
379 
//
380 
 
381 
//
382 
// Block 0
383 
//
384 
RAMB4_S16_S16 ramb4_s16_0(
385 
        .CLKA(clk_a),
386 
        .RSTA(1'b0),
387 
        .ADDRA({3'b000, addr_a}),
388 
        .DIA(16'h0000),
389 
        .ENA(ce_a),
390 
        .WEA(1'b0),
391 
        .DOA(do_a[15:0]),
392 
 
393 
        .CLKB(clk_b),
394 
        .RSTB(1'b0),
395 
        .ADDRB({3'b000, addr_b}),
396 
        .DIB(di_b[15:0]),
397 
        .ENB(ce_b),
398 
        .WEB(we_b),
399 
        .DOB()
400 
);
401 
 
402 
//
403 
// Block 1
404 
//
405 
RAMB4_S16_S16 ramb4_s16_1(
406 
        .CLKA(clk_a),
407 
        .RSTA(1'b0),
408 
        .ADDRA({3'b000, addr_a}),
409 
        .DIA(16'h0000),
410 
        .ENA(ce_a),
411 
        .WEA(1'b0),
412 
        .DOA(do_a[31:16]),
413 
 
414 
        .CLKB(clk_b),
415 
        .RSTB(1'b0),
416 
        .ADDRB({3'b000, addr_b}),
417 
        .DIB(di_b[31:16]),
418 
        .ENB(ce_b),
419 
        .WEB(we_b),
420 
        .DOB()
421 
);
422 
 
423 
`else
424 
 
425 
`ifdef OR1200_XILINX_RAMB16
426 
 
427 
//
428 
// Instantiation of FPGA memory:
429 
//
430 
// Virtex4/Spartan3E
431 
//
432 
// Added By Nir Mor
433 
//
434 
 
435 
RAMB16_S36_S36 ramb16_s36_s36(
436 
        .CLKA(clk_a),
437 
        .SSRA(1'b0),
438 
        .ADDRA({4'b0000, addr_a}),
439 
        .DIA(32'h00000000),
440 
        .DIPA(4'h0),
441 
        .ENA(ce_a),
442 
        .WEA(1'b0),
443 
        .DOA(do_a),
444 
        .DOPA(),
445 
 
446 
        .CLKB(clk_b),
447 
        .SSRB(1'b0),
448 
        .ADDRB({4'b0000, addr_b}),
449 
        .DIB(di_b),
450 
        .DIPB(4'h0),
451 
        .ENB(ce_b),
452 
        .WEB(we_b),
453 
        .DOB(),
454 
        .DOPB()
455 
);
456 
 
457 
`else
458 
 
459 
`ifdef OR1200_ALTERA_LPM_XXX
460 
 
461 
//
462 
// Instantiation of FPGA memory:
463 
//
464 
// Altera LPM
465 
//
466 
// Added By Jamil Khatib
467 
//
468 
altqpram altqpram_component (
469 
        .wraddress_a (addr_a),
470 
        .inclocken_a (ce_a),
471 
        .wraddress_b (addr_b),
472 
        .wren_a (we_a),
473 
        .inclocken_b (ce_b),
474 
        .wren_b (we_b),
475 
        .inaclr_a (1'b0),
476 
        .inaclr_b (1'b0),
477 
        .inclock_a (clk_a),
478 
        .inclock_b (clk_b),
479 
        .data_a (di_a),
480 
        .data_b (di_b),
481 
        .q_a (do_a),
482 
        .q_b (do_b)
483 
);
484 
 
485 
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
486 
        altqpram_component.width_write_a = dw,
487 
        altqpram_component.widthad_write_a = aw,
488 
        altqpram_component.numwords_write_a = dw,
489 
        altqpram_component.width_read_a = dw,
490 
        altqpram_component.widthad_read_a = aw,
491 
        altqpram_component.numwords_read_a = dw,
492 
        altqpram_component.width_write_b = dw,
493 
        altqpram_component.widthad_write_b = aw,
494 
        altqpram_component.numwords_write_b = dw,
495 
        altqpram_component.width_read_b = dw,
496 
        altqpram_component.widthad_read_b = aw,
497 
        altqpram_component.numwords_read_b = dw,
498 
        altqpram_component.indata_reg_a = "INCLOCK_A",
499 
        altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
500 
        altqpram_component.outdata_reg_a = "INCLOCK_A",
501 
        altqpram_component.indata_reg_b = "INCLOCK_B",
502 
        altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
503 
        altqpram_component.outdata_reg_b = "INCLOCK_B",
504 
        altqpram_component.indata_aclr_a = "INACLR_A",
505 
        altqpram_component.wraddress_aclr_a = "INACLR_A",
506 
        altqpram_component.wrcontrol_aclr_a = "INACLR_A",
507 
        altqpram_component.outdata_aclr_a = "INACLR_A",
508 
        altqpram_component.indata_aclr_b = "NONE",
509 
        altqpram_component.wraddress_aclr_b = "NONE",
510 
        altqpram_component.wrcontrol_aclr_b = "NONE",
511 
        altqpram_component.outdata_aclr_b = "INACLR_B",
512 
        altqpram_component.lpm_hint = "USE_ESB=ON";
513 
        //examplar attribute altqpram_component NOOPT TRUE
514 
 
515 
`else
516 
 
517 
//
518 
// Generic double-port synchronous RAM model
519 
//
520 
 
521 
//
522 
// Generic RAM's registers and wires
523 
//
524 
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
525 
reg     [aw-1:0] addr_a_reg;             // RAM address registered
526 
 
527 
//
528 
// Data output drivers
529 
//
530 
assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
531 
 
532 
//
533 
// RAM read
534 
//
535 
always @(posedge clk_a or `OR1200_RST_EVENT rst_a)
536 
        if (rst_a == `OR1200_RST_VALUE)
537 
                addr_a_reg <=  {aw{1'b0}};
538 
        else if (ce_a)
539 
                addr_a_reg <=  addr_a;
540 
 
541 
//
542 
// RAM write
543 
//
544 
always @(posedge clk_b)
545 
        if (ce_b && we_b)
546 
                mem[addr_b] <=  di_b;
547 
 
548 
`endif  // !OR1200_ALTERA_LPM
549 
`endif  // !OR1200_XILINX_RAMB16
550 
`endif  // !OR1200_XILINX_RAMB4
551 
`endif  // !OR1200_XILINX_RAM32X1D
552 
`endif  // !OR1200_VIRTUALSILICON_SSP_T1
553 
`endif  // !OR1200_VIRTUALSILICON_SSP_T2
554 
`endif  // !OR1200_VIRAGE_STP
555 
`endif  // !OR1200_AVANT_ATP
556 
`endif  // !OR1200_ARTISAN_SDP
557 
 
558 
endmodule

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