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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [or1200/] [verilog/] [src/] [or1200_fpu_div.v] - Blame information for rev 38

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  or1200_fpu_div                                              ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://opencores.org/project,or1k                           ////
////                                                              ////
////  Description                                                 ////
////  division entity for the division unit                       ////
////                                                              ////
////  To Do:                                                      ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////      - Original design (FPU100) -                            ////
////        Jidan Al-eryani, jidan@gmx.net                        ////
////      - Conv. to Verilog and inclusion in OR1200 -            ////
////        Julius Baxter, julius@opencores.org                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
//  Copyright (C) 2006, 2010
//
//      This source file may be used and distributed without        
//      restriction provided that this copyright statement is not   
//      removed from the file and that any derivative work contains 
//      the original copyright notice and the associated disclaimer.
//                                                           
//              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     
//      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   
//      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   
//      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      
//      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         
//      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    
//      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   
//      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        
//      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  
//      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  
//      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  
//      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         
//      POSSIBILITY OF SUCH DAMAGE. 
//
 
module or1200_fpu_div
  (
   clk_i,
   dvdnd_i,
   dvsor_i,
   sign_dvd_i,
   sign_div_i,
   start_i,
   ready_o,
   qutnt_o,
   rmndr_o,
   sign_o,
   div_zero_o
   );
 
   parameter FP_WIDTH = 32;
   parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
   parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
   parameter FRAC_WIDTH = 23;
   parameter EXP_WIDTH = 8;
   parameter ZERO_VECTOR = 31'd0;
   parameter INF = 31'b1111111100000000000000000000000;
   parameter QNAN = 31'b1111111110000000000000000000000;
   parameter SNAN = 31'b1111111100000000000000000000001;
 
 
   input clk_i;
   input [2*(FRAC_WIDTH+2)-1:0] dvdnd_i;
   input [FRAC_WIDTH+3:0]        dvsor_i;
   input                        sign_dvd_i;
   input                        sign_div_i;
   input                        start_i;
   output                       ready_o;
   output [FRAC_WIDTH+3:0]       qutnt_o;
   output [FRAC_WIDTH+3:0]       rmndr_o;
   output                       sign_o;
   output                       div_zero_o;
 
   parameter t_state_waiting = 1'b0,
               t_state_busy = 1'b1;
 
   reg [FRAC_WIDTH+3:0]  s_qutnt_o;
   reg [FRAC_WIDTH+3:0]  s_rmndr_o;
   reg [2*(FRAC_WIDTH+2)-1:0]    s_dvdnd_i;
   reg [FRAC_WIDTH+3:0]  s_dvsor_i;
   reg                          s_sign_dvd_i, s_sign_div_i;
   wire                         s_sign_o;
   wire                         s_div_zero_o;
   reg                          s_start_i;
   reg                          s_ready_o;
   reg                          s_state;
   reg [4:0]                     s_count;
   reg [FRAC_WIDTH+3:0]  s_dvd;
 
   // Input Register
   always @(posedge clk_i)
     begin
        s_dvdnd_i <= dvdnd_i;
        s_dvsor_i <= dvsor_i;
        s_sign_dvd_i<= sign_dvd_i;
        s_sign_div_i<= sign_div_i;
        s_start_i <= start_i;
     end
 
   assign qutnt_o = s_qutnt_o;
   assign rmndr_o = s_rmndr_o;
   assign sign_o = s_sign_o;
   assign ready_o = s_ready_o;
   assign div_zero_o = s_div_zero_o;
 
   assign s_sign_o = sign_dvd_i ^ sign_div_i;
   assign s_div_zero_o = !(|s_dvsor_i) & (|s_dvdnd_i);
 
 
   always @(posedge clk_i)
     if (s_start_i)
       begin
          s_state <= t_state_busy;
          s_count <= 26;
       end
     else if (!(|s_count) & s_state==t_state_busy)
       begin
          s_state <= t_state_waiting;
          s_ready_o <= 1;
          s_count <=26;
       end
     else if (s_state==t_state_busy)
       s_count <= s_count - 1;
     else
       begin
          s_state <= t_state_waiting;
          s_ready_o <= 0;
       end
 
   wire [26:0] v_div;
   assign v_div = (s_count==26) ? {3'd0,s_dvdnd_i[49:26]} : s_dvd;
   wire [26:0] v_div_minus_s_dvsor_i;
   assign v_div_minus_s_dvsor_i = v_div - s_dvsor_i;
 
 
   always @(posedge clk_i)
     begin
        //Reset
        if (s_start_i)
          begin
             s_qutnt_o <= 0;
             s_rmndr_o <= 0;
          end
        else if (s_state==t_state_busy)
          begin
 
             if (v_div < s_dvsor_i)
               begin
                  s_qutnt_o[s_count] <= 1'b0;
                  s_dvd <= {v_div[25:0],1'b0};
               end
             else
               begin
                  s_qutnt_o[s_count] <= 1'b1;
                  s_dvd <= {v_div_minus_s_dvsor_i[25:0],1'b0};
               end
 
             s_rmndr_o <= v_div;
 
          end // if (s_state==t_state_busy)
     end // always @ (posedge clk_i)
 
endmodule // or1200_fpu_div
 

Line No.	Rev	Author	Line
1	38	alirezamon	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// or1200_fpu_div ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// division entity for the division unit ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Original design (FPU100) - ////`
16			`//// Jidan Al-eryani, jidan@gmx.net ////`
17			`//// - Conv. to Verilog and inclusion in OR1200 - ////`
18			`//// Julius Baxter, julius@opencores.org ////`
19			`//// ////`
20			`//////////////////////////////////////////////////////////////////////`
21			`//`
22			`// Copyright (C) 2006, 2010`
23			`//`
24			`// This source file may be used and distributed without`
25			`// restriction provided that this copyright statement is not`
26			`// removed from the file and that any derivative work contains`
27			`// the original copyright notice and the associated disclaimer.`
28			`//`
29			// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
30			`// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED`
31			`// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS`
32			`// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR`
33			`// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,`
34			`// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES`
35			`// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE`
36			`// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR`
37			`// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF`
38			`// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
39			`// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT`
40			`// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE`
41			`// POSSIBILITY OF SUCH DAMAGE.`
42			`//`
43
44			`module or1200_fpu_div`
45			`(`
46			`clk_i,`
47			`dvdnd_i,`
48			`dvsor_i,`
49			`sign_dvd_i,`
50			`sign_div_i,`
51			`start_i,`
52			`ready_o,`
53			`qutnt_o,`
54			`rmndr_o,`
55			`sign_o,`
56			`div_zero_o`
57			`);`
58
59			`parameter FP_WIDTH = 32;`
60			`parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial`
61			`parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial`
62			`parameter FRAC_WIDTH = 23;`
63			`parameter EXP_WIDTH = 8;`
64			`parameter ZERO_VECTOR = 31'd0;`
65			`parameter INF = 31'b1111111100000000000000000000000;`
66			`parameter QNAN = 31'b1111111110000000000000000000000;`
67			`parameter SNAN = 31'b1111111100000000000000000000001;`
68
69
70			`input clk_i;`
71			`input [2*(FRAC_WIDTH+2)-1:0] dvdnd_i;`
72			`input [FRAC_WIDTH+3:0] dvsor_i;`
73			`input sign_dvd_i;`
74			`input sign_div_i;`
75			`input start_i;`
76			`output ready_o;`
77			`output [FRAC_WIDTH+3:0] qutnt_o;`
78			`output [FRAC_WIDTH+3:0] rmndr_o;`
79			`output sign_o;`
80			`output div_zero_o;`
81
82			`parameter t_state_waiting = 1'b0,`
83			`t_state_busy = 1'b1;`
84
85			`reg [FRAC_WIDTH+3:0] s_qutnt_o;`
86			`reg [FRAC_WIDTH+3:0] s_rmndr_o;`
87			`reg [2*(FRAC_WIDTH+2)-1:0] s_dvdnd_i;`
88			`reg [FRAC_WIDTH+3:0] s_dvsor_i;`
89			`reg s_sign_dvd_i, s_sign_div_i;`
90			`wire s_sign_o;`
91			`wire s_div_zero_o;`
92			`reg s_start_i;`
93			`reg s_ready_o;`
94			`reg s_state;`
95			`reg [4:0] s_count;`
96			`reg [FRAC_WIDTH+3:0] s_dvd;`
97
98			`// Input Register`
99			`always @(posedge clk_i)`
100			`begin`
101			`s_dvdnd_i <= dvdnd_i;`
102			`s_dvsor_i <= dvsor_i;`
103			`s_sign_dvd_i<= sign_dvd_i;`
104			`s_sign_div_i<= sign_div_i;`
105			`s_start_i <= start_i;`
106			`end`
107
108			`assign qutnt_o = s_qutnt_o;`
109			`assign rmndr_o = s_rmndr_o;`
110			`assign sign_o = s_sign_o;`
111			`assign ready_o = s_ready_o;`
112			`assign div_zero_o = s_div_zero_o;`
113
114			`assign s_sign_o = sign_dvd_i ^ sign_div_i;`
115			`assign s_div_zero_o = !(\|s_dvsor_i) & (\|s_dvdnd_i);`
116
117
118			`always @(posedge clk_i)`
119			`if (s_start_i)`
120			`begin`
121			`s_state <= t_state_busy;`
122			`s_count <= 26;`
123			`end`
124			`else if (!(\|s_count) & s_state==t_state_busy)`
125			`begin`
126			`s_state <= t_state_waiting;`
127			`s_ready_o <= 1;`
128			`s_count <=26;`
129			`end`
130			`else if (s_state==t_state_busy)`
131			`s_count <= s_count - 1;`
132			`else`
133			`begin`
134			`s_state <= t_state_waiting;`
135			`s_ready_o <= 0;`
136			`end`
137
138			`wire [26:0] v_div;`
139			`assign v_div = (s_count==26) ? {3'd0,s_dvdnd_i[49:26]} : s_dvd;`
140			`wire [26:0] v_div_minus_s_dvsor_i;`
141			`assign v_div_minus_s_dvsor_i = v_div - s_dvsor_i;`
142
143
144			`always @(posedge clk_i)`
145			`begin`
146			`//Reset`
147			`if (s_start_i)`
148			`begin`
149			`s_qutnt_o <= 0;`
150			`s_rmndr_o <= 0;`
151			`end`
152			`else if (s_state==t_state_busy)`
153			`begin`
154
155			`if (v_div < s_dvsor_i)`
156			`begin`
157			`s_qutnt_o[s_count] <= 1'b0;`
158			`s_dvd <= {v_div[25:0],1'b0};`
159			`end`
160			`else`
161			`begin`
162			`s_qutnt_o[s_count] <= 1'b1;`
163			`s_dvd <= {v_div_minus_s_dvsor_i[25:0],1'b0};`
164			`end`
165
166			`s_rmndr_o <= v_div;`
167
168			`end // if (s_state==t_state_busy)`
169			`end // always @ (posedge clk_i)`
170
171			`endmodule // or1200_fpu_div`
172

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [or1200/] [verilog/] [src/] [or1200_fpu_div.v] - Blame information for rev 38