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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [or1200/] [verilog/] [src/] [or1200_genpc.v] - Blame information for rev 38

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's generate PC                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  PC, interface to IC.                                        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_genpc.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Structure reordered and bugs fixed. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_genpc(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
        icpu_rty_i, icpu_adr_i,
 
        // Internal i/f
        pre_branch_op, branch_op, except_type, except_prefix,
        id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,
        flag, flagforw, ex_branch_taken, except_start,
        epcr, spr_dat_i, spr_pc_we, genpc_refetch,
        genpc_freeze, no_more_dslot, lsu_stall, du_flush_pipe, spr_dat_npc
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
output  [31:0]                   icpu_adr_o;
output                          icpu_cycstb_o;
output  [3:0]                    icpu_sel_o;
output  [3:0]                    icpu_tag_o;
input                           icpu_rty_i;
input   [31:0]                   icpu_adr_i;
 
//
// Internal i/f
//
input   [`OR1200_BRANCHOP_WIDTH-1:0]    pre_branch_op;
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
input                                   except_prefix;
input   [31:2]                  id_branch_addrtarget;
input   [31:2]                  ex_branch_addrtarget;
input   [31:0]                   muxed_b;
input   [31:0]                   operand_b;
input                           flag;
input                           flagforw;
output                          ex_branch_taken;
input                           except_start;
input   [31:0]                   epcr;
input   [31:0]                   spr_dat_i;
input                           spr_pc_we;
input [31:0]                     spr_dat_npc;
input                           genpc_refetch;
input                           genpc_freeze;
input                           no_more_dslot;
input                           lsu_stall;
input                           du_flush_pipe;
 
parameter boot_adr = `OR1200_BOOT_ADR;
//
// Internal wires and regs
//
reg     [31:2]                  pcreg_default;
reg                             pcreg_select;
reg     [31:2]                  pcreg;
reg     [31:0]                   pc;
// Set in event of jump or taken branch   
reg                             ex_branch_taken;
reg                             genpc_refetch_r;
reg                             wait_lsu;
 
   //
   // Address of insn to be fecthed
   //
   assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & !du_flush_pipe
                       & (icpu_rty_i | genpc_refetch) ?
                       icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken|spr_pc_we};
 
   //
   // Control access to IC subsystem
   //
   assign icpu_cycstb_o = ~(genpc_freeze | (|pre_branch_op && !icpu_rty_i) | wait_lsu);
   assign icpu_sel_o = 4'b1111;
   assign icpu_tag_o = `OR1200_ITAG_NI;
 
   //
   // wait_lsu
   //
   always @(posedge clk or `OR1200_RST_EVENT rst)
     if (rst == `OR1200_RST_VALUE)
       wait_lsu <=  1'b0;
     else if (!wait_lsu & |pre_branch_op & lsu_stall)
       wait_lsu <=  1'b1;
     else if (wait_lsu & ~|pre_branch_op)
       wait_lsu <=  1'b0;
 
   //
   // genpc_freeze_r
   //
   always @(posedge clk or `OR1200_RST_EVENT rst)
     if (rst == `OR1200_RST_VALUE)
       genpc_refetch_r <=  1'b0;
     else if (genpc_refetch)
       genpc_refetch_r <=  1'b1;
     else
       genpc_refetch_r <=  1'b0;
 
   //
   // Async calculation of new PC value. This value is used for addressing the
   // IC.
   //
   always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type
            or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or
            except_prefix or du_flush_pipe)
     begin
        casez ({du_flush_pipe, spr_pc_we, except_start, branch_op}) // synopsys parallel_case
          {3'b000, `OR1200_BRANCHOP_NOP}: begin
             pc = {pcreg + 30'd1, 2'b0};
             ex_branch_taken = 1'b0;
          end
          {3'b000, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
             // synopsys translate_off
             $display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h"
                      , $time, ex_branch_addrtarget);
             // synopsys translate_on
`endif
             pc = {ex_branch_addrtarget, 2'b00};
             ex_branch_taken = 1'b1;
          end
          {3'b000, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
             // synopsys translate_off
             $display("%t: BRANCHOP_JR: pc <= operand_b %h",
                      $time, operand_b);
             // synopsys translate_on
`endif
             pc = operand_b;
             ex_branch_taken = 1'b1;
          end
          {3'b000, `OR1200_BRANCHOP_BF}:
            if (flag) begin
`ifdef OR1200_VERBOSE
               // synopsys translate_off
               $display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h",
                        $time, ex_branch_addrtarget);
               // synopsys translate_on
`endif
               pc = {ex_branch_addrtarget, 2'b00};
               ex_branch_taken = 1'b1;
            end
            else begin
`ifdef OR1200_VERBOSE
               // synopsys translate_off
               $display("%t: BRANCHOP_BF: not taken", $time);
               // synopsys translate_on
`endif
               pc = {pcreg + 30'd1, 2'b0};
               ex_branch_taken = 1'b0;
            end
          {3'b000, `OR1200_BRANCHOP_BNF}:
            if (flag) begin
`ifdef OR1200_VERBOSE
               // synopsys translate_off
               $display("%t: BRANCHOP_BNF: not taken", $time);
               // synopsys translate_on
`endif
               pc = {pcreg + 30'd1, 2'b0};
               ex_branch_taken = 1'b0;
            end
            else begin
`ifdef OR1200_VERBOSE
               // synopsys translate_off
               $display("%t: BRANCHOP_BNF: pc <= ex_branch_addrtarget %h",
                        $time, ex_branch_addrtarget);
               // synopsys translate_on
`endif
               pc = {ex_branch_addrtarget, 2'b00};
               ex_branch_taken = 1'b1;
            end
          {3'b000, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
             // synopsys translate_off
             $display("%t: BRANCHOP_RFE: pc <= epcr %h",
                      $time, epcr);
             // synopsys translate_on
`endif
             pc = epcr;
             ex_branch_taken = 1'b1;
          end
          {3'b100, 3'b???}: begin
`ifdef OR1200_VERBOSE
             // synopsys translate_off
             $display("Reload breaked ins at : %h.", spr_dat_npc);
             // synopsys translate_on
`endif
             pc = spr_dat_npc;
             ex_branch_taken = 1'b1;
          end
          {3'b001, 3'b???}: begin
`ifdef OR1200_VERBOSE
             // synopsys translate_off
             $display("Starting exception: %h.", except_type);
             // synopsys translate_on
`endif
             pc = {(except_prefix ?
                    `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P),
                   except_type, `OR1200_EXCEPT_V};
             ex_branch_taken = 1'b1;
          end
          default: begin
`ifdef OR1200_VERBOSE
             // synopsys translate_off
             $display("l.mtspr writing into PC: %h.", spr_dat_i);
             // synopsys translate_on
`endif
             pc = spr_dat_i;
             ex_branch_taken = 1'b0;
          end
        endcase
     end
 
   // select async. value for pcreg after reset - PC jumps to the address selected
   // after boot.
   wire [31:0] pcreg_boot = boot_adr;
 
   //
   // PC register
   //
   always @(posedge clk or `OR1200_RST_EVENT rst)
     // default value 
     if (rst == `OR1200_RST_VALUE) begin
        pcreg_default <=  (boot_adr >>2) - 4;
        pcreg_select <=  1'b1;// select async. value due to reset state
     end
   // selected value (different from default) is written into FF after
   // reset state
     else if (pcreg_select) begin
        // dynamic value can only be assigned to FF out of reset! 
        pcreg_default <=  pcreg_boot[31:2];
        pcreg_select <=  1'b0;          // select FF value 
     end
     else if (spr_pc_we) begin
        pcreg_default <=  spr_dat_i[31:2];
     end
     else if (du_flush_pipe | no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i
              & !genpc_refetch) begin
        pcreg_default <=  pc[31:2];
     end
 
   always @(pcreg_boot or pcreg_default or pcreg_select)
     if (pcreg_select)
       // async. value is selected due to reset state 
       pcreg = pcreg_boot[31:2];
     else
       // FF value is selected 2nd clock after reset state 
       pcreg = pcreg_default ;
 
endmodule

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Subversion Repositories an-fpga-implementation-of-low-latency-noc-based-mpsoc

[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [or1200/] [verilog/] [src/] [or1200_genpc.v] - Blame information for rev 38

Line No.	Rev	Author	Line
1	38	alirezamon	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's generate PC ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PC, interface to IC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// $Log: or1200_genpc.v,v $`
45			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
46			`// Major update:`
47			`// Structure reordered and bugs fixed.`
48
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "or1200_defines.v"
53
54			`module or1200_genpc(`
55			`// Clock and reset`
56			`clk, rst,`
57
58			`// External i/f to IC`
59			`icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,`
60			`icpu_rty_i, icpu_adr_i,`
61
62			`// Internal i/f`
63			`pre_branch_op, branch_op, except_type, except_prefix,`
64			`id_branch_addrtarget, ex_branch_addrtarget, muxed_b, operand_b,`
65			`flag, flagforw, ex_branch_taken, except_start,`
66			`epcr, spr_dat_i, spr_pc_we, genpc_refetch,`
67			`genpc_freeze, no_more_dslot, lsu_stall, du_flush_pipe, spr_dat_npc`
68			`);`
69
70			`//`
71			`// I/O`
72			`//`
73
74			`//`
75			`// Clock and reset`
76			`//`
77			`input clk;`
78			`input rst;`
79
80			`//`
81			`// External i/f to IC`
82			`//`
83			`output [31:0] icpu_adr_o;`
84			`output icpu_cycstb_o;`
85			`output [3:0] icpu_sel_o;`
86			`output [3:0] icpu_tag_o;`
87			`input icpu_rty_i;`
88			`input [31:0] icpu_adr_i;`
89
90			`//`
91			`// Internal i/f`
92			`//`
93			input [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op;
94			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
95			input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
96			`input except_prefix;`
97			`input [31:2] id_branch_addrtarget;`
98			`input [31:2] ex_branch_addrtarget;`
99			`input [31:0] muxed_b;`
100			`input [31:0] operand_b;`
101			`input flag;`
102			`input flagforw;`
103			`output ex_branch_taken;`
104			`input except_start;`
105			`input [31:0] epcr;`
106			`input [31:0] spr_dat_i;`
107			`input spr_pc_we;`
108			`input [31:0] spr_dat_npc;`
109			`input genpc_refetch;`
110			`input genpc_freeze;`
111			`input no_more_dslot;`
112			`input lsu_stall;`
113			`input du_flush_pipe;`
114
115			parameter boot_adr = `OR1200_BOOT_ADR;
116			`//`
117			`// Internal wires and regs`
118			`//`
119			`reg [31:2] pcreg_default;`
120			`reg pcreg_select;`
121			`reg [31:2] pcreg;`
122			`reg [31:0] pc;`
123			`// Set in event of jump or taken branch`
124			`reg ex_branch_taken;`
125			`reg genpc_refetch_r;`
126			`reg wait_lsu;`
127
128			`//`
129			`// Address of insn to be fecthed`
130			`//`
131			`assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & !du_flush_pipe`
132			`& (icpu_rty_i \| genpc_refetch) ?`
133			`icpu_adr_i : {pc[31:2], 1'b0, ex_branch_taken\|spr_pc_we};`
134
135			`//`
136			`// Control access to IC subsystem`
137			`//`
138			`assign icpu_cycstb_o = ~(genpc_freeze \| (\|pre_branch_op && !icpu_rty_i) \| wait_lsu);`
139			`assign icpu_sel_o = 4'b1111;`
140			assign icpu_tag_o = `OR1200_ITAG_NI;
141
142			`//`
143			`// wait_lsu`
144			`//`
145			always @(posedge clk or `OR1200_RST_EVENT rst)
146			if (rst == `OR1200_RST_VALUE)
147			`wait_lsu <= 1'b0;`
148			`else if (!wait_lsu & \|pre_branch_op & lsu_stall)`
149			`wait_lsu <= 1'b1;`
150			`else if (wait_lsu & ~\|pre_branch_op)`
151			`wait_lsu <= 1'b0;`
152
153			`//`
154			`// genpc_freeze_r`
155			`//`
156			always @(posedge clk or `OR1200_RST_EVENT rst)
157			if (rst == `OR1200_RST_VALUE)
158			`genpc_refetch_r <= 1'b0;`
159			`else if (genpc_refetch)`
160			`genpc_refetch_r <= 1'b1;`
161			`else`
162			`genpc_refetch_r <= 1'b0;`
163
164			`//`
165			`// Async calculation of new PC value. This value is used for addressing the`
166			`// IC.`
167			`//`
168			`always @(pcreg or ex_branch_addrtarget or flag or branch_op or except_type`
169			`or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or`
170			`except_prefix or du_flush_pipe)`
171			`begin`
172			`casez ({du_flush_pipe, spr_pc_we, except_start, branch_op}) // synopsys parallel_case`
173			{3'b000, `OR1200_BRANCHOP_NOP}: begin
174			`pc = {pcreg + 30'd1, 2'b0};`
175			`ex_branch_taken = 1'b0;`
176			`end`
177			{3'b000, `OR1200_BRANCHOP_J}: begin
178			`ifdef OR1200_VERBOSE
179			`// synopsys translate_off`
180			`$display("%t: BRANCHOP_J: pc <= ex_branch_addrtarget %h"`
181			`, $time, ex_branch_addrtarget);`
182			`// synopsys translate_on`
183			`endif
184			`pc = {ex_branch_addrtarget, 2'b00};`
185			`ex_branch_taken = 1'b1;`
186			`end`
187			{3'b000, `OR1200_BRANCHOP_JR}: begin
188			`ifdef OR1200_VERBOSE
189			`// synopsys translate_off`
190			`$display("%t: BRANCHOP_JR: pc <= operand_b %h",`
191			`$time, operand_b);`
192			`// synopsys translate_on`
193			`endif
194			`pc = operand_b;`
195			`ex_branch_taken = 1'b1;`
196			`end`
197			{3'b000, `OR1200_BRANCHOP_BF}:
198			`if (flag) begin`
199			`ifdef OR1200_VERBOSE
200			`// synopsys translate_off`
201			`$display("%t: BRANCHOP_BF: pc <= ex_branch_addrtarget %h",`
202			`$time, ex_branch_addrtarget);`
203			`// synopsys translate_on`
204			`endif
205			`pc = {ex_branch_addrtarget, 2'b00};`
206			`ex_branch_taken = 1'b1;`
207			`end`
208			`else begin`
209			`ifdef OR1200_VERBOSE
210			`// synopsys translate_off`
211			`$display("%t: BRANCHOP_BF: not taken", $time);`
212			`// synopsys translate_on`
213			`endif
214			`pc = {pcreg + 30'd1, 2'b0};`
215			`ex_branch_taken = 1'b0;`
216			`end`
217			{3'b000, `OR1200_BRANCHOP_BNF}:
218			`if (flag) begin`
219			`ifdef OR1200_VERBOSE
220			`// synopsys translate_off`
221			`$display("%t: BRANCHOP_BNF: not taken", $time);`
222			`// synopsys translate_on`
223			`endif
224			`pc = {pcreg + 30'd1, 2'b0};`
225			`ex_branch_taken = 1'b0;`
226			`end`
227			`else begin`
228			`ifdef OR1200_VERBOSE
229			`// synopsys translate_off`
230			`$display("%t: BRANCHOP_BNF: pc <= ex_branch_addrtarget %h",`
231			`$time, ex_branch_addrtarget);`
232			`// synopsys translate_on`
233			`endif
234			`pc = {ex_branch_addrtarget, 2'b00};`
235			`ex_branch_taken = 1'b1;`
236			`end`
237			{3'b000, `OR1200_BRANCHOP_RFE}: begin
238			`ifdef OR1200_VERBOSE
239			`// synopsys translate_off`
240			`$display("%t: BRANCHOP_RFE: pc <= epcr %h",`
241			`$time, epcr);`
242			`// synopsys translate_on`
243			`endif
244			`pc = epcr;`
245			`ex_branch_taken = 1'b1;`
246			`end`
247			`{3'b100, 3'b???}: begin`
248			`ifdef OR1200_VERBOSE
249			`// synopsys translate_off`
250			`$display("Reload breaked ins at : %h.", spr_dat_npc);`
251			`// synopsys translate_on`
252			`endif
253			`pc = spr_dat_npc;`
254			`ex_branch_taken = 1'b1;`
255			`end`
256			`{3'b001, 3'b???}: begin`
257			`ifdef OR1200_VERBOSE
258			`// synopsys translate_off`
259			`$display("Starting exception: %h.", except_type);`
260			`// synopsys translate_on`
261			`endif
262			`pc = {(except_prefix ?`
263			`OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P),
264			except_type, `OR1200_EXCEPT_V};
265			`ex_branch_taken = 1'b1;`
266			`end`
267			`default: begin`
268			`ifdef OR1200_VERBOSE
269			`// synopsys translate_off`
270			`$display("l.mtspr writing into PC: %h.", spr_dat_i);`
271			`// synopsys translate_on`
272			`endif
273			`pc = spr_dat_i;`
274			`ex_branch_taken = 1'b0;`
275			`end`
276			`endcase`
277			`end`
278
279			`// select async. value for pcreg after reset - PC jumps to the address selected`
280			`// after boot.`
281			`wire [31:0] pcreg_boot = boot_adr;`
282
283			`//`
284			`// PC register`
285			`//`
286			always @(posedge clk or `OR1200_RST_EVENT rst)
287			`// default value`
288			if (rst == `OR1200_RST_VALUE) begin
289			`pcreg_default <= (boot_adr >>2) - 4;`
290			`pcreg_select <= 1'b1;// select async. value due to reset state`
291			`end`
292			`// selected value (different from default) is written into FF after`
293			`// reset state`
294			`else if (pcreg_select) begin`
295			`// dynamic value can only be assigned to FF out of reset!`
296			`pcreg_default <= pcreg_boot[31:2];`
297			`pcreg_select <= 1'b0; // select FF value`
298			`end`
299			`else if (spr_pc_we) begin`
300			`pcreg_default <= spr_dat_i[31:2];`
301			`end`
302			`else if (du_flush_pipe \| no_more_dslot \| except_start \| !genpc_freeze & !icpu_rty_i`
303			`& !genpc_refetch) begin`
304			`pcreg_default <= pc[31:2];`
305			`end`
306
307			`always @(pcreg_boot or pcreg_default or pcreg_select)`
308			`if (pcreg_select)`
309			`// async. value is selected due to reset state`
310			`pcreg = pcreg_boot[31:2];`
311			`else`
312			`// FF value is selected 2nd clock after reset state`
313			`pcreg = pcreg_default ;`
314
315			`endmodule`