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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [or1200/] [verilog/] [src/] [or1200_if.v] - Blame information for rev 38

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's instruction fetch                                  ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  PC, instruction fetch, interface to IC.                     ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_if.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Structure reordered and bugs fixed. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_if(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
 
        // Internal i/f
        if_freeze, if_insn, if_pc, if_flushpipe, saving_if_insn,
        if_stall, no_more_dslot, genpc_refetch, rfe,
        except_itlbmiss, except_immufault, except_ibuserr
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
input   [31:0]                   icpu_dat_i;
input                           icpu_ack_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
input   [3:0]                    icpu_tag_i;
 
//
// Internal i/f
//
input                           if_freeze;
output  [31:0]                   if_insn;
output  [31:0]                   if_pc;
input                           if_flushpipe;
output                          saving_if_insn;
output                          if_stall;
input                           no_more_dslot;
output                          genpc_refetch;
input                           rfe;
output                          except_itlbmiss;
output                          except_immufault;
output                          except_ibuserr;
 
//
// Internal wires and regs
//
wire                    save_insn;
wire                    if_bypass;
reg                     if_bypass_reg;
reg     [31:0]           insn_saved;
reg     [31:0]           addr_saved;
reg     [2:0]            err_saved;
reg                     saved;
 
assign save_insn = (icpu_ack_i | icpu_err_i) & if_freeze & !saved;
assign saving_if_insn = !if_flushpipe & save_insn;
 
//
// IF bypass 
//
assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg | if_flushpipe;
 
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                if_bypass_reg <=  1'b0;
        else
                if_bypass_reg <=  if_bypass;
 
//
// IF stage insn
//
assign if_insn = no_more_dslot | rfe | if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
assign if_pc = saved ? addr_saved : {icpu_adr_i[31:2], 2'h0};
assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
assign genpc_refetch = saved & icpu_ack_i;
assign except_itlbmiss = no_more_dslot ? 1'b0 : saved ? err_saved[0] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
assign except_immufault = no_more_dslot ? 1'b0 : saved ? err_saved[1] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
assign except_ibuserr = no_more_dslot ? 1'b0 : saved ? err_saved[2] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
 
//
// Flag for saved insn/address
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                saved <=  1'b0;
        else if (if_flushpipe)
                saved <=  1'b0;
        else if (save_insn)
                saved <=  1'b1;
        else if (!if_freeze)
                saved <=  1'b0;
 
//
// Store fetched instruction
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (if_flushpipe)
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
        else if (save_insn)
                insn_saved <=  icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
        else if (!if_freeze)
                insn_saved <=  {`OR1200_OR32_NOP, 26'h041_0000};
 
//
// Store fetched instruction's address
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                addr_saved <=  32'h00000000;
        else if (if_flushpipe)
                addr_saved <=  32'h00000000;
        else if (save_insn)
                addr_saved <=  {icpu_adr_i[31:2], 2'b00};
        else if (!if_freeze)
                addr_saved <=  {icpu_adr_i[31:2], 2'b00};
 
//
// Store fetched instruction's error tags 
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                err_saved <=  3'b000;
        else if (if_flushpipe)
                err_saved <=  3'b000;
        else if (save_insn) begin
                err_saved[0] <=  icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
                err_saved[1] <=  icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
                err_saved[2] <=  icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
        end
        else if (!if_freeze)
                err_saved <=  3'b000;
 
 
endmodule

Line No.	Rev	Author	Line
1	38	alirezamon	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's instruction fetch ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PC, instruction fetch, interface to IC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// $Log: or1200_if.v,v $`
45			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
46			`// Major update:`
47			`// Structure reordered and bugs fixed.`
48
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "or1200_defines.v"
53
54			`module or1200_if(`
55			`// Clock and reset`
56			`clk, rst,`
57
58			`// External i/f to IC`
59			`icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,`
60
61			`// Internal i/f`
62			`if_freeze, if_insn, if_pc, if_flushpipe, saving_if_insn,`
63			`if_stall, no_more_dslot, genpc_refetch, rfe,`
64			`except_itlbmiss, except_immufault, except_ibuserr`
65			`);`
66
67			`//`
68			`// I/O`
69			`//`
70
71			`//`
72			`// Clock and reset`
73			`//`
74			`input clk;`
75			`input rst;`
76
77			`//`
78			`// External i/f to IC`
79			`//`
80			`input [31:0] icpu_dat_i;`
81			`input icpu_ack_i;`
82			`input icpu_err_i;`
83			`input [31:0] icpu_adr_i;`
84			`input [3:0] icpu_tag_i;`
85
86			`//`
87			`// Internal i/f`
88			`//`
89			`input if_freeze;`
90			`output [31:0] if_insn;`
91			`output [31:0] if_pc;`
92			`input if_flushpipe;`
93			`output saving_if_insn;`
94			`output if_stall;`
95			`input no_more_dslot;`
96			`output genpc_refetch;`
97			`input rfe;`
98			`output except_itlbmiss;`
99			`output except_immufault;`
100			`output except_ibuserr;`
101
102			`//`
103			`// Internal wires and regs`
104			`//`
105			`wire save_insn;`
106			`wire if_bypass;`
107			`reg if_bypass_reg;`
108			`reg [31:0] insn_saved;`
109			`reg [31:0] addr_saved;`
110			`reg [2:0] err_saved;`
111			`reg saved;`
112
113			`assign save_insn = (icpu_ack_i \| icpu_err_i) & if_freeze & !saved;`
114			`assign saving_if_insn = !if_flushpipe & save_insn;`
115
116			`//`
117			`// IF bypass`
118			`//`
119			`assign if_bypass = icpu_adr_i[0] ? 1'b0 : if_bypass_reg \| if_flushpipe;`
120
121			always @(posedge clk or `OR1200_RST_EVENT rst)
122			if (rst == `OR1200_RST_VALUE)
123			`if_bypass_reg <= 1'b0;`
124			`else`
125			`if_bypass_reg <= if_bypass;`
126
127			`//`
128			`// IF stage insn`
129			`//`
130			assign if_insn = no_more_dslot \| rfe \| if_bypass ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
131			`assign if_pc = saved ? addr_saved : {icpu_adr_i[31:2], 2'h0};`
132			`assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;`
133			`assign genpc_refetch = saved & icpu_ack_i;`
134			assign except_itlbmiss = no_more_dslot ? 1'b0 : saved ? err_saved[0] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
135			assign except_immufault = no_more_dslot ? 1'b0 : saved ? err_saved[1] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
136			assign except_ibuserr = no_more_dslot ? 1'b0 : saved ? err_saved[2] : icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
137
138			`//`
139			`// Flag for saved insn/address`
140			`//`
141			always @(posedge clk or `OR1200_RST_EVENT rst)
142			if (rst == `OR1200_RST_VALUE)
143			`saved <= 1'b0;`
144			`else if (if_flushpipe)`
145			`saved <= 1'b0;`
146			`else if (save_insn)`
147			`saved <= 1'b1;`
148			`else if (!if_freeze)`
149			`saved <= 1'b0;`
150
151			`//`
152			`// Store fetched instruction`
153			`//`
154			always @(posedge clk or `OR1200_RST_EVENT rst)
155			if (rst == `OR1200_RST_VALUE)
156			insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
157			`else if (if_flushpipe)`
158			insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
159			`else if (save_insn)`
160			insn_saved <= icpu_err_i ? {`OR1200_OR32_NOP, 26'h041_0000} : icpu_dat_i;
161			`else if (!if_freeze)`
162			insn_saved <= {`OR1200_OR32_NOP, 26'h041_0000};
163
164			`//`
165			`// Store fetched instruction's address`
166			`//`
167			always @(posedge clk or `OR1200_RST_EVENT rst)
168			if (rst == `OR1200_RST_VALUE)
169			`addr_saved <= 32'h00000000;`
170			`else if (if_flushpipe)`
171			`addr_saved <= 32'h00000000;`
172			`else if (save_insn)`
173			`addr_saved <= {icpu_adr_i[31:2], 2'b00};`
174			`else if (!if_freeze)`
175			`addr_saved <= {icpu_adr_i[31:2], 2'b00};`
176
177			`//`
178			`// Store fetched instruction's error tags`
179			`//`
180			always @(posedge clk or `OR1200_RST_EVENT rst)
181			if (rst == `OR1200_RST_VALUE)
182			`err_saved <= 3'b000;`
183			`else if (if_flushpipe)`
184			`err_saved <= 3'b000;`
185			`else if (save_insn) begin`
186			err_saved[0] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE);
187			err_saved[1] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE);
188			err_saved[2] <= icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE);
189			`end`
190			`else if (!if_freeze)`
191			`err_saved <= 3'b000;`
192
193
194			`endmodule`

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[/] [an-fpga-implementation-of-low-latency-noc-based-mpsoc/] [trunk/] [mpsoc/] [src_processor/] [or1200/] [verilog/] [src/] [or1200_if.v] - Blame information for rev 38