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<title>ao68000: alu Module Reference</title>
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<div class="summary">
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<a href="#Inputs">Inputs</a> |
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<a href="#Outputs">Outputs</a> |
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<a href="#Signals">Signals</a> |
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<a href="#Module Instances">Module Instances</a> |
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<a href="#Defines">Defines</a> |
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<a href="#Always Constructs">Always Constructs</a> </div>
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<div class="headertitle">
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<h1>alu Module Reference</h1> </div>
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</div>
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<div class="contents">
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<!-- doxytag: class="alu" -->
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<p>Arithmetic and Logic Unit.
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<a href="#_details">More...</a></p>
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Inheritance diagram for alu:<!-- endSectionHeader --></div>
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</div><!-- endSectionContent --></div>
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<p><a href="classalu-members.html">List of all members.</a></p>
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<table class="memberdecls">
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<tr><td colspan="2"><h2><a name="Always Constructs"></a>
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Always Constructs</h2></td></tr>
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alfik |
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a833db0d5eda614d712b846b259c0f4d3">ALWAYS_30</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a04b10dc82e8a06c3856bfd16a7e18d06">ALWAYS_31</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td colspan="2"><h2><a name="Defines"></a>
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Defines</h2></td></tr>
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<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">Sm</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand2</span><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand2</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><b><a class="el" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">]</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
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<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">Dm</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand1</span><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand1</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><b><a class="el" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">]</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
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<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#a942f3773659fb9e9e38101743237144a">Rm</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?result</span><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?result</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><b><a class="el" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">]</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
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| 64 |
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<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">Z</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">8'b0</span><span class="vhdlchar">)</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">16'b0</span><span class="vhdlchar">)</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">32'b0</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
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<tr><td colspan="2"><h2><a name="Inputs"></a>
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Inputs</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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| 68 |
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a379cf0ab5b30f07c291e327fc5bb194f">address</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">interrupt_mask</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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| 75 |
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td colspan="2"><h2><a name="Outputs"></a>
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Outputs</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">alu_mult_div_ready</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><h2><a name="Module Instances"></a>
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Module Instances</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classalu.html#a6447478386a93e0306b7cb09937c23c3">lpm_mult::muls</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><h2><a name="Signals"></a>
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Signals</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">16</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">32</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">div_overflow</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a> </td></tr>
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| 95 |
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">div_remainder</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">33</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a> </td></tr>
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| 97 |
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> </td></tr>
|
| 99 |
12 |
alfik |
</table>
|
| 100 |
|
|
<hr/><a name="_details"></a><h2>Detailed Description</h2>
|
| 101 |
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|
<p>Arithmetic and Logic Unit. </p>
|
| 102 |
|
|
<p>The alu module is responsible for performing all of the arithmetic and logic operations of the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> processor. It operates on two 32-bit registers: operand1 and operand2 from the registers module. The output is saved into a result 32-bit register. This register is located in the alu module.</p>
|
| 103 |
|
|
<p>The alu module also contains the status register (SR) with the condition code register. The microcode decides what operation the alu performs. </p>
|
| 104 |
|
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|
| 105 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02591">2591</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 106 |
12 |
alfik |
<hr/><h2>Member Function Documentation</h2>
|
| 107 |
|
|
<a class="anchor" id="a833db0d5eda614d712b846b259c0f4d3"></a><!-- doxytag: member="alu::ALWAYS_30" ref="a833db0d5eda614d712b846b259c0f4d3" args="clock, reset_n" -->
|
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|
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<div class="memitem">
|
| 109 |
|
|
<div class="memproto">
|
| 110 |
|
|
<table class="memname">
|
| 111 |
|
|
<tr>
|
| 112 |
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|
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_30 <td></td>
|
| 113 |
13 |
alfik |
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
|
| 114 |
12 |
alfik |
</tr>
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|
<tr>
|
| 116 |
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|
<td class="paramkey"></td>
|
| 117 |
|
|
<td></td>
|
| 118 |
13 |
alfik |
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
|
| 119 |
12 |
alfik |
</tr>
|
| 120 |
|
|
<code> [Always Construct]</code></td>
|
| 121 |
|
|
</tr>
|
| 122 |
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</table>
|
| 123 |
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|
</div>
|
| 124 |
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<div class="memdoc">
|
| 125 |
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|
| 126 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02652">2652</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 127 |
12 |
alfik |
<div class="fragment"><pre class="fragment">
|
| 128 |
13 |
alfik |
<a name="l02652"></a>02652 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 129 |
|
|
<a name="l02653"></a>02653 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 130 |
|
|
<a name="l02654"></a>02654 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <span class="vhdllogic">5'd0</span>;
|
| 131 |
|
|
<a name="l02655"></a>02655 <span class="vhdlkeyword">end</span>
|
| 132 |
|
|
<a name="l02656"></a>02656 <span class="keyword">// Cycle #0 : load the registers</span>
|
| 133 |
|
|
<a name="l02657"></a>02657 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a> == <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd0</span>) <span class="vhdlkeyword">begin</span>
|
| 134 |
|
|
<a name="l02658"></a>02658 <span class="keyword">// 17 cycles to finish + wait state</span>
|
| 135 |
|
|
<a name="l02659"></a>02659 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <span class="vhdllogic">5'd18</span>;
|
| 136 |
|
|
<a name="l02660"></a>02660 <span class="keyword">// Clear the quotient</span>
|
| 137 |
|
|
<a name="l02661"></a>02661 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= <span class="vhdllogic">17'd0</span>;
|
| 138 |
|
|
<a name="l02662"></a>02662
|
| 139 |
|
|
<a name="l02663"></a>02663 <span class="keyword">// Unsigned divide or positive numerator</span>
|
| 140 |
|
|
<a name="l02664"></a>02664 <span class="vhdlkeyword">if</span> ((!<a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) || (!<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>])) <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 141 |
|
|
<a name="l02665"></a>02665 <span class="keyword">// Negative numerator</span>
|
| 142 |
|
|
<a name="l02666"></a>02666 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= -<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 143 |
|
|
<a name="l02667"></a>02667
|
| 144 |
|
|
<a name="l02668"></a>02668 <span class="keyword">// Unsigned divide or positive denominator</span>
|
| 145 |
|
|
<a name="l02669"></a>02669 <span class="vhdlkeyword">if</span> ((!<a class="code" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a>) || (!<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>])) <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>],<span class="vhdllogic">16'd0</span>};
|
| 146 |
|
|
<a name="l02670"></a>02670 <span class="keyword">// Negative denominator</span>
|
| 147 |
|
|
<a name="l02671"></a>02671 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {-<a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>],<span class="vhdllogic">16'd0</span>};
|
| 148 |
|
|
<a name="l02672"></a>02672 <span class="vhdlkeyword">end</span>
|
| 149 |
|
|
<a name="l02673"></a>02673 <span class="keyword">// Cycles #1-17 : division calculation</span>
|
| 150 |
|
|
<a name="l02674"></a>02674 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> > <span class="vhdllogic">5'd1</span>) <span class="vhdlkeyword">begin</span>
|
| 151 |
|
|
<a name="l02675"></a>02675 <span class="keyword">// Check difference's sign</span>
|
| 152 |
|
|
<a name="l02676"></a>02676 <span class="vhdlkeyword">if</span> (!<a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a>[<span class="vhdllogic">32</span>]) <span class="vhdlkeyword">begin</span>
|
| 153 |
|
|
<a name="l02677"></a>02677 <span class="keyword">// Difference is positive : shift a one</span>
|
| 154 |
|
|
<a name="l02678"></a>02678 <a class="code" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a> <= <a class="code" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 155 |
|
|
<a name="l02679"></a>02679 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= {<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b1</span>};
|
| 156 |
|
|
<a name="l02680"></a>02680 <span class="vhdlkeyword">end</span>
|
| 157 |
|
|
<a name="l02681"></a>02681 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 158 |
|
|
<a name="l02682"></a>02682 <span class="keyword">// Difference is negative : shift a zero</span>
|
| 159 |
|
|
<a name="l02683"></a>02683 <a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a> <= {<a class="code" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
| 160 |
|
|
<a name="l02684"></a>02684 <span class="vhdlkeyword">end</span>
|
| 161 |
|
|
<a name="l02685"></a>02685 <span class="keyword">// Shift right divider</span>
|
| 162 |
|
|
<a name="l02686"></a>02686 <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a> <= {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>]};
|
| 163 |
|
|
<a name="l02687"></a>02687 <span class="keyword">// Count one bit</span>
|
| 164 |
|
|
<a name="l02688"></a>02688 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> - <span class="vhdllogic">5'd1</span>;
|
| 165 |
|
|
<a name="l02689"></a>02689 <span class="vhdlkeyword">end</span>
|
| 166 |
|
|
<a name="l02690"></a>02690 <span class="keyword">// result read</span>
|
| 167 |
|
|
<a name="l02691"></a>02691 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a> == <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd1</span>) <span class="vhdlkeyword">begin</span>
|
| 168 |
|
|
<a name="l02692"></a>02692 <span class="keyword">// goto idle</span>
|
| 169 |
|
|
<a name="l02693"></a>02693 <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> <= <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> - <span class="vhdllogic">5'd1</span>;
|
| 170 |
|
|
<a name="l02694"></a>02694 <span class="vhdlkeyword">end</span>
|
| 171 |
|
|
<a name="l02695"></a>02695 <span class="vhdlkeyword">end</span>
|
| 172 |
|
|
</pre></div>
|
| 173 |
|
|
</div>
|
| 174 |
|
|
</div>
|
| 175 |
|
|
<a class="anchor" id="a04b10dc82e8a06c3856bfd16a7e18d06"></a><!-- doxytag: member="alu::ALWAYS_31" ref="a04b10dc82e8a06c3856bfd16a7e18d06" args="clock, reset_n" -->
|
| 176 |
|
|
<div class="memitem">
|
| 177 |
|
|
<div class="memproto">
|
| 178 |
|
|
<table class="memname">
|
| 179 |
|
|
<tr>
|
| 180 |
|
|
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_31 <td></td>
|
| 181 |
|
|
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
|
| 182 |
|
|
</tr>
|
| 183 |
|
|
<tr>
|
| 184 |
|
|
<td class="paramkey"></td>
|
| 185 |
|
|
<td></td>
|
| 186 |
|
|
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
|
| 187 |
|
|
</tr>
|
| 188 |
|
|
<code> [Always Construct]</code></td>
|
| 189 |
|
|
</tr>
|
| 190 |
|
|
</table>
|
| 191 |
|
|
</div>
|
| 192 |
|
|
<div class="memdoc">
|
| 193 |
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|
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| 194 |
|
|
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02807">2807</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 195 |
|
|
<div class="fragment"><pre class="fragment">
|
| 196 |
|
|
<a name="l02807"></a>02807 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 197 |
|
|
<a name="l02808"></a>02808 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 198 |
|
|
<a name="l02809"></a>02809 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <span class="vhdllogic">1'b0</span>, <span class="vhdllogic">1'b1</span>, <span class="vhdllogic">2'b0</span>, <span class="vhdllogic">3'b111</span>, <span class="vhdllogic">8'b0</span> };
|
| 199 |
|
|
<a name="l02810"></a>02810 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <span class="vhdllogic">32'd0</span>;
|
| 200 |
|
|
<a name="l02811"></a>02811 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 201 |
|
|
<a name="l02812"></a>02812 <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a> <= <span class="vhdllogic">3'b0</span>;
|
| 202 |
|
|
<a name="l02813"></a>02813 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b0</span>;
|
| 203 |
|
|
<a name="l02814"></a>02814 <span class="vhdlkeyword">end</span>
|
| 204 |
|
|
<a name="l02815"></a>02815 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 205 |
|
|
<a name="l02816"></a>02816 <span class="vhdlkeyword">case</span>(<a class="code" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a>)
|
| 206 |
|
|
<a name="l02817"></a>02817 <a class="code" href="ao68000_8v.html#a687e6310453b4cedb64aa6e66b058c18">`ALU_SR_SET_INTERRUPT</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 207 |
|
|
<a name="l02818"></a>02818 <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a> <= <a class="code" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">interrupt_mask</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
|
| 208 |
|
|
<a name="l02819"></a>02819 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b1</span>;
|
| 209 |
|
|
<a name="l02820"></a>02820 <span class="vhdlkeyword">end</span>
|
| 210 |
|
|
<a name="l02821"></a>02821
|
| 211 |
|
|
<a name="l02822"></a>02822 <a class="code" href="ao68000_8v.html#ac9fc44b8d3bbcd6c742f1ba074fc668d">`ALU_SR_SET_TRAP</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 212 |
|
|
<a name="l02823"></a>02823 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 213 |
|
|
<a name="l02824"></a>02824 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">14</span>], <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">12</span>:<span class="vhdllogic">11</span>], <a class="code" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 214 |
|
|
<a name="l02825"></a>02825 <span class="vhdlkeyword">end</span>
|
| 215 |
|
|
<a name="l02826"></a>02826 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 216 |
|
|
<a name="l02827"></a>02827 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">14</span>], <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">12</span>:<span class="vhdllogic">0</span>] };
|
| 217 |
|
|
<a name="l02828"></a>02828 <span class="vhdlkeyword">end</span>
|
| 218 |
|
|
<a name="l02829"></a>02829 <a class="code" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a> <= <span class="vhdllogic">1'b0</span>;
|
| 219 |
|
|
<a name="l02830"></a>02830 <span class="vhdlkeyword">end</span>
|
| 220 |
|
|
<a name="l02831"></a>02831
|
| 221 |
|
|
<a name="l02832"></a>02832 <a class="code" href="ao68000_8v.html#a59147ff996e0ba496f1f06d7a06decae">`ALU_MOVEP_M2R_1</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 222 |
|
|
<a name="l02833"></a>02833 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 223 |
|
|
<a name="l02834"></a>02834 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 224 |
|
|
<a name="l02835"></a>02835 <span class="keyword">//CCR: no change</span>
|
| 225 |
|
|
<a name="l02836"></a>02836 <span class="vhdlkeyword">end</span>
|
| 226 |
|
|
<a name="l02837"></a>02837 <a class="code" href="ao68000_8v.html#a3b1155f3496b0fc984e5418e09586bf5">`ALU_MOVEP_M2R_2</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 227 |
|
|
<a name="l02838"></a>02838 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 228 |
|
|
<a name="l02839"></a>02839 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 229 |
|
|
<a name="l02840"></a>02840 <span class="keyword">//CCR: no change</span>
|
| 230 |
|
|
<a name="l02841"></a>02841 <span class="vhdlkeyword">end</span>
|
| 231 |
|
|
<a name="l02842"></a>02842 <a class="code" href="ao68000_8v.html#a5458c8548afc8f7517bdc582c9946b2f">`ALU_MOVEP_M2R_3</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 232 |
|
|
<a name="l02843"></a>02843 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 233 |
|
|
<a name="l02844"></a>02844 <span class="keyword">//CCR: no change</span>
|
| 234 |
|
|
<a name="l02845"></a>02845 <span class="vhdlkeyword">end</span>
|
| 235 |
|
|
<a name="l02846"></a>02846 <a class="code" href="ao68000_8v.html#a8ec0074ca9c5cfec15aa93b92353e09b">`ALU_MOVEP_M2R_4</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 236 |
|
|
<a name="l02847"></a>02847 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 237 |
|
|
<a name="l02848"></a>02848 <span class="keyword">//CCR: no change</span>
|
| 238 |
|
|
<a name="l02849"></a>02849 <span class="vhdlkeyword">end</span>
|
| 239 |
|
|
<a name="l02850"></a>02850
|
| 240 |
|
|
<a name="l02851"></a>02851
|
| 241 |
|
|
<a name="l02852"></a>02852 <a class="code" href="ao68000_8v.html#aab7548aba43c6c12259a2a154ce2982b">`ALU_MOVEP_R2M_1</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 242 |
|
|
<a name="l02853"></a>02853 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>];
|
| 243 |
|
|
<a name="l02854"></a>02854 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>];
|
| 244 |
|
|
<a name="l02855"></a>02855 <span class="keyword">// CCR: no change</span>
|
| 245 |
|
|
<a name="l02856"></a>02856 <span class="vhdlkeyword">end</span>
|
| 246 |
|
|
<a name="l02857"></a>02857 <a class="code" href="ao68000_8v.html#a9918f4663f481092da549f3cb008721d">`ALU_MOVEP_R2M_2</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 247 |
|
|
<a name="l02858"></a>02858 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>];
|
| 248 |
|
|
<a name="l02859"></a>02859 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 249 |
|
|
<a name="l02860"></a>02860 <span class="keyword">// CCR: no change</span>
|
| 250 |
|
|
<a name="l02861"></a>02861 <span class="vhdlkeyword">end</span>
|
| 251 |
|
|
<a name="l02862"></a>02862 <a class="code" href="ao68000_8v.html#aee5fc91f58c97ffa4d252e127c9e4226">`ALU_MOVEP_R2M_3</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 252 |
|
|
<a name="l02863"></a>02863 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>];
|
| 253 |
|
|
<a name="l02864"></a>02864 <span class="keyword">// CCR: no change</span>
|
| 254 |
|
|
<a name="l02865"></a>02865 <span class="vhdlkeyword">end</span>
|
| 255 |
|
|
<a name="l02866"></a>02866 <a class="code" href="ao68000_8v.html#a0bc85184fda7b9fcbf00afa29be91d42">`ALU_MOVEP_R2M_4</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 256 |
|
|
<a name="l02867"></a>02867 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 257 |
|
|
<a name="l02868"></a>02868 <span class="keyword">// CCR: no change</span>
|
| 258 |
|
|
<a name="l02869"></a>02869 <span class="vhdlkeyword">end</span>
|
| 259 |
|
|
<a name="l02870"></a>02870
|
| 260 |
|
|
<a name="l02871"></a>02871
|
| 261 |
|
|
<a name="l02872"></a>02872
|
| 262 |
|
|
<a name="l02873"></a>02873 <a class="code" href="ao68000_8v.html#a6a119b7268e4e0a78e0307ba0c693ccb">`ALU_SIGN_EXTEND</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 263 |
|
|
<a name="l02874"></a>02874 <span class="keyword">// move operand1 with sign-extension to result</span>
|
| 264 |
|
|
<a name="l02875"></a>02875 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 265 |
|
|
<a name="l02876"></a>02876 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
| 266 |
|
|
<a name="l02877"></a>02877 <span class="vhdlkeyword">end</span>
|
| 267 |
|
|
<a name="l02878"></a>02878 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 268 |
|
|
<a name="l02879"></a>02879 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 269 |
|
|
<a name="l02880"></a>02880 <span class="vhdlkeyword">end</span>
|
| 270 |
|
|
<a name="l02881"></a>02881 <span class="keyword">// CCR: no change</span>
|
| 271 |
|
|
<a name="l02882"></a>02882 <span class="vhdlkeyword">end</span>
|
| 272 |
|
|
<a name="l02883"></a>02883
|
| 273 |
|
|
<a name="l02884"></a>02884 <a class="code" href="ao68000_8v.html#ae497ab0b3e0550245c333bdb426d4236">`ALU_ARITHMETIC_LOGIC</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 274 |
|
|
<a name="l02885"></a>02885
|
| 275 |
|
|
<a name="l02886"></a>02886 <span class="keyword">// OR,OR to mem,OR to Dn</span>
|
| 276 |
|
|
<a name="l02887"></a>02887 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b000</span>) ||
|
| 277 |
|
|
<a name="l02888"></a>02888 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span>)
|
| 278 |
|
|
<a name="l02889"></a>02889 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] | <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 279 |
|
|
<a name="l02890"></a>02890 <span class="keyword">// AND,AND to mem,AND to Dn</span>
|
| 280 |
|
|
<a name="l02891"></a>02891 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b001</span>) ||
|
| 281 |
|
|
<a name="l02892"></a>02892 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span>)
|
| 282 |
|
|
<a name="l02893"></a>02893 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] & <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 283 |
|
|
<a name="l02894"></a>02894 <span class="keyword">// EORI,EOR</span>
|
| 284 |
|
|
<a name="l02895"></a>02895 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b101</span>) ||
|
| 285 |
|
|
<a name="l02896"></a>02896 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b001</span>)
|
| 286 |
|
|
<a name="l02897"></a>02897 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] ^ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 287 |
|
|
<a name="l02898"></a>02898 <span class="keyword">// ADD,ADD to mem,ADD to Dn,ADDQ</span>
|
| 288 |
|
|
<a name="l02899"></a>02899 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b011</span>) ||
|
| 289 |
|
|
<a name="l02900"></a>02900 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span>) ||
|
| 290 |
|
|
<a name="l02901"></a>02901 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>)
|
| 291 |
|
|
<a name="l02902"></a>02902 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 292 |
|
|
<a name="l02903"></a>02903 <span class="keyword">// SUBI,CMPI,CMPM,SUB to mem,SUB to Dn,CMP,SUBQ</span>
|
| 293 |
|
|
<a name="l02904"></a>02904 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b010</span>) ||
|
| 294 |
|
|
<a name="l02905"></a>02905 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b110</span>) ||
|
| 295 |
|
|
<a name="l02906"></a>02906 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span>) ||
|
| 296 |
|
|
<a name="l02907"></a>02907 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) ||
|
| 297 |
|
|
<a name="l02908"></a>02908 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>)) ||
|
| 298 |
|
|
<a name="l02909"></a>02909 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>)
|
| 299 |
|
|
<a name="l02910"></a>02910 ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 300 |
|
|
<a name="l02911"></a>02911
|
| 301 |
|
|
<a name="l02912"></a>02912 <span class="keyword">// Z</span>
|
| 302 |
|
|
<a name="l02913"></a>02913 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 303 |
|
|
<a name="l02914"></a>02914 <span class="keyword">// N</span>
|
| 304 |
|
|
<a name="l02915"></a>02915 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 305 |
|
|
<a name="l02916"></a>02916
|
| 306 |
|
|
<a name="l02917"></a>02917 <span class="keyword">// CMPI,CMPM,CMP</span>
|
| 307 |
|
|
<a name="l02918"></a>02918 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b110</span>) ||
|
| 308 |
|
|
<a name="l02919"></a>02919 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b101</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b110</span>) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b001</span>) ||
|
| 309 |
|
|
<a name="l02920"></a>02920 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> && (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b000</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">3'b010</span>))
|
| 310 |
|
|
<a name="l02921"></a>02921 ) <span class="vhdlkeyword">begin</span>
|
| 311 |
|
|
<a name="l02922"></a>02922 <span class="keyword">// C,V</span>
|
| 312 |
|
|
<a name="l02923"></a>02923 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 313 |
|
|
<a name="l02924"></a>02924 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 314 |
|
|
<a name="l02925"></a>02925 <span class="keyword">// X not affected</span>
|
| 315 |
|
|
<a name="l02926"></a>02926 <span class="vhdlkeyword">end</span>
|
| 316 |
|
|
<a name="l02927"></a>02927 <span class="keyword">// ADDI,ADD to mem,ADD to Dn,ADDQ</span>
|
| 317 |
|
|
<a name="l02928"></a>02928 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b011</span>) ||
|
| 318 |
|
|
<a name="l02929"></a>02929 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span>) ||
|
| 319 |
|
|
<a name="l02930"></a>02930 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>)
|
| 320 |
|
|
<a name="l02931"></a>02931 ) <span class="vhdlkeyword">begin</span>
|
| 321 |
|
|
<a name="l02932"></a>02932 <span class="keyword">// C,X,V</span>
|
| 322 |
|
|
<a name="l02933"></a>02933 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 323 |
|
|
<a name="l02934"></a>02934 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 324 |
|
|
<a name="l02935"></a>02935 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 325 |
|
|
<a name="l02936"></a>02936 <span class="vhdlkeyword">end</span>
|
| 326 |
|
|
<a name="l02937"></a>02937 <span class="keyword">// SUBI,SUB to mem,SUB to Dn,SUBQ</span>
|
| 327 |
|
|
<a name="l02938"></a>02938 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0000</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">3'b010</span>) ||
|
| 328 |
|
|
<a name="l02939"></a>02939 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span>) ||
|
| 329 |
|
|
<a name="l02940"></a>02940 (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>)
|
| 330 |
|
|
<a name="l02941"></a>02941 ) <span class="vhdlkeyword">begin</span>
|
| 331 |
|
|
<a name="l02942"></a>02942 <span class="keyword">// C,X,V</span>
|
| 332 |
|
|
<a name="l02943"></a>02943 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 333 |
|
|
<a name="l02944"></a>02944 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 334 |
|
|
<a name="l02945"></a>02945 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 335 |
12 |
alfik |
<a name="l02946"></a>02946 <span class="vhdlkeyword">end</span>
|
| 336 |
13 |
alfik |
<a name="l02947"></a>02947 <span class="keyword">// ANDI,EORI,ORI,EOR,OR to mem,AND to mem,OR to Dn,AND to Dn</span>
|
| 337 |
|
|
<a name="l02948"></a>02948 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 338 |
|
|
<a name="l02949"></a>02949 <span class="keyword">// C,V</span>
|
| 339 |
|
|
<a name="l02950"></a>02950 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 340 |
|
|
<a name="l02951"></a>02951 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 341 |
|
|
<a name="l02952"></a>02952 <span class="keyword">// X not affected</span>
|
| 342 |
|
|
<a name="l02953"></a>02953 <span class="vhdlkeyword">end</span>
|
| 343 |
|
|
<a name="l02954"></a>02954 <span class="vhdlkeyword">end</span>
|
| 344 |
|
|
<a name="l02955"></a>02955
|
| 345 |
|
|
<a name="l02956"></a>02956 <a class="code" href="ao68000_8v.html#a3e54001e73374bd4f7cfda3de55bd944">`ALU_ABCD_SBCD_ADDX_SUBX</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span> <span class="keyword">// 259 LE</span>
|
| 346 |
|
|
<a name="l02957"></a>02957 <span class="keyword">// ABCD</span>
|
| 347 |
|
|
<a name="l02958"></a>02958 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b100</span> ) <span class="vhdlkeyword">begin</span>
|
| 348 |
|
|
<a name="l02959"></a>02959 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} + {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} + {<span class="vhdllogic">4'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
| 349 |
|
|
<a name="l02960"></a>02960 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]} + {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]};
|
| 350 |
|
|
<a name="l02961"></a>02961
|
| 351 |
|
|
<a name="l02962"></a>02962 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">23</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] + {<span class="vhdllogic">7'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
| 352 |
|
|
<a name="l02963"></a>02963
|
| 353 |
|
|
<a name="l02964"></a>02964 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'd9</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] + <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>];
|
| 354 |
|
|
<a name="l02965"></a>02965 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'h1F</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd2</span>) :
|
| 355 |
|
|
<a name="l02966"></a>02966 (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'h0F</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd1</span>) :
|
| 356 |
|
|
<a name="l02967"></a>02967 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 357 |
|
|
<a name="l02968"></a>02968 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 358 |
|
|
<a name="l02969"></a>02969
|
| 359 |
|
|
<a name="l02970"></a>02970 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">17</span>:<span class="vhdllogic">14</span>];
|
| 360 |
|
|
<a name="l02971"></a>02971 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>];
|
| 361 |
|
|
<a name="l02972"></a>02972
|
| 362 |
|
|
<a name="l02973"></a>02973 <span class="keyword">// C</span>
|
| 363 |
|
|
<a name="l02974"></a>02974 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 364 |
|
|
<a name="l02975"></a>02975 <span class="keyword">// X = C</span>
|
| 365 |
|
|
<a name="l02976"></a>02976 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 366 |
|
|
<a name="l02977"></a>02977
|
| 367 |
|
|
<a name="l02978"></a>02978 <span class="keyword">// V</span>
|
| 368 |
|
|
<a name="l02979"></a>02979 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">30</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 369 |
|
|
<a name="l02980"></a>02980 <span class="vhdlkeyword">end</span>
|
| 370 |
|
|
<a name="l02981"></a>02981 <span class="keyword">// SBCD</span>
|
| 371 |
|
|
<a name="l02982"></a>02982 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
| 372 |
|
|
<a name="l02983"></a>02983
|
| 373 |
|
|
<a name="l02984"></a>02984 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = <span class="vhdllogic">6'd32</span> + {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} - {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} - {<span class="vhdllogic">5'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
| 374 |
|
|
<a name="l02985"></a>02985 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = <span class="vhdllogic">6'd32</span> + {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]} - {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]};
|
| 375 |
|
|
<a name="l02986"></a>02986
|
| 376 |
|
|
<a name="l02987"></a>02987 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">23</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] - {<span class="vhdllogic">7'b0</span>, <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
| 377 |
|
|
<a name="l02988"></a>02988
|
| 378 |
|
|
<a name="l02989"></a>02989 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd32</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] - <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>];
|
| 379 |
|
|
<a name="l02990"></a>02990 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd16</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd2</span>) :
|
| 380 |
|
|
<a name="l02991"></a>02991 (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd32</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd1</span>) :
|
| 381 |
|
|
<a name="l02992"></a>02992 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 382 |
|
|
<a name="l02993"></a>02993 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>] == <span class="vhdllogic">1'b1</span>) ? (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 383 |
|
|
<a name="l02994"></a>02994
|
| 384 |
|
|
<a name="l02995"></a>02995 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">17</span>:<span class="vhdllogic">14</span>];
|
| 385 |
|
|
<a name="l02996"></a>02996 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>];
|
| 386 |
|
|
<a name="l02997"></a>02997
|
| 387 |
|
|
<a name="l02998"></a>02998 <span class="keyword">// C</span>
|
| 388 |
|
|
<a name="l02999"></a>02999 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 389 |
|
|
<a name="l03000"></a>03000 <span class="keyword">// X = C</span>
|
| 390 |
|
|
<a name="l03001"></a>03001 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 391 |
|
|
<a name="l03002"></a>03002
|
| 392 |
|
|
<a name="l03003"></a>03003 <span class="keyword">// V</span>
|
| 393 |
|
|
<a name="l03004"></a>03004 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">30</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 394 |
|
|
<a name="l03005"></a>03005 <span class="vhdlkeyword">end</span>
|
| 395 |
|
|
<a name="l03006"></a>03006 <span class="keyword">// ADDX</span>
|
| 396 |
|
|
<a name="l03007"></a>03007 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b101</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
| 397 |
|
|
<a name="l03008"></a>03008 <span class="keyword">// SUBX</span>
|
| 398 |
|
|
<a name="l03009"></a>03009 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b001</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
| 399 |
12 |
alfik |
<a name="l03010"></a>03010
|
| 400 |
13 |
alfik |
<a name="l03011"></a>03011 <span class="keyword">// Z</span>
|
| 401 |
|
|
<a name="l03012"></a>03012 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 402 |
|
|
<a name="l03013"></a>03013 <span class="keyword">// N</span>
|
| 403 |
|
|
<a name="l03014"></a>03014 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 404 |
|
|
<a name="l03015"></a>03015
|
| 405 |
|
|
<a name="l03016"></a>03016 <span class="keyword">// ADDX</span>
|
| 406 |
|
|
<a name="l03017"></a>03017 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b101</span> ) <span class="vhdlkeyword">begin</span>
|
| 407 |
|
|
<a name="l03018"></a>03018 <span class="keyword">// C,X,V</span>
|
| 408 |
|
|
<a name="l03019"></a>03019 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 409 |
|
|
<a name="l03020"></a>03020 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 410 |
|
|
<a name="l03021"></a>03021 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 411 |
|
|
<a name="l03022"></a>03022 <span class="vhdlkeyword">end</span>
|
| 412 |
|
|
<a name="l03023"></a>03023 <span class="keyword">// SUBX</span>
|
| 413 |
|
|
<a name="l03024"></a>03024 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b001</span> ) <span class="vhdlkeyword">begin</span>
|
| 414 |
|
|
<a name="l03025"></a>03025 <span class="keyword">// C,X,V</span>
|
| 415 |
|
|
<a name="l03026"></a>03026 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 416 |
|
|
<a name="l03027"></a>03027 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 417 |
|
|
<a name="l03028"></a>03028 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 418 |
|
|
<a name="l03029"></a>03029 <span class="vhdlkeyword">end</span>
|
| 419 |
|
|
<a name="l03030"></a>03030 <span class="vhdlkeyword">end</span>
|
| 420 |
|
|
<a name="l03031"></a>03031
|
| 421 |
|
|
<a name="l03032"></a>03032 <a class="code" href="ao68000_8v.html#ac444f659b2726fd335e839dfadabbfe3">`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 422 |
|
|
<a name="l03033"></a>03033
|
| 423 |
|
|
<a name="l03034"></a>03034 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 424 |
|
|
<a name="l03035"></a>03035 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
| 425 |
|
|
<a name="l03036"></a>03036 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 426 |
12 |
alfik |
<a name="l03037"></a>03037
|
| 427 |
13 |
alfik |
<a name="l03038"></a>03038 <span class="keyword">// X for ASL</span>
|
| 428 |
|
|
<a name="l03039"></a>03039 <span class="keyword">//if(operand2[5:0] > 6'b0 && ir[8] == 1'b1 && ((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) ) begin</span>
|
| 429 |
|
|
<a name="l03040"></a>03040 <span class="keyword">// X set to Dm</span>
|
| 430 |
|
|
<a name="l03041"></a>03041 <span class="keyword">// sr[4] <= `Dm;</span>
|
| 431 |
|
|
<a name="l03042"></a>03042 <span class="keyword">//end</span>
|
| 432 |
|
|
<a name="l03043"></a>03043 <span class="keyword">// else X not affected</span>
|
| 433 |
|
|
<a name="l03044"></a>03044
|
| 434 |
|
|
<a name="l03045"></a>03045 <span class="keyword">// V cleared</span>
|
| 435 |
|
|
<a name="l03046"></a>03046 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 436 |
|
|
<a name="l03047"></a>03047 <span class="keyword">// C for ROXL,ROXR: set to X</span>
|
| 437 |
|
|
<a name="l03048"></a>03048 <span class="vhdlkeyword">if</span>( (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>) ) <span class="vhdlkeyword">begin</span>
|
| 438 |
|
|
<a name="l03049"></a>03049 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>];
|
| 439 |
|
|
<a name="l03050"></a>03050 <span class="vhdlkeyword">end</span>
|
| 440 |
|
|
<a name="l03051"></a>03051 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 441 |
|
|
<a name="l03052"></a>03052 <span class="keyword">// C cleared</span>
|
| 442 |
|
|
<a name="l03053"></a>03053 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 443 |
|
|
<a name="l03054"></a>03054 <span class="vhdlkeyword">end</span>
|
| 444 |
|
|
<a name="l03055"></a>03055
|
| 445 |
|
|
<a name="l03056"></a>03056 <span class="keyword">// N set</span>
|
| 446 |
|
|
<a name="l03057"></a>03057 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 447 |
|
|
<a name="l03058"></a>03058 <span class="keyword">// Z set</span>
|
| 448 |
|
|
<a name="l03059"></a>03059 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 449 |
|
|
<a name="l03060"></a>03060 <span class="vhdlkeyword">end</span>
|
| 450 |
|
|
<a name="l03061"></a>03061
|
| 451 |
|
|
<a name="l03062"></a>03062 <a class="code" href="ao68000_8v.html#ac946f278d039868214c441c11fcf2587">`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 452 |
|
|
<a name="l03063"></a>03063
|
| 453 |
|
|
<a name="l03064"></a>03064 <span class="keyword">// ASL</span>
|
| 454 |
|
|
<a name="l03065"></a>03065 <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b00</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b00</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 455 |
|
|
<a name="l03066"></a>03066 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
| 456 |
|
|
<a name="l03067"></a>03067
|
| 457 |
|
|
<a name="l03068"></a>03068 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b0</span>)? (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> != <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) : <span class="vhdllogic">1'b1</span>; <span class="keyword">// V</span>
|
| 458 |
|
|
<a name="l03069"></a>03069 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
| 459 |
|
|
<a name="l03070"></a>03070 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
| 460 |
|
|
<a name="l03071"></a>03071 <span class="vhdlkeyword">end</span>
|
| 461 |
|
|
<a name="l03072"></a>03072 <span class="keyword">// LSL</span>
|
| 462 |
|
|
<a name="l03073"></a>03073 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b01</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b01</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 463 |
|
|
<a name="l03074"></a>03074 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
| 464 |
|
|
<a name="l03075"></a>03075
|
| 465 |
|
|
<a name="l03076"></a>03076 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 466 |
|
|
<a name="l03077"></a>03077 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
| 467 |
|
|
<a name="l03078"></a>03078 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
| 468 |
|
|
<a name="l03079"></a>03079 <span class="vhdlkeyword">end</span>
|
| 469 |
|
|
<a name="l03080"></a>03080 <span class="keyword">// ROL</span>
|
| 470 |
|
|
<a name="l03081"></a>03081 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b11</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 471 |
|
|
<a name="l03082"></a>03082 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>};
|
| 472 |
12 |
alfik |
<a name="l03083"></a>03083
|
| 473 |
13 |
alfik |
<a name="l03084"></a>03084 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 474 |
|
|
<a name="l03085"></a>03085 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
| 475 |
|
|
<a name="l03086"></a>03086 <span class="keyword">// X not affected</span>
|
| 476 |
|
|
<a name="l03087"></a>03087 <span class="vhdlkeyword">end</span>
|
| 477 |
|
|
<a name="l03088"></a>03088 <span class="keyword">// ROXL</span>
|
| 478 |
|
|
<a name="l03089"></a>03089 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 479 |
|
|
<a name="l03090"></a>03090 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>]};
|
| 480 |
|
|
<a name="l03091"></a>03091
|
| 481 |
|
|
<a name="l03092"></a>03092 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 482 |
|
|
<a name="l03093"></a>03093 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C</span>
|
| 483 |
|
|
<a name="l03094"></a>03094 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X</span>
|
| 484 |
|
|
<a name="l03095"></a>03095 <span class="vhdlkeyword">end</span>
|
| 485 |
|
|
<a name="l03096"></a>03096 <span class="keyword">// ASR</span>
|
| 486 |
|
|
<a name="l03097"></a>03097 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b00</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b00</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 487 |
|
|
<a name="l03098"></a>03098 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
| 488 |
|
|
<a name="l03099"></a>03099 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
| 489 |
|
|
<a name="l03100"></a>03100 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
| 490 |
|
|
<a name="l03101"></a>03101
|
| 491 |
|
|
<a name="l03102"></a>03102 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 492 |
|
|
<a name="l03103"></a>03103 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
| 493 |
|
|
<a name="l03104"></a>03104 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
| 494 |
|
|
<a name="l03105"></a>03105 <span class="vhdlkeyword">end</span>
|
| 495 |
|
|
<a name="l03106"></a>03106 <span class="keyword">// LSR</span>
|
| 496 |
|
|
<a name="l03107"></a>03107 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b01</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b01</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 497 |
|
|
<a name="l03108"></a>03108 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
| 498 |
|
|
<a name="l03109"></a>03109 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
| 499 |
|
|
<a name="l03110"></a>03110 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
| 500 |
|
|
<a name="l03111"></a>03111
|
| 501 |
|
|
<a name="l03112"></a>03112 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 502 |
|
|
<a name="l03113"></a>03113 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
| 503 |
|
|
<a name="l03114"></a>03114 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
| 504 |
|
|
<a name="l03115"></a>03115 <span class="vhdlkeyword">end</span>
|
| 505 |
|
|
<a name="l03116"></a>03116 <span class="keyword">// ROR</span>
|
| 506 |
|
|
<a name="l03117"></a>03117 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b11</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b11</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 507 |
|
|
<a name="l03118"></a>03118 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>] };
|
| 508 |
|
|
<a name="l03119"></a>03119 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>] };
|
| 509 |
|
|
<a name="l03120"></a>03120 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>] };
|
| 510 |
|
|
<a name="l03121"></a>03121
|
| 511 |
|
|
<a name="l03122"></a>03122 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 512 |
|
|
<a name="l03123"></a>03123 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
| 513 |
|
|
<a name="l03124"></a>03124 <span class="keyword">// X not affected</span>
|
| 514 |
|
|
<a name="l03125"></a>03125 <span class="vhdlkeyword">end</span>
|
| 515 |
|
|
<a name="l03126"></a>03126 <span class="keyword">// ROXR</span>
|
| 516 |
|
|
<a name="l03127"></a>03127 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">9</span>] == <span class="vhdllogic">2'b10</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] != <span class="vhdllogic">2'b11</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">2'b10</span>)) && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 517 |
|
|
<a name="l03128"></a>03128 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>]};
|
| 518 |
|
|
<a name="l03129"></a>03129 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">1</span>]};
|
| 519 |
|
|
<a name="l03130"></a>03130 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>]};
|
| 520 |
|
|
<a name="l03131"></a>03131
|
| 521 |
|
|
<a name="l03132"></a>03132 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V</span>
|
| 522 |
|
|
<a name="l03133"></a>03133 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C</span>
|
| 523 |
|
|
<a name="l03134"></a>03134 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X</span>
|
| 524 |
|
|
<a name="l03135"></a>03135 <span class="vhdlkeyword">end</span>
|
| 525 |
|
|
<a name="l03136"></a>03136
|
| 526 |
|
|
<a name="l03137"></a>03137 <span class="keyword">// N set</span>
|
| 527 |
|
|
<a name="l03138"></a>03138 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 528 |
|
|
<a name="l03139"></a>03139 <span class="keyword">// Z set</span>
|
| 529 |
|
|
<a name="l03140"></a>03140 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 530 |
|
|
<a name="l03141"></a>03141 <span class="vhdlkeyword">end</span>
|
| 531 |
|
|
<a name="l03142"></a>03142
|
| 532 |
|
|
<a name="l03143"></a>03143 <a class="code" href="ao68000_8v.html#a268aa82704bd8f1c1548dfc69a12a951">`ALU_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 533 |
|
|
<a name="l03144"></a>03144 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 534 |
|
|
<a name="l03145"></a>03145
|
| 535 |
|
|
<a name="l03146"></a>03146 <span class="keyword">// X not affected</span>
|
| 536 |
|
|
<a name="l03147"></a>03147 <span class="keyword">// C cleared</span>
|
| 537 |
|
|
<a name="l03148"></a>03148 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 538 |
|
|
<a name="l03149"></a>03149 <span class="keyword">// V cleared</span>
|
| 539 |
|
|
<a name="l03150"></a>03150 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 540 |
|
|
<a name="l03151"></a>03151
|
| 541 |
|
|
<a name="l03152"></a>03152 <span class="keyword">// N set</span>
|
| 542 |
|
|
<a name="l03153"></a>03153 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 543 |
|
|
<a name="l03154"></a>03154 <span class="keyword">// Z set</span>
|
| 544 |
|
|
<a name="l03155"></a>03155 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 545 |
|
|
<a name="l03156"></a>03156 <span class="vhdlkeyword">end</span>
|
| 546 |
|
|
<a name="l03157"></a>03157
|
| 547 |
|
|
<a name="l03158"></a>03158 <a class="code" href="ao68000_8v.html#a30a87601d2ca38286bb0d486d59f6a07">`ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 548 |
|
|
<a name="l03159"></a>03159 <span class="keyword">// ADDA: 1101</span>
|
| 549 |
|
|
<a name="l03160"></a>03160 <span class="keyword">// CMPA: 1011</span>
|
| 550 |
|
|
<a name="l03161"></a>03161 <span class="keyword">// SUBA: 1001</span>
|
| 551 |
|
|
<a name="l03162"></a>03162 <span class="keyword">// ADDQ,SUBQ: 0101 xxx0,1</span>
|
| 552 |
|
|
<a name="l03163"></a>03163 <span class="keyword">// operation requires that operand2 was sign extended</span>
|
| 553 |
|
|
<a name="l03164"></a>03164
|
| 554 |
|
|
<a name="l03165"></a>03165 <span class="keyword">// ADDA,ADDQ</span>
|
| 555 |
|
|
<a name="l03166"></a>03166 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1101</span> || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b0</span>) )
|
| 556 |
|
|
<a name="l03167"></a>03167 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 557 |
|
|
<a name="l03168"></a>03168 <span class="keyword">// SUBA,CMPA,SUBQ</span>
|
| 558 |
|
|
<a name="l03169"></a>03169 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1001</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b0101</span> && <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">8</span>] == <span class="vhdllogic">1'b1</span>) )
|
| 559 |
|
|
<a name="l03170"></a>03170 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 560 |
|
|
<a name="l03171"></a>03171
|
| 561 |
|
|
<a name="l03172"></a>03172 <span class="keyword">// for CMPA</span>
|
| 562 |
|
|
<a name="l03173"></a>03173 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> ) <span class="vhdlkeyword">begin</span>
|
| 563 |
|
|
<a name="l03174"></a>03174 <span class="keyword">// Z</span>
|
| 564 |
|
|
<a name="l03175"></a>03175 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 565 |
|
|
<a name="l03176"></a>03176 <span class="keyword">// N</span>
|
| 566 |
|
|
<a name="l03177"></a>03177 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 567 |
|
|
<a name="l03178"></a>03178
|
| 568 |
|
|
<a name="l03179"></a>03179 <span class="keyword">// C,V</span>
|
| 569 |
|
|
<a name="l03180"></a>03180 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 570 |
|
|
<a name="l03181"></a>03181 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 571 |
|
|
<a name="l03182"></a>03182 <span class="keyword">// X not affected</span>
|
| 572 |
|
|
<a name="l03183"></a>03183 <span class="vhdlkeyword">end</span>
|
| 573 |
|
|
<a name="l03184"></a>03184 <span class="keyword">// for ADDA,SUBA,ADDQ,SUBQ: ccr not affected</span>
|
| 574 |
|
|
<a name="l03185"></a>03185 <span class="vhdlkeyword">end</span>
|
| 575 |
|
|
<a name="l03186"></a>03186
|
| 576 |
|
|
<a name="l03187"></a>03187 <a class="code" href="ao68000_8v.html#af0a4db089a5eb288abf9453ca2d79c26">`ALU_CHK</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 577 |
|
|
<a name="l03188"></a>03188 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
| 578 |
|
|
<a name="l03189"></a>03189
|
| 579 |
|
|
<a name="l03190"></a>03190 <span class="keyword">// undocumented behavior: Z flag, see 68knotes.txt</span>
|
| 580 |
|
|
<a name="l03191"></a>03191 <span class="keyword">//sr[2] <= (operand1[15:0] == 16'b0) ? 1'b1 : 1'b0;</span>
|
| 581 |
|
|
<a name="l03192"></a>03192 <span class="keyword">// undocumented behavior: C,V flags, see 68knotes.txt</span>
|
| 582 |
|
|
<a name="l03193"></a>03193 <span class="keyword">//sr[0] <= 1'b0;</span>
|
| 583 |
|
|
<a name="l03194"></a>03194 <span class="keyword">//sr[1] <= 1'b0;</span>
|
| 584 |
|
|
<a name="l03195"></a>03195
|
| 585 |
|
|
<a name="l03196"></a>03196 <span class="keyword">// C,X,V</span>
|
| 586 |
|
|
<a name="l03197"></a>03197 <span class="keyword">// sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);</span>
|
| 587 |
|
|
<a name="l03198"></a>03198 <span class="keyword">// sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];</span>
|
| 588 |
|
|
<a name="l03199"></a>03199 <span class="keyword">// sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);</span>
|
| 589 |
|
|
<a name="l03200"></a>03200 <span class="keyword">// +: 0-1, 0-0=0, 1-1=0</span>
|
| 590 |
|
|
<a name="l03201"></a>03201 <span class="keyword">// -: 0-0=1, 1-0, 1-1=1</span>
|
| 591 |
|
|
<a name="l03202"></a>03202 <span class="keyword">// operand1 - operand2 > 0</span>
|
| 592 |
|
|
<a name="l03203"></a>03203 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] && ((~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>)) == <span class="vhdllogic">1'b1</span> ) <span class="vhdlkeyword">begin</span>
|
| 593 |
|
|
<a name="l03204"></a>03204 <span class="keyword">// clear N</span>
|
| 594 |
|
|
<a name="l03205"></a>03205 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 595 |
|
|
<a name="l03206"></a>03206 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 596 |
|
|
<a name="l03207"></a>03207 <span class="vhdlkeyword">end</span>
|
| 597 |
|
|
<a name="l03208"></a>03208 <span class="keyword">// operand1 < 0</span>
|
| 598 |
|
|
<a name="l03209"></a>03209 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span> ) <span class="vhdlkeyword">begin</span>
|
| 599 |
|
|
<a name="l03210"></a>03210 <span class="keyword">// set N</span>
|
| 600 |
|
|
<a name="l03211"></a>03211 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b1</span>;
|
| 601 |
|
|
<a name="l03212"></a>03212 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 602 |
|
|
<a name="l03213"></a>03213 <span class="vhdlkeyword">end</span>
|
| 603 |
|
|
<a name="l03214"></a>03214 <span class="keyword">// no trap</span>
|
| 604 |
|
|
<a name="l03215"></a>03215 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 605 |
|
|
<a name="l03216"></a>03216 <span class="keyword">// N undefined: not affected</span>
|
| 606 |
|
|
<a name="l03217"></a>03217 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 607 |
|
|
<a name="l03218"></a>03218 <span class="vhdlkeyword">end</span>
|
| 608 |
|
|
<a name="l03219"></a>03219
|
| 609 |
|
|
<a name="l03220"></a>03220 <span class="keyword">// X not affected</span>
|
| 610 |
|
|
<a name="l03221"></a>03221 <span class="vhdlkeyword">end</span>
|
| 611 |
|
|
<a name="l03222"></a>03222
|
| 612 |
|
|
<a name="l03223"></a>03223 <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 613 |
|
|
<a name="l03224"></a>03224
|
| 614 |
|
|
<a name="l03225"></a>03225 <span class="keyword">// division by 0</span>
|
| 615 |
|
|
<a name="l03226"></a>03226 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 616 |
|
|
<a name="l03227"></a>03227 <span class="keyword">// X not affected</span>
|
| 617 |
|
|
<a name="l03228"></a>03228 <span class="keyword">// C cleared</span>
|
| 618 |
|
|
<a name="l03229"></a>03229 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 619 |
|
|
<a name="l03230"></a>03230 <span class="keyword">// V,Z,N undefined: cleared</span>
|
| 620 |
|
|
<a name="l03231"></a>03231 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 621 |
|
|
<a name="l03232"></a>03232 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 622 |
|
|
<a name="l03233"></a>03233 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 623 |
|
|
<a name="l03234"></a>03234
|
| 624 |
|
|
<a name="l03235"></a>03235 <span class="keyword">// set trap</span>
|
| 625 |
|
|
<a name="l03236"></a>03236 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 626 |
|
|
<a name="l03237"></a>03237 <span class="vhdlkeyword">end</span>
|
| 627 |
|
|
<a name="l03238"></a>03238 <span class="keyword">// division in idle state</span>
|
| 628 |
|
|
<a name="l03239"></a>03239 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a> == <span class="vhdllogic">5'd0</span>) <span class="vhdlkeyword">begin</span>
|
| 629 |
|
|
<a name="l03240"></a>03240 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 630 |
|
|
<a name="l03241"></a>03241 <span class="vhdlkeyword">end</span>
|
| 631 |
|
|
<a name="l03242"></a>03242 <span class="keyword">// division overflow: divu, divs</span>
|
| 632 |
|
|
<a name="l03243"></a>03243 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">div_overflow</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 633 |
|
|
<a name="l03244"></a>03244 <span class="keyword">/*OPTIM</span>
|
| 634 |
|
|
<a name="l03245"></a>03245 <span class="keyword"> else if( ((ir[15:12] == 4'b1000 && mult_div_sign == 1'b0) && (divu_quotient[31:16] != 16'd0)) ||</span>
|
| 635 |
|
|
<a name="l03246"></a>03246 <span class="keyword"> ((ir[15:12] == 4'b1000 && mult_div_sign == 1'b1) && (divs_quotient[31:16] != {16{divs_quotient[15]}}))</span>
|
| 636 |
|
|
<a name="l03247"></a>03247 <span class="keyword"> ) begin</span>
|
| 637 |
|
|
<a name="l03248"></a>03248 <span class="keyword"> */</span>
|
| 638 |
|
|
<a name="l03249"></a>03249 <span class="keyword">// X not affected</span>
|
| 639 |
|
|
<a name="l03250"></a>03250 <span class="keyword">// C cleared</span>
|
| 640 |
|
|
<a name="l03251"></a>03251 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 641 |
|
|
<a name="l03252"></a>03252 <span class="keyword">// V set</span>
|
| 642 |
|
|
<a name="l03253"></a>03253 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b1</span>;
|
| 643 |
|
|
<a name="l03254"></a>03254 <span class="keyword">// Z,N undefined: cleared and set</span>
|
| 644 |
|
|
<a name="l03255"></a>03255 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 645 |
|
|
<a name="l03256"></a>03256 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b1</span>;
|
| 646 |
|
|
<a name="l03257"></a>03257
|
| 647 |
|
|
<a name="l03258"></a>03258 <span class="keyword">// set trap</span>
|
| 648 |
|
|
<a name="l03259"></a>03259 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 649 |
|
|
<a name="l03260"></a>03260 <span class="vhdlkeyword">end</span>
|
| 650 |
|
|
<a name="l03261"></a>03261 <span class="keyword">// division</span>
|
| 651 |
|
|
<a name="l03262"></a>03262 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> ) <span class="vhdlkeyword">begin</span>
|
| 652 |
|
|
<a name="l03263"></a>03263 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <= {<a class="code" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">div_remainder</a>, <a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a>};
|
| 653 |
|
|
<a name="l03264"></a>03264
|
| 654 |
|
|
<a name="l03265"></a>03265 <span class="keyword">// X not affected</span>
|
| 655 |
|
|
<a name="l03266"></a>03266 <span class="keyword">// C cleared</span>
|
| 656 |
|
|
<a name="l03267"></a>03267 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 657 |
|
|
<a name="l03268"></a>03268 <span class="keyword">// V cleared</span>
|
| 658 |
|
|
<a name="l03269"></a>03269 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 659 |
|
|
<a name="l03270"></a>03270 <span class="keyword">// Z</span>
|
| 660 |
|
|
<a name="l03271"></a>03271 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a> == <span class="vhdllogic">16'b0</span>);
|
| 661 |
|
|
<a name="l03272"></a>03272 <span class="keyword">// N</span>
|
| 662 |
|
|
<a name="l03273"></a>03273 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span>);
|
| 663 |
12 |
alfik |
<a name="l03274"></a>03274
|
| 664 |
13 |
alfik |
<a name="l03275"></a>03275 <span class="keyword">// set trap</span>
|
| 665 |
|
|
<a name="l03276"></a>03276 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 666 |
|
|
<a name="l03277"></a>03277 <span class="vhdlkeyword">end</span>
|
| 667 |
|
|
<a name="l03278"></a>03278 <span class="keyword">// multiplication</span>
|
| 668 |
|
|
<a name="l03279"></a>03279 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> ) <span class="vhdlkeyword">begin</span>
|
| 669 |
|
|
<a name="l03280"></a>03280 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 670 |
|
|
<a name="l03281"></a>03281
|
| 671 |
|
|
<a name="l03282"></a>03282 <span class="keyword">// X not affected</span>
|
| 672 |
|
|
<a name="l03283"></a>03283 <span class="keyword">// C cleared</span>
|
| 673 |
|
|
<a name="l03284"></a>03284 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 674 |
|
|
<a name="l03285"></a>03285 <span class="keyword">// V cleared</span>
|
| 675 |
|
|
<a name="l03286"></a>03286 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 676 |
|
|
<a name="l03287"></a>03287 <span class="keyword">// Z</span>
|
| 677 |
|
|
<a name="l03288"></a>03288 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">32'b0</span>);
|
| 678 |
|
|
<a name="l03289"></a>03289 <span class="keyword">// N</span>
|
| 679 |
|
|
<a name="l03290"></a>03290 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a>[<span class="vhdllogic">31</span>] == <span class="vhdllogic">1'b1</span>);
|
| 680 |
|
|
<a name="l03291"></a>03291
|
| 681 |
|
|
<a name="l03292"></a>03292 <span class="keyword">// set trap</span>
|
| 682 |
|
|
<a name="l03293"></a>03293 <a class="code" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 683 |
12 |
alfik |
<a name="l03294"></a>03294 <span class="vhdlkeyword">end</span>
|
| 684 |
13 |
alfik |
<a name="l03295"></a>03295 <span class="vhdlkeyword">end</span>
|
| 685 |
|
|
<a name="l03296"></a>03296
|
| 686 |
|
|
<a name="l03297"></a>03297
|
| 687 |
|
|
<a name="l03298"></a>03298 <a class="code" href="ao68000_8v.html#a14b85ce3e5b4ede3b2c4e89f420c8c3c">`ALU_BCHG_BCLR_BSET_BTST</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span> <span class="keyword">// 97 LE</span>
|
| 688 |
|
|
<a name="l03299"></a>03299 <span class="keyword">// byte</span>
|
| 689 |
|
|
<a name="l03300"></a>03300 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
| 690 |
|
|
<a name="l03301"></a>03301 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ]);
|
| 691 |
|
|
<a name="l03302"></a>03302 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 692 |
|
|
<a name="l03303"></a>03303 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ] = (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>) ? ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ]) : (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
| 693 |
|
|
<a name="l03304"></a>03304 <span class="vhdlkeyword">end</span>
|
| 694 |
|
|
<a name="l03305"></a>03305 <span class="keyword">// long</span>
|
| 695 |
|
|
<a name="l03306"></a>03306 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
| 696 |
|
|
<a name="l03307"></a>03307 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ]);
|
| 697 |
|
|
<a name="l03308"></a>03308 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 698 |
|
|
<a name="l03309"></a>03309 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ] = (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>) ? ~(<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[ <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ]) : (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
| 699 |
|
|
<a name="l03310"></a>03310 <span class="vhdlkeyword">end</span>
|
| 700 |
|
|
<a name="l03311"></a>03311
|
| 701 |
|
|
<a name="l03312"></a>03312 <span class="keyword">// C,V,N,X not affected</span>
|
| 702 |
|
|
<a name="l03313"></a>03313 <span class="vhdlkeyword">end</span>
|
| 703 |
|
|
<a name="l03314"></a>03314
|
| 704 |
|
|
<a name="l03315"></a>03315 <a class="code" href="ao68000_8v.html#ac7de3ab6c8eec4381bde5e4f61b45761">`ALU_TAS</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 705 |
|
|
<a name="l03316"></a>03316 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= { <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">6</span>:<span class="vhdllogic">0</span>] };
|
| 706 |
|
|
<a name="l03317"></a>03317
|
| 707 |
|
|
<a name="l03318"></a>03318 <span class="keyword">// X not affected</span>
|
| 708 |
|
|
<a name="l03319"></a>03319 <span class="keyword">// C cleared</span>
|
| 709 |
|
|
<a name="l03320"></a>03320 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 710 |
|
|
<a name="l03321"></a>03321 <span class="keyword">// V cleared</span>
|
| 711 |
|
|
<a name="l03322"></a>03322 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 712 |
|
|
<a name="l03323"></a>03323
|
| 713 |
|
|
<a name="l03324"></a>03324 <span class="keyword">// N set</span>
|
| 714 |
|
|
<a name="l03325"></a>03325 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>);
|
| 715 |
|
|
<a name="l03326"></a>03326 <span class="keyword">// Z set</span>
|
| 716 |
|
|
<a name="l03327"></a>03327 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>);
|
| 717 |
|
|
<a name="l03328"></a>03328 <span class="vhdlkeyword">end</span>
|
| 718 |
|
|
<a name="l03329"></a>03329
|
| 719 |
|
|
<a name="l03330"></a>03330
|
| 720 |
|
|
<a name="l03331"></a>03331 <a class="code" href="ao68000_8v.html#a07c7e53af3f4995a167966ba18c2728f">`ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 721 |
|
|
<a name="l03332"></a>03332 <span class="keyword">// NEGX / CLR / NEG / NOT</span>
|
| 722 |
|
|
<a name="l03333"></a>03333 <span class="vhdlkeyword">if</span> ((<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span>) || (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span>))
|
| 723 |
|
|
<a name="l03334"></a>03334 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = <span class="vhdllogic">32'b0</span> - (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] & {<span class="vhdllogic">32</span>{<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] | ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]}}) - ((<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] & ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] & ~<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]) | (<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">10</span>] & <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">9</span>]));
|
| 724 |
|
|
<a name="l03335"></a>03335 <span class="keyword">/*OPTIM</span>
|
| 725 |
|
|
<a name="l03336"></a>03336 <span class="keyword"> // NEGX</span>
|
| 726 |
|
|
<a name="l03337"></a>03337 <span class="keyword"> if( ir[11:8] == 4'b0000 ) result = 32'b0 - operand1[31:0] - sr[4];</span>
|
| 727 |
|
|
<a name="l03338"></a>03338 <span class="keyword"> // CLR</span>
|
| 728 |
|
|
<a name="l03339"></a>03339 <span class="keyword"> else if (ir[11:8] == 4'b0010) result = 32'b0;</span>
|
| 729 |
|
|
<a name="l03340"></a>03340 <span class="keyword"> // NEG</span>
|
| 730 |
|
|
<a name="l03341"></a>03341 <span class="keyword"> else if( ir[11:8] == 4'b0100 ) result = 32'b0 - operand1[31:0];</span>
|
| 731 |
|
|
<a name="l03342"></a>03342 <span class="keyword"> // NOT</span>
|
| 732 |
|
|
<a name="l03343"></a>03343 <span class="keyword"> else if( ir[11:8] == 4'b0110 ) result = ~operand1[31:0];</span>
|
| 733 |
|
|
<a name="l03344"></a>03344 <span class="keyword"> */</span>
|
| 734 |
|
|
<a name="l03345"></a>03345 <span class="keyword">// NBCD</span>
|
| 735 |
|
|
<a name="l03346"></a>03346 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_00</span> ) <span class="vhdlkeyword">begin</span>
|
| 736 |
|
|
<a name="l03347"></a>03347
|
| 737 |
|
|
<a name="l03348"></a>03348 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">5'd25</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>];
|
| 738 |
|
|
<a name="l03349"></a>03349 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] > <span class="vhdllogic">4'd9</span>) ? (<span class="vhdllogic">5'd24</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]) : (<span class="vhdllogic">5'd25</span> - <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]);
|
| 739 |
|
|
<a name="l03350"></a>03350
|
| 740 |
|
|
<a name="l03351"></a>03351 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span> && <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd9</span>) <span class="vhdlkeyword">begin</span>
|
| 741 |
|
|
<a name="l03352"></a>03352 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">4'd0</span>;
|
| 742 |
|
|
<a name="l03353"></a>03353 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <span class="vhdllogic">4'd0</span>;
|
| 743 |
|
|
<a name="l03354"></a>03354 <span class="vhdlkeyword">end</span>
|
| 744 |
|
|
<a name="l03355"></a>03355 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span> && (<a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span> || <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd15</span>)) <span class="vhdlkeyword">begin</span>
|
| 745 |
|
|
<a name="l03356"></a>03356 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">4'd0</span>;
|
| 746 |
|
|
<a name="l03357"></a>03357 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] + <span class="vhdllogic">4'd1</span>;
|
| 747 |
|
|
<a name="l03358"></a>03358 <span class="vhdlkeyword">end</span>
|
| 748 |
|
|
<a name="l03359"></a>03359 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 749 |
|
|
<a name="l03360"></a>03360 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] + <span class="vhdllogic">4'd1</span>;
|
| 750 |
|
|
<a name="l03361"></a>03361 <span class="vhdlkeyword">end</span>
|
| 751 |
|
|
<a name="l03362"></a>03362
|
| 752 |
|
|
<a name="l03363"></a>03363 <span class="keyword">//V undefined: unchanged</span>
|
| 753 |
|
|
<a name="l03364"></a>03364 <span class="keyword">//Z</span>
|
| 754 |
|
|
<a name="l03365"></a>03365 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 755 |
|
|
<a name="l03366"></a>03366 <span class="keyword">//C,X</span>
|
| 756 |
|
|
<a name="l03367"></a>03367 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'd0</span> && <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
| 757 |
|
|
<a name="l03368"></a>03368 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'd0</span> && <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>; <span class="keyword">//=C</span>
|
| 758 |
|
|
<a name="l03369"></a>03369 <span class="vhdlkeyword">end</span>
|
| 759 |
|
|
<a name="l03370"></a>03370 <span class="keyword">// SWAP</span>
|
| 760 |
|
|
<a name="l03371"></a>03371 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_01</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>] };
|
| 761 |
|
|
<a name="l03372"></a>03372 <span class="keyword">// EXT byte to word</span>
|
| 762 |
|
|
<a name="l03373"></a>03373 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_10</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>], {<span class="vhdllogic">8</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 763 |
|
|
<a name="l03374"></a>03374 <span class="keyword">// EXT word to long</span>
|
| 764 |
|
|
<a name="l03375"></a>03375 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_11</span> ) <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> = { {<span class="vhdllogic">16</span>{<a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
| 765 |
|
|
<a name="l03376"></a>03376
|
| 766 |
|
|
<a name="l03377"></a>03377 <span class="keyword">// N set if negative else clear</span>
|
| 767 |
|
|
<a name="l03378"></a>03378 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 768 |
|
|
<a name="l03379"></a>03379
|
| 769 |
|
|
<a name="l03380"></a>03380 <span class="keyword">// CLR,NOT,SWAP,EXT</span>
|
| 770 |
|
|
<a name="l03381"></a>03381 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_01</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">5'b1000_1</span> ) <span class="vhdlkeyword">begin</span>
|
| 771 |
|
|
<a name="l03382"></a>03382 <span class="keyword">// X not affected</span>
|
| 772 |
|
|
<a name="l03383"></a>03383 <span class="keyword">// C,V cleared</span>
|
| 773 |
|
|
<a name="l03384"></a>03384 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 774 |
|
|
<a name="l03385"></a>03385 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 775 |
|
|
<a name="l03386"></a>03386 <span class="keyword">// Z set</span>
|
| 776 |
|
|
<a name="l03387"></a>03387 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 777 |
|
|
<a name="l03388"></a>03388 <span class="vhdlkeyword">end</span>
|
| 778 |
|
|
<a name="l03389"></a>03389 <span class="keyword">// NEGX</span>
|
| 779 |
|
|
<a name="l03390"></a>03390 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span> ) <span class="vhdlkeyword">begin</span>
|
| 780 |
|
|
<a name="l03391"></a>03391 <span class="keyword">// C set if borrow</span>
|
| 781 |
|
|
<a name="l03392"></a>03392 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 782 |
|
|
<a name="l03393"></a>03393 <span class="keyword">// X=C</span>
|
| 783 |
|
|
<a name="l03394"></a>03394 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 784 |
|
|
<a name="l03395"></a>03395 <span class="keyword">// V set if overflow</span>
|
| 785 |
|
|
<a name="l03396"></a>03396 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 786 |
|
|
<a name="l03397"></a>03397 <span class="keyword">// Z cleared if nonzero else unchanged</span>
|
| 787 |
|
|
<a name="l03398"></a>03398 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 788 |
|
|
<a name="l03399"></a>03399 <span class="vhdlkeyword">end</span>
|
| 789 |
|
|
<a name="l03400"></a>03400 <span class="keyword">// NEG</span>
|
| 790 |
|
|
<a name="l03401"></a>03401 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span> ) <span class="vhdlkeyword">begin</span>
|
| 791 |
|
|
<a name="l03402"></a>03402 <span class="keyword">// C clear if zero else set</span>
|
| 792 |
|
|
<a name="l03403"></a>03403 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 793 |
|
|
<a name="l03404"></a>03404 <span class="keyword">// X=C</span>
|
| 794 |
|
|
<a name="l03405"></a>03405 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 795 |
|
|
<a name="l03406"></a>03406 <span class="keyword">// V set if overflow</span>
|
| 796 |
|
|
<a name="l03407"></a>03407 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">1</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 797 |
|
|
<a name="l03408"></a>03408 <span class="keyword">// Z set if zero else clear</span>
|
| 798 |
|
|
<a name="l03409"></a>03409 <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 799 |
|
|
<a name="l03410"></a>03410 <span class="vhdlkeyword">end</span>
|
| 800 |
|
|
<a name="l03411"></a>03411 <span class="vhdlkeyword">end</span>
|
| 801 |
|
|
<a name="l03412"></a>03412
|
| 802 |
|
|
<a name="l03413"></a>03413
|
| 803 |
|
|
<a name="l03414"></a>03414 <a class="code" href="ao68000_8v.html#a32c0e163ff437b07e40593ab59e42fe3">`ALU_SIMPLE_LONG_ADD</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 804 |
|
|
<a name="l03415"></a>03415 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 805 |
|
|
<a name="l03416"></a>03416
|
| 806 |
|
|
<a name="l03417"></a>03417 <span class="keyword">// CCR not affected</span>
|
| 807 |
|
|
<a name="l03418"></a>03418 <span class="vhdlkeyword">end</span>
|
| 808 |
|
|
<a name="l03419"></a>03419
|
| 809 |
|
|
<a name="l03420"></a>03420 <a class="code" href="ao68000_8v.html#aea6fee15f3d775b1a8d262490203c713">`ALU_SIMPLE_LONG_SUB</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 810 |
|
|
<a name="l03421"></a>03421 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 811 |
|
|
<a name="l03422"></a>03422
|
| 812 |
|
|
<a name="l03423"></a>03423 <span class="keyword">// CCR not affected</span>
|
| 813 |
|
|
<a name="l03424"></a>03424 <span class="vhdlkeyword">end</span>
|
| 814 |
|
|
<a name="l03425"></a>03425
|
| 815 |
|
|
<a name="l03426"></a>03426 <a class="code" href="ao68000_8v.html#a5083d98f4b785fe7af85ba1114f678ff">`ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 816 |
|
|
<a name="l03427"></a>03427
|
| 817 |
|
|
<a name="l03428"></a>03428 <span class="keyword">// MOVE TO SR,RTE,STOP,ORI to SR,ANDI to SR,EORI to SR</span>
|
| 818 |
|
|
<a name="l03429"></a>03429 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">8'b0100_0110</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0011</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0010</span> ||
|
| 819 |
|
|
<a name="l03430"></a>03430 <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_01_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_01_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_01_111100</span>
|
| 820 |
|
|
<a name="l03431"></a>03431 ) <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">15</span>], <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">13</span>], <span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
| 821 |
|
|
<a name="l03432"></a>03432 <span class="keyword">// MOVE TO CCR,RTR,ORI to CCR,ANDI to CCR,EORI to CCR</span>
|
| 822 |
|
|
<a name="l03433"></a>03433 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">8'b0100_0100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0100_1110_0111_0111</span> ||
|
| 823 |
|
|
<a name="l03434"></a>03434 <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_000_0_00_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_001_0_00_111100</span> || <a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0000_101_0_00_111100</span>
|
| 824 |
|
|
<a name="l03435"></a>03435 ) <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a> <= { <a class="code" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
| 825 |
|
|
<a name="l03436"></a>03436 <span class="vhdlkeyword">end</span>
|
| 826 |
|
|
<a name="l03437"></a>03437
|
| 827 |
|
|
<a name="l03438"></a>03438 <a class="code" href="ao68000_8v.html#ab6d6f774c41848f9c33c7b393620be2d">`ALU_SIMPLE_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 828 |
|
|
<a name="l03439"></a>03439 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 829 |
|
|
<a name="l03440"></a>03440
|
| 830 |
|
|
<a name="l03441"></a>03441 <span class="keyword">// CCR not affected</span>
|
| 831 |
|
|
<a name="l03442"></a>03442 <span class="vhdlkeyword">end</span>
|
| 832 |
|
|
<a name="l03443"></a>03443
|
| 833 |
|
|
<a name="l03444"></a>03444 <a class="code" href="ao68000_8v.html#ac439a8b79bd4b213f0f33172bd5e5a73">`ALU_LINK_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 834 |
|
|
<a name="l03445"></a>03445 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">3'b111</span>) <span class="vhdlkeyword">begin</span>
|
| 835 |
|
|
<a name="l03446"></a>03446 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a> - <span class="vhdllogic">32'd4</span>;
|
| 836 |
|
|
<a name="l03447"></a>03447 <span class="vhdlkeyword">end</span>
|
| 837 |
|
|
<a name="l03448"></a>03448 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 838 |
|
|
<a name="l03449"></a>03449 <a class="code" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a> <= <a class="code" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a>;
|
| 839 |
|
|
<a name="l03450"></a>03450 <span class="vhdlkeyword">end</span>
|
| 840 |
|
|
<a name="l03451"></a>03451
|
| 841 |
|
|
<a name="l03452"></a>03452 <span class="keyword">// CCR not affected</span>
|
| 842 |
|
|
<a name="l03453"></a>03453 <span class="vhdlkeyword">end</span>
|
| 843 |
|
|
<a name="l03454"></a>03454
|
| 844 |
|
|
<a name="l03455"></a>03455 <span class="vhdlkeyword">endcase</span>
|
| 845 |
|
|
<a name="l03456"></a>03456 <span class="vhdlkeyword">end</span>
|
| 846 |
|
|
<a name="l03457"></a>03457 <span class="vhdlkeyword">end</span>
|
| 847 |
12 |
alfik |
</pre></div>
|
| 848 |
|
|
</div>
|
| 849 |
|
|
</div>
|
| 850 |
|
|
<hr/><h2>Member Data Documentation</h2>
|
| 851 |
13 |
alfik |
<a class="anchor" id="aaa60d149641cba8468ad7791eb5999ab"></a><!-- doxytag: member="alu::clock" ref="aaa60d149641cba8468ad7791eb5999ab" args="" -->
|
| 852 |
12 |
alfik |
<div class="memitem">
|
| 853 |
|
|
<div class="memproto">
|
| 854 |
|
|
<table class="memname">
|
| 855 |
|
|
<tr>
|
| 856 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#aaa60d149641cba8468ad7791eb5999ab">clock</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 857 |
12 |
alfik |
</tr>
|
| 858 |
|
|
</table>
|
| 859 |
|
|
</div>
|
| 860 |
|
|
<div class="memdoc">
|
| 861 |
|
|
|
| 862 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02592">2592</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 863 |
12 |
alfik |
|
| 864 |
|
|
</div>
|
| 865 |
|
|
</div>
|
| 866 |
13 |
alfik |
<a class="anchor" id="a5e83fb99cb897f45ca128fa1594c5967"></a><!-- doxytag: member="alu::reset_n" ref="a5e83fb99cb897f45ca128fa1594c5967" args="" -->
|
| 867 |
12 |
alfik |
<div class="memitem">
|
| 868 |
|
|
<div class="memproto">
|
| 869 |
|
|
<table class="memname">
|
| 870 |
|
|
<tr>
|
| 871 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a5e83fb99cb897f45ca128fa1594c5967">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 872 |
12 |
alfik |
</tr>
|
| 873 |
|
|
</table>
|
| 874 |
|
|
</div>
|
| 875 |
|
|
<div class="memdoc">
|
| 876 |
|
|
|
| 877 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02593">2593</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 878 |
12 |
alfik |
|
| 879 |
|
|
</div>
|
| 880 |
|
|
</div>
|
| 881 |
13 |
alfik |
<a class="anchor" id="a379cf0ab5b30f07c291e327fc5bb194f"></a><!-- doxytag: member="alu::address" ref="a379cf0ab5b30f07c291e327fc5bb194f" args="" -->
|
| 882 |
12 |
alfik |
<div class="memitem">
|
| 883 |
|
|
<div class="memproto">
|
| 884 |
|
|
<table class="memname">
|
| 885 |
|
|
<tr>
|
| 886 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a379cf0ab5b30f07c291e327fc5bb194f">address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 887 |
12 |
alfik |
</tr>
|
| 888 |
|
|
</table>
|
| 889 |
|
|
</div>
|
| 890 |
|
|
<div class="memdoc">
|
| 891 |
|
|
|
| 892 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02596">2596</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 893 |
12 |
alfik |
|
| 894 |
|
|
</div>
|
| 895 |
|
|
</div>
|
| 896 |
13 |
alfik |
<a class="anchor" id="aff1294ddc1983f4e66996a118dc19d01"></a><!-- doxytag: member="alu::ir" ref="aff1294ddc1983f4e66996a118dc19d01" args="" -->
|
| 897 |
12 |
alfik |
<div class="memitem">
|
| 898 |
|
|
<div class="memproto">
|
| 899 |
|
|
<table class="memname">
|
| 900 |
|
|
<tr>
|
| 901 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#aff1294ddc1983f4e66996a118dc19d01">ir</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 902 |
12 |
alfik |
</tr>
|
| 903 |
|
|
</table>
|
| 904 |
|
|
</div>
|
| 905 |
|
|
<div class="memdoc">
|
| 906 |
|
|
|
| 907 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02598">2598</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 908 |
12 |
alfik |
|
| 909 |
|
|
</div>
|
| 910 |
|
|
</div>
|
| 911 |
13 |
alfik |
<a class="anchor" id="ab689dbfef609d2f29a3bfd8eea9ac4c9"></a><!-- doxytag: member="alu::size" ref="ab689dbfef609d2f29a3bfd8eea9ac4c9" args="" -->
|
| 912 |
12 |
alfik |
<div class="memitem">
|
| 913 |
|
|
<div class="memproto">
|
| 914 |
|
|
<table class="memname">
|
| 915 |
|
|
<tr>
|
| 916 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ab689dbfef609d2f29a3bfd8eea9ac4c9">size</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 917 |
12 |
alfik |
</tr>
|
| 918 |
|
|
</table>
|
| 919 |
|
|
</div>
|
| 920 |
|
|
<div class="memdoc">
|
| 921 |
|
|
|
| 922 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02600">2600</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 923 |
12 |
alfik |
|
| 924 |
|
|
</div>
|
| 925 |
|
|
</div>
|
| 926 |
13 |
alfik |
<a class="anchor" id="a321dfa4a70bd231091e44e3972b71b6d"></a><!-- doxytag: member="alu::operand1" ref="a321dfa4a70bd231091e44e3972b71b6d" args="" -->
|
| 927 |
12 |
alfik |
<div class="memitem">
|
| 928 |
|
|
<div class="memproto">
|
| 929 |
|
|
<table class="memname">
|
| 930 |
|
|
<tr>
|
| 931 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a321dfa4a70bd231091e44e3972b71b6d">operand1</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 932 |
12 |
alfik |
</tr>
|
| 933 |
|
|
</table>
|
| 934 |
|
|
</div>
|
| 935 |
|
|
<div class="memdoc">
|
| 936 |
|
|
|
| 937 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02602">2602</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 938 |
12 |
alfik |
|
| 939 |
|
|
</div>
|
| 940 |
|
|
</div>
|
| 941 |
13 |
alfik |
<a class="anchor" id="abea2bb54b9dba60806dcf2fccc896748"></a><!-- doxytag: member="alu::operand2" ref="abea2bb54b9dba60806dcf2fccc896748" args="" -->
|
| 942 |
12 |
alfik |
<div class="memitem">
|
| 943 |
|
|
<div class="memproto">
|
| 944 |
|
|
<table class="memname">
|
| 945 |
|
|
<tr>
|
| 946 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#abea2bb54b9dba60806dcf2fccc896748">operand2</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 947 |
12 |
alfik |
</tr>
|
| 948 |
|
|
</table>
|
| 949 |
|
|
</div>
|
| 950 |
|
|
<div class="memdoc">
|
| 951 |
|
|
|
| 952 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02603">2603</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 953 |
12 |
alfik |
|
| 954 |
|
|
</div>
|
| 955 |
|
|
</div>
|
| 956 |
13 |
alfik |
<a class="anchor" id="aaec5e2b3f347a2651f6456b7d0dafe16"></a><!-- doxytag: member="alu::interrupt_mask" ref="aaec5e2b3f347a2651f6456b7d0dafe16" args="" -->
|
| 957 |
12 |
alfik |
<div class="memitem">
|
| 958 |
|
|
<div class="memproto">
|
| 959 |
|
|
<table class="memname">
|
| 960 |
|
|
<tr>
|
| 961 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#aaec5e2b3f347a2651f6456b7d0dafe16">interrupt_mask</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 962 |
12 |
alfik |
</tr>
|
| 963 |
|
|
</table>
|
| 964 |
|
|
</div>
|
| 965 |
|
|
<div class="memdoc">
|
| 966 |
|
|
|
| 967 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02605">2605</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 968 |
12 |
alfik |
|
| 969 |
|
|
</div>
|
| 970 |
|
|
</div>
|
| 971 |
13 |
alfik |
<a class="anchor" id="acd09435ce38c12172a01a2b3725577dc"></a><!-- doxytag: member="alu::alu_control" ref="acd09435ce38c12172a01a2b3725577dc" args="" -->
|
| 972 |
12 |
alfik |
<div class="memitem">
|
| 973 |
|
|
<div class="memproto">
|
| 974 |
|
|
<table class="memname">
|
| 975 |
|
|
<tr>
|
| 976 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#acd09435ce38c12172a01a2b3725577dc">alu_control</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 977 |
12 |
alfik |
</tr>
|
| 978 |
|
|
</table>
|
| 979 |
|
|
</div>
|
| 980 |
|
|
<div class="memdoc">
|
| 981 |
|
|
|
| 982 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02606">2606</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 983 |
12 |
alfik |
|
| 984 |
|
|
</div>
|
| 985 |
|
|
</div>
|
| 986 |
13 |
alfik |
<a class="anchor" id="a82a5493611ab7e8e59a11376b01bf617"></a><!-- doxytag: member="alu::sr" ref="a82a5493611ab7e8e59a11376b01bf617" args="" -->
|
| 987 |
12 |
alfik |
<div class="memitem">
|
| 988 |
|
|
<div class="memproto">
|
| 989 |
|
|
<table class="memname">
|
| 990 |
|
|
<tr>
|
| 991 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a82a5493611ab7e8e59a11376b01bf617">sr</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 992 |
12 |
alfik |
</tr>
|
| 993 |
|
|
</table>
|
| 994 |
|
|
</div>
|
| 995 |
|
|
<div class="memdoc">
|
| 996 |
|
|
|
| 997 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02608">2608</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 998 |
12 |
alfik |
|
| 999 |
|
|
</div>
|
| 1000 |
|
|
</div>
|
| 1001 |
13 |
alfik |
<a class="anchor" id="aa956d8f0509c2338b20188ff77b3c219"></a><!-- doxytag: member="alu::result" ref="aa956d8f0509c2338b20188ff77b3c219" args="" -->
|
| 1002 |
12 |
alfik |
<div class="memitem">
|
| 1003 |
|
|
<div class="memproto">
|
| 1004 |
|
|
<table class="memname">
|
| 1005 |
|
|
<tr>
|
| 1006 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#aa956d8f0509c2338b20188ff77b3c219">result</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
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</tr>
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</table>
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|
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</div>
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<div class="memdoc">
|
| 1011 |
|
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| 1012 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02609">2609</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1013 |
12 |
alfik |
|
| 1014 |
|
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</div>
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| 1015 |
|
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</div>
|
| 1016 |
13 |
alfik |
<a class="anchor" id="a41770492859599997a003e2681e7d955"></a><!-- doxytag: member="alu::alu_signal" ref="a41770492859599997a003e2681e7d955" args="" -->
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alfik |
<div class="memitem">
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<div class="memproto">
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| 1019 |
|
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<table class="memname">
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| 1020 |
|
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<tr>
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| 1021 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a41770492859599997a003e2681e7d955">alu_signal</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1022 |
12 |
alfik |
</tr>
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| 1023 |
|
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</table>
|
| 1024 |
|
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</div>
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| 1025 |
|
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<div class="memdoc">
|
| 1026 |
|
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|
| 1027 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02611">2611</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1028 |
12 |
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| 1029 |
|
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</div>
|
| 1030 |
|
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</div>
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| 1031 |
13 |
alfik |
<a class="anchor" id="ab6a8e15c686ee360ddad15cd4d995ea9"></a><!-- doxytag: member="alu::alu_mult_div_ready" ref="ab6a8e15c686ee360ddad15cd4d995ea9" args="" -->
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12 |
alfik |
<div class="memitem">
|
| 1033 |
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<div class="memproto">
|
| 1034 |
|
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<table class="memname">
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| 1035 |
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<tr>
|
| 1036 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ab6a8e15c686ee360ddad15cd4d995ea9">alu_mult_div_ready</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1037 |
12 |
alfik |
</tr>
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| 1038 |
|
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</table>
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| 1039 |
|
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</div>
|
| 1040 |
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<div class="memdoc">
|
| 1041 |
|
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|
| 1042 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02612">2612</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1043 |
12 |
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|
| 1044 |
|
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</div>
|
| 1045 |
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</div>
|
| 1046 |
13 |
alfik |
<a class="anchor" id="abbf525422eca0279b697f742b90237e0"></a><!-- doxytag: member="alu::mult_div_sign" ref="abbf525422eca0279b697f742b90237e0" args="wire" -->
|
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alfik |
<div class="memitem">
|
| 1048 |
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<div class="memproto">
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| 1049 |
|
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<table class="memname">
|
| 1050 |
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<tr>
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| 1051 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#abbf525422eca0279b697f742b90237e0">mult_div_sign</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
|
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12 |
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</tr>
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| 1053 |
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</table>
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</div>
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<div class="memdoc">
|
| 1056 |
|
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|
| 1057 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02623">2623</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1058 |
12 |
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|
| 1059 |
|
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</div>
|
| 1060 |
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</div>
|
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13 |
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<a class="anchor" id="a01e7473ea866a8cc46912bc69b59f8b0"></a><!-- doxytag: member="alu::div_count" ref="a01e7473ea866a8cc46912bc69b59f8b0" args="reg[4:0]" -->
|
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<div class="memitem">
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<div class="memproto">
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| 1064 |
|
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<table class="memname">
|
| 1065 |
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<tr>
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13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a01e7473ea866a8cc46912bc69b59f8b0">div_count</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[4:0]]</code></td>
|
| 1067 |
12 |
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</tr>
|
| 1068 |
|
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</table>
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| 1069 |
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</div>
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| 1070 |
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<div class="memdoc">
|
| 1071 |
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|
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13 |
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02626">2626</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
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12 |
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| 1074 |
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</div>
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| 1075 |
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</div>
|
| 1076 |
13 |
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<a class="anchor" id="ab225284f49794091a5a28e73b8b13e14"></a><!-- doxytag: member="alu::quotient" ref="ab225284f49794091a5a28e73b8b13e14" args="reg[16:0]" -->
|
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<div class="memitem">
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<div class="memproto">
|
| 1079 |
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<table class="memname">
|
| 1080 |
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alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ab225284f49794091a5a28e73b8b13e14">quotient</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[16:0]]</code></td>
|
| 1082 |
12 |
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</tr>
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| 1083 |
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</table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02627">2627</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1088 |
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| 1089 |
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</div>
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| 1090 |
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</div>
|
| 1091 |
13 |
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<a class="anchor" id="a0c2a64b2f5dd32b2159ca0f29de360aa"></a><!-- doxytag: member="alu::dividend" ref="a0c2a64b2f5dd32b2159ca0f29de360aa" args="reg[31:0]" -->
|
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<div class="memitem">
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a0c2a64b2f5dd32b2159ca0f29de360aa">dividend</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[31:0]]</code></td>
|
| 1097 |
12 |
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</tr>
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</table>
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</div>
|
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<div class="memdoc">
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| 1101 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02628">2628</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1103 |
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| 1104 |
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</div>
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| 1105 |
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</div>
|
| 1106 |
13 |
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<a class="anchor" id="a9c2364593889150d7f5679fc33b0f1fa"></a><!-- doxytag: member="alu::divider" ref="a9c2364593889150d7f5679fc33b0f1fa" args="reg[31:0]" -->
|
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a9c2364593889150d7f5679fc33b0f1fa">divider</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[31:0]]</code></td>
|
| 1112 |
12 |
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</tr>
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| 1113 |
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</table>
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| 1114 |
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</div>
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<div class="memdoc">
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| 1116 |
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13 |
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02628">2628</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1118 |
12 |
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| 1119 |
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</div>
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| 1120 |
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</div>
|
| 1121 |
13 |
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<a class="anchor" id="a07af2646e5b543c5be95dddb22fd4ea6"></a><!-- doxytag: member="alu::div_diff" ref="a07af2646e5b543c5be95dddb22fd4ea6" args="wire[32:0]" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a07af2646e5b543c5be95dddb22fd4ea6">div_diff</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[32:0]]</code></td>
|
| 1127 |
12 |
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</tr>
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| 1128 |
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</table>
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| 1129 |
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</div>
|
| 1130 |
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<div class="memdoc">
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| 1131 |
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02631">2631</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1133 |
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| 1134 |
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</div>
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| 1135 |
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</div>
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| 1136 |
13 |
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<a class="anchor" id="a8d11b113e74362e74035541da1b0a02e"></a><!-- doxytag: member="alu::div_overflow" ref="a8d11b113e74362e74035541da1b0a02e" args="wire" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a8d11b113e74362e74035541da1b0a02e">div_overflow</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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| 1142 |
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</tr>
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| 1143 |
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</table>
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| 1144 |
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</div>
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<div class="memdoc">
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| 1146 |
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02634">2634</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1149 |
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</div>
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| 1150 |
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</div>
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| 1151 |
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<a class="anchor" id="af65ee78a38f09889c3b8c9efc759f559"></a><!-- doxytag: member="alu::div_quotient" ref="af65ee78a38f09889c3b8c9efc759f559" args="wire[15:0]" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#af65ee78a38f09889c3b8c9efc759f559">div_quotient</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[15:0]]</code></td>
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</tr>
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| 1158 |
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</table>
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</div>
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| 1160 |
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<div class="memdoc">
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| 1161 |
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02640">2640</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1163 |
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| 1164 |
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</div>
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| 1165 |
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</div>
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| 1166 |
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<a class="anchor" id="ad32bb10563baa2d2d78c2a23e8f2219e"></a><!-- doxytag: member="alu::div_remainder" ref="ad32bb10563baa2d2d78c2a23e8f2219e" args="wire[15:0]" -->
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<div class="memitem">
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ad32bb10563baa2d2d78c2a23e8f2219e">div_remainder</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[15:0]]</code></td>
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| 1172 |
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</tr>
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</table>
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</div>
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| 1175 |
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<div class="memdoc">
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| 1176 |
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02646">2646</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1178 |
12 |
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| 1179 |
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</div>
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| 1180 |
|
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</div>
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| 1181 |
13 |
alfik |
<a class="anchor" id="aff5530027f36561324e060e703004b6b"></a><!-- doxytag: member="alu::mult_result" ref="aff5530027f36561324e060e703004b6b" args="wire[33:0]" -->
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<div class="memitem">
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| 1183 |
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<div class="memproto">
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#aff5530027f36561324e060e703004b6b">mult_result</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[33:0]]</code></td>
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</tr>
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| 1188 |
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</table>
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| 1189 |
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</div>
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| 1190 |
|
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<div class="memdoc">
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| 1191 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02743">2743</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1193 |
12 |
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| 1194 |
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</div>
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| 1195 |
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</div>
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| 1196 |
13 |
alfik |
<a class="anchor" id="ab6caa4c83db93eebe29133a1ce68435e"></a><!-- doxytag: member="alu::interrupt_mask_copy" ref="ab6caa4c83db93eebe29133a1ce68435e" args="reg[2:0]" -->
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<div class="memitem">
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<div class="memproto">
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| 1199 |
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ab6caa4c83db93eebe29133a1ce68435e">interrupt_mask_copy</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[2:0]]</code></td>
|
| 1202 |
12 |
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</tr>
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| 1204 |
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</div>
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| 1205 |
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<div class="memdoc">
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| 1206 |
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02804">2804</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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12 |
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| 1209 |
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</div>
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| 1210 |
|
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</div>
|
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13 |
alfik |
<a class="anchor" id="afbfdb3d9663bb0dbde8f5ad7af046b27"></a><!-- doxytag: member="alu::was_interrupt" ref="afbfdb3d9663bb0dbde8f5ad7af046b27" args="reg" -->
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<table class="memname">
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alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#afbfdb3d9663bb0dbde8f5ad7af046b27">was_interrupt</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg]</code></td>
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| 1217 |
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02805">2805</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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12 |
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| 1224 |
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</div>
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</div>
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13 |
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<a class="anchor" id="a09fdad5ef76ddc7865c6e3a9cfc09123"></a><!-- doxytag: member="alu::Dm" ref="a09fdad5ef76ddc7865c6e3a9cfc09123" args="((size[0]==1'b1)?operand1[7]:(size[1]==1'b1)?operand1[15]:operand1[31])" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">Dm</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02796">2796</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a6447478386a93e0306b7cb09937c23c3"></a><!-- doxytag: member="alu::lpm_mult" ref="a6447478386a93e0306b7cb09937c23c3" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a6447478386a93e0306b7cb09937c23c3">lpm_mult</a></span> <b><span class="vhdlchar">muls</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02745">2745</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a942f3773659fb9e9e38101743237144a"></a><!-- doxytag: member="alu::Rm" ref="a942f3773659fb9e9e38101743237144a" args="((size[0]==1'b1)?result[7]:(size[1]==1'b1)?result[15]:result[31])" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a942f3773659fb9e9e38101743237144a">Rm</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02798">2798</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a52a04e7012270413af6cecfc29ce720a"></a><!-- doxytag: member="alu::Sm" ref="a52a04e7012270413af6cecfc29ce720a" args="((size[0]==1'b1)?operand2[7]:(size[1]==1'b1)?operand2[15]:operand2[31])" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">Sm</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02794">2794</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ac5469ea2de38c1332c5a56b6b6242d55"></a><!-- doxytag: member="alu::Z" ref="ac5469ea2de38c1332c5a56b6b6242d55" args="((size[0]==1'b1)?(result[7:0]==8'b0):(size[1]==1'b1)?(result[15:0]==16'b0):(result[31:0]==32'b0))" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">Z</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02800">2800</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
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<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li>
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:45:29 for ao68000 by 
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<a href="http://www.doxygen.org/index.html">
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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