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<title>ao68000: alu Module Reference</title>
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<div class="summary">
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<a href="#Inputs">Inputs</a> |
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<a href="#Outputs">Outputs</a> |
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<a href="#Signals">Signals</a> |
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<a href="#Module Instances">Module Instances</a> |
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<a href="#Defines">Defines</a> |
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<a href="#Always Constructs">Always Constructs</a> </div>
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<div class="headertitle">
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<h1>alu Module Reference</h1> </div>
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</div>
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<div class="contents">
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<!-- doxytag: class="alu" -->
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<p>Arithmetic and Logic Unit.
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<a href="#_details">More...</a></p>
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Inheritance diagram for alu:<!-- endSectionHeader --></div>
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</div><!-- endSectionContent --></div>
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<p><a href="classalu-members.html">List of all members.</a></p>
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<table class="memberdecls">
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<tr><td colspan="2"><h2><a name="Always Constructs"></a>
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Always Constructs</h2></td></tr>
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alfik |
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a04b10dc82e8a06c3856bfd16a7e18d06">ALWAYS_31</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classalu.html#a322325f3e53ea8e7d70fbdc7f5d1b30b">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classalu.html#a2f01d99d4de620b6ce6c7c0a150a5fab">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a5c48a82153e9796a3913029cde0cc182">ALWAYS_32</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classalu.html#a322325f3e53ea8e7d70fbdc7f5d1b30b">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classalu.html#a2f01d99d4de620b6ce6c7c0a150a5fab">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td colspan="2"><h2><a name="Defines"></a>
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Defines</h2></td></tr>
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16 |
alfik |
<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">Sm</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand2</span><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand2</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><b><a class="el" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">]</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
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<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">Dm</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand1</span><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?operand1</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><b><a class="el" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">]</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
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| 63 |
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<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#a942f3773659fb9e9e38101743237144a">Rm</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?result</span><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?result</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">]</span><span class="vhdlchar">:</span><b><a class="el" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">]</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
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| 64 |
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<tr><td class="memTemplParams" colspan="2"><b><a class="el" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">Z</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">(</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">8'b0</span><span class="vhdlchar">)</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">1'b1</span><span class="vhdlchar">)</span><span class="vhdlchar">?</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">16'b0</span><span class="vhdlchar">)</span><span class="vhdlchar">:</span><span class="vhdlchar">(</span><b><a class="el" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a></b> <span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar">=</span><span class="vhdlchar">=</span><span class="vhdldigit">32'b0</span><span class="vhdlchar">)</span><span class="vhdlchar">)</span><span class="vhdlchar"> </span></b></b></td></tr>
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<tr><td colspan="2"><h2><a name="Inputs"></a>
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Inputs</h2></td></tr>
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16 |
alfik |
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a322325f3e53ea8e7d70fbdc7f5d1b30b">clock</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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| 68 |
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a2f01d99d4de620b6ce6c7c0a150a5fab">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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| 69 |
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a5a9e1012e0cf7d30a4a4dcaf5486693c">address</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#ab8bac09f28bae473ebf96e3c2c7e2806">interrupt_mask</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#abd96864c4534e2905f0ac629d1bcfce1">alu_control</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">17</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td colspan="2"><h2><a name="Outputs"></a>
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Outputs</h2></td></tr>
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16 |
alfik |
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#ad39d03bb22df22560c4f5dc796382313">alu_signal</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classalu.html#ac76782f488b9491569955793b9b37762">alu_mult_div_ready</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><h2><a name="Module Instances"></a>
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Module Instances</h2></td></tr>
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alfik |
<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classalu.html#a6447478386a93e0306b7cb09937c23c3">lpm_mult::muls</a> </b> </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><h2><a name="Signals"></a>
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Signals</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a25ae8f83a524b562fb57cd0af6dee164">mult_div_sign</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">16</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#ac5f88cdff8f17d02e28927335c6f141d">quotient</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a108916b9974c024932e1e9874589c4ba">dividend</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#ab4e5d750cf0d96eb715606c6166945cb">divider</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">32</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a2fc8379eb8a0ee027596e29d34c0fbc7">div_diff</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#abad1e1ed5e810e1a31e16550349b6bfb">div_overflow</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a66f6b0eb96212740619af0f057d33546">div_quotient</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a3b4ed364cf9180375a05991a64005ea7">div_remainder</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">33</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#ac1b8a2e6c2bb6a12b10db4250f56135e">mult_result</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a71bbcd2b437cc138ec4e56a2fb248d7e">interrupt_mask_copy</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#acd1a91ac2175444844ece34147d7baa4">was_interrupt</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#ab2b982ee64f25838bec8dba77728dfd8">lbit</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classalu.html#a8035654de9f2902808f814526db0e1bc">rbit</a> </td></tr>
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| 102 |
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</table>
|
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
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|
<p>Arithmetic and Logic Unit. </p>
|
| 105 |
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<p>The alu module is responsible for performing all of the arithmetic and logic operations of the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> processor. It operates on two 32-bit registers: operand1 and operand2 from the registers module. The output is saved into a result 32-bit register. This register is located in the alu module.</p>
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| 106 |
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<p>The alu module also contains the status register (SR) with the condition code register. The microcode decides what operation the alu performs. </p>
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| 108 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02625">2625</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 109 |
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<hr/><h2>Member Function Documentation</h2>
|
| 110 |
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<a class="anchor" id="a04b10dc82e8a06c3856bfd16a7e18d06"></a><!-- doxytag: member="alu::ALWAYS_31" ref="a04b10dc82e8a06c3856bfd16a7e18d06" args="clock, reset_n" -->
|
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<div class="memitem">
|
| 112 |
|
|
<div class="memproto">
|
| 113 |
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|
<table class="memname">
|
| 114 |
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<tr>
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| 115 |
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_31 <td></td>
|
| 116 |
|
|
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classalu.html#a322325f3e53ea8e7d70fbdc7f5d1b30b">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
|
| 117 |
12 |
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</tr>
|
| 118 |
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|
<tr>
|
| 119 |
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|
<td class="paramkey"></td>
|
| 120 |
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<td></td>
|
| 121 |
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alfik |
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classalu.html#a2f01d99d4de620b6ce6c7c0a150a5fab">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
|
| 122 |
12 |
alfik |
</tr>
|
| 123 |
|
|
<code> [Always Construct]</code></td>
|
| 124 |
|
|
</tr>
|
| 125 |
|
|
</table>
|
| 126 |
|
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</div>
|
| 127 |
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|
<div class="memdoc">
|
| 128 |
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| 129 |
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02687">2687</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 130 |
12 |
alfik |
<div class="fragment"><pre class="fragment">
|
| 131 |
16 |
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<a name="l02687"></a>02687 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classalu.html#a322325f3e53ea8e7d70fbdc7f5d1b30b">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classalu.html#a2f01d99d4de620b6ce6c7c0a150a5fab">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 132 |
|
|
<a name="l02688"></a>02688 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a2f01d99d4de620b6ce6c7c0a150a5fab">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 133 |
|
|
<a name="l02689"></a>02689 <a class="code" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a> <= <span class="vhdllogic">5'd0</span>;
|
| 134 |
|
|
<a name="l02690"></a>02690 <span class="vhdlkeyword">end</span>
|
| 135 |
|
|
<a name="l02691"></a>02691 <span class="keyword">// Cycle #0 : load the registers</span>
|
| 136 |
|
|
<a name="l02692"></a>02692 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#abd96864c4534e2905f0ac629d1bcfce1">alu_control</a> == <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> && <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a> == <span class="vhdllogic">5'd0</span>) <span class="vhdlkeyword">begin</span>
|
| 137 |
|
|
<a name="l02693"></a>02693 <span class="keyword">// 17 cycles to finish + wait state</span>
|
| 138 |
|
|
<a name="l02694"></a>02694 <a class="code" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a> <= <span class="vhdllogic">5'd18</span>;
|
| 139 |
|
|
<a name="l02695"></a>02695 <span class="keyword">// Clear the quotient</span>
|
| 140 |
|
|
<a name="l02696"></a>02696 <a class="code" href="classalu.html#ac5f88cdff8f17d02e28927335c6f141d">quotient</a> <= <span class="vhdllogic">17'd0</span>;
|
| 141 |
|
|
<a name="l02697"></a>02697
|
| 142 |
|
|
<a name="l02698"></a>02698 <span class="keyword">// Unsigned divide or positive numerator</span>
|
| 143 |
|
|
<a name="l02699"></a>02699 <span class="vhdlkeyword">if</span> ((!<a class="code" href="classalu.html#a25ae8f83a524b562fb57cd0af6dee164">mult_div_sign</a>) || (!<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>])) <a class="code" href="classalu.html#a108916b9974c024932e1e9874589c4ba">dividend</a> <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>;
|
| 144 |
|
|
<a name="l02700"></a>02700 <span class="keyword">// Negative numerator</span>
|
| 145 |
|
|
<a name="l02701"></a>02701 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#a108916b9974c024932e1e9874589c4ba">dividend</a> <= -<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>;
|
| 146 |
|
|
<a name="l02702"></a>02702
|
| 147 |
|
|
<a name="l02703"></a>02703 <span class="keyword">// Unsigned divide or positive denominator</span>
|
| 148 |
|
|
<a name="l02704"></a>02704 <span class="vhdlkeyword">if</span> ((!<a class="code" href="classalu.html#a25ae8f83a524b562fb57cd0af6dee164">mult_div_sign</a>) || (!<a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">15</span>])) <a class="code" href="classalu.html#ab4e5d750cf0d96eb715606c6166945cb">divider</a> <= {<a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>],<span class="vhdllogic">16'd0</span>};
|
| 149 |
|
|
<a name="l02705"></a>02705 <span class="keyword">// Negative denominator</span>
|
| 150 |
|
|
<a name="l02706"></a>02706 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#ab4e5d750cf0d96eb715606c6166945cb">divider</a> <= {-<a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>],<span class="vhdllogic">16'd0</span>};
|
| 151 |
|
|
<a name="l02707"></a>02707 <span class="vhdlkeyword">end</span>
|
| 152 |
|
|
<a name="l02708"></a>02708 <span class="keyword">// Cycles #1-17 : division calculation</span>
|
| 153 |
|
|
<a name="l02709"></a>02709 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a> > <span class="vhdllogic">5'd1</span>) <span class="vhdlkeyword">begin</span>
|
| 154 |
|
|
<a name="l02710"></a>02710 <span class="keyword">// Check difference's sign</span>
|
| 155 |
|
|
<a name="l02711"></a>02711 <span class="vhdlkeyword">if</span> (!<a class="code" href="classalu.html#a2fc8379eb8a0ee027596e29d34c0fbc7">div_diff</a>[<span class="vhdllogic">32</span>]) <span class="vhdlkeyword">begin</span>
|
| 156 |
|
|
<a name="l02712"></a>02712 <span class="keyword">// Difference is positive : shift a one</span>
|
| 157 |
|
|
<a name="l02713"></a>02713 <a class="code" href="classalu.html#a108916b9974c024932e1e9874589c4ba">dividend</a> <= <a class="code" href="classalu.html#a2fc8379eb8a0ee027596e29d34c0fbc7">div_diff</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 158 |
|
|
<a name="l02714"></a>02714 <a class="code" href="classalu.html#ac5f88cdff8f17d02e28927335c6f141d">quotient</a> <= {<a class="code" href="classalu.html#ac5f88cdff8f17d02e28927335c6f141d">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b1</span>};
|
| 159 |
|
|
<a name="l02715"></a>02715 <span class="vhdlkeyword">end</span>
|
| 160 |
|
|
<a name="l02716"></a>02716 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 161 |
|
|
<a name="l02717"></a>02717 <span class="keyword">// Difference is negative : shift a zero</span>
|
| 162 |
|
|
<a name="l02718"></a>02718 <a class="code" href="classalu.html#ac5f88cdff8f17d02e28927335c6f141d">quotient</a> <= {<a class="code" href="classalu.html#ac5f88cdff8f17d02e28927335c6f141d">quotient</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">1'b0</span>};
|
| 163 |
|
|
<a name="l02719"></a>02719 <span class="vhdlkeyword">end</span>
|
| 164 |
|
|
<a name="l02720"></a>02720 <span class="keyword">// Shift right divider</span>
|
| 165 |
|
|
<a name="l02721"></a>02721 <a class="code" href="classalu.html#ab4e5d750cf0d96eb715606c6166945cb">divider</a> <= {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#ab4e5d750cf0d96eb715606c6166945cb">divider</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">1</span>]};
|
| 166 |
|
|
<a name="l02722"></a>02722 <span class="keyword">// Count one bit</span>
|
| 167 |
|
|
<a name="l02723"></a>02723 <a class="code" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a> <= <a class="code" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a> - <span class="vhdllogic">5'd1</span>;
|
| 168 |
|
|
<a name="l02724"></a>02724 <span class="vhdlkeyword">end</span>
|
| 169 |
|
|
<a name="l02725"></a>02725 <span class="keyword">// result read</span>
|
| 170 |
|
|
<a name="l02726"></a>02726 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#abd96864c4534e2905f0ac629d1bcfce1">alu_control</a> == <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span> && <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a> == <span class="vhdllogic">5'd1</span>) <span class="vhdlkeyword">begin</span>
|
| 171 |
|
|
<a name="l02727"></a>02727 <span class="keyword">// goto idle</span>
|
| 172 |
|
|
<a name="l02728"></a>02728 <a class="code" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a> <= <a class="code" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a> - <span class="vhdllogic">5'd1</span>;
|
| 173 |
|
|
<a name="l02729"></a>02729 <span class="vhdlkeyword">end</span>
|
| 174 |
|
|
<a name="l02730"></a>02730 <span class="vhdlkeyword">end</span>
|
| 175 |
13 |
alfik |
</pre></div>
|
| 176 |
|
|
</div>
|
| 177 |
|
|
</div>
|
| 178 |
16 |
alfik |
<a class="anchor" id="a5c48a82153e9796a3913029cde0cc182"></a><!-- doxytag: member="alu::ALWAYS_32" ref="a5c48a82153e9796a3913029cde0cc182" args="clock, reset_n" -->
|
| 179 |
13 |
alfik |
<div class="memitem">
|
| 180 |
|
|
<div class="memproto">
|
| 181 |
|
|
<table class="memname">
|
| 182 |
|
|
<tr>
|
| 183 |
16 |
alfik |
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_32 <td></td>
|
| 184 |
|
|
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classalu.html#a322325f3e53ea8e7d70fbdc7f5d1b30b">clock</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
|
| 185 |
13 |
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</tr>
|
| 186 |
|
|
<tr>
|
| 187 |
|
|
<td class="paramkey"></td>
|
| 188 |
|
|
<td></td>
|
| 189 |
16 |
alfik |
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classalu.html#a2f01d99d4de620b6ce6c7c0a150a5fab">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
|
| 190 |
13 |
alfik |
</tr>
|
| 191 |
|
|
<code> [Always Construct]</code></td>
|
| 192 |
|
|
</tr>
|
| 193 |
|
|
</table>
|
| 194 |
|
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</div>
|
| 195 |
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<div class="memdoc">
|
| 196 |
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| 197 |
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02773">2773</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 198 |
13 |
alfik |
<div class="fragment"><pre class="fragment">
|
| 199 |
16 |
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<a name="l02773"></a>02773 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classalu.html#a322325f3e53ea8e7d70fbdc7f5d1b30b">clock</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classalu.html#a2f01d99d4de620b6ce6c7c0a150a5fab">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 200 |
|
|
<a name="l02774"></a>02774 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a2f01d99d4de620b6ce6c7c0a150a5fab">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 201 |
|
|
<a name="l02775"></a>02775 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a> <= { <span class="vhdllogic">1'b0</span>, <span class="vhdllogic">1'b0</span>, <span class="vhdllogic">1'b1</span>, <span class="vhdllogic">2'b0</span>, <span class="vhdllogic">3'b111</span>, <span class="vhdllogic">8'b0</span> };
|
| 202 |
|
|
<a name="l02776"></a>02776 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> <= <span class="vhdllogic">32'd0</span>;
|
| 203 |
|
|
<a name="l02777"></a>02777 <a class="code" href="classalu.html#ad39d03bb22df22560c4f5dc796382313">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 204 |
|
|
<a name="l02778"></a>02778 <a class="code" href="classalu.html#a71bbcd2b437cc138ec4e56a2fb248d7e">interrupt_mask_copy</a> <= <span class="vhdllogic">3'b0</span>;
|
| 205 |
|
|
<a name="l02779"></a>02779 <a class="code" href="classalu.html#acd1a91ac2175444844ece34147d7baa4">was_interrupt</a> <= <span class="vhdllogic">1'b0</span>;
|
| 206 |
|
|
<a name="l02780"></a>02780 <span class="vhdlkeyword">end</span>
|
| 207 |
|
|
<a name="l02781"></a>02781 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 208 |
|
|
<a name="l02782"></a>02782 <span class="vhdlkeyword">case</span>(<a class="code" href="classalu.html#abd96864c4534e2905f0ac629d1bcfce1">alu_control</a>)
|
| 209 |
|
|
<a name="l02783"></a>02783 <a class="code" href="ao68000_8v.html#a687e6310453b4cedb64aa6e66b058c18">`ALU_SR_SET_INTERRUPT</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 210 |
|
|
<a name="l02784"></a>02784 <a class="code" href="classalu.html#a71bbcd2b437cc138ec4e56a2fb248d7e">interrupt_mask_copy</a> <= <a class="code" href="classalu.html#ab8bac09f28bae473ebf96e3c2c7e2806">interrupt_mask</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>];
|
| 211 |
|
|
<a name="l02785"></a>02785 <a class="code" href="classalu.html#acd1a91ac2175444844ece34147d7baa4">was_interrupt</a> <= <span class="vhdllogic">1'b1</span>;
|
| 212 |
|
|
<a name="l02786"></a>02786 <span class="vhdlkeyword">end</span>
|
| 213 |
|
|
<a name="l02787"></a>02787
|
| 214 |
|
|
<a name="l02788"></a>02788 <a class="code" href="ao68000_8v.html#ac9fc44b8d3bbcd6c742f1ba074fc668d">`ALU_SR_SET_TRAP</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 215 |
|
|
<a name="l02789"></a>02789 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#acd1a91ac2175444844ece34147d7baa4">was_interrupt</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 216 |
|
|
<a name="l02790"></a>02790 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">14</span>], <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">12</span>:<span class="vhdllogic">11</span>], <a class="code" href="classalu.html#a71bbcd2b437cc138ec4e56a2fb248d7e">interrupt_mask_copy</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 217 |
|
|
<a name="l02791"></a>02791 <span class="vhdlkeyword">end</span>
|
| 218 |
|
|
<a name="l02792"></a>02792 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 219 |
|
|
<a name="l02793"></a>02793 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a> <= { <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">14</span>], <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">12</span>:<span class="vhdllogic">0</span>] };
|
| 220 |
|
|
<a name="l02794"></a>02794 <span class="vhdlkeyword">end</span>
|
| 221 |
|
|
<a name="l02795"></a>02795 <a class="code" href="classalu.html#acd1a91ac2175444844ece34147d7baa4">was_interrupt</a> <= <span class="vhdllogic">1'b0</span>;
|
| 222 |
|
|
<a name="l02796"></a>02796 <span class="vhdlkeyword">end</span>
|
| 223 |
|
|
<a name="l02797"></a>02797
|
| 224 |
|
|
<a name="l02798"></a>02798 <a class="code" href="ao68000_8v.html#a59147ff996e0ba496f1f06d7a06decae">`ALU_MOVEP_M2R_1</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 225 |
|
|
<a name="l02799"></a>02799 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 226 |
|
|
<a name="l02800"></a>02800 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 227 |
|
|
<a name="l02801"></a>02801 <span class="keyword">//CCR: no change</span>
|
| 228 |
|
|
<a name="l02802"></a>02802 <span class="vhdlkeyword">end</span>
|
| 229 |
|
|
<a name="l02803"></a>02803 <a class="code" href="ao68000_8v.html#a3b1155f3496b0fc984e5418e09586bf5">`ALU_MOVEP_M2R_2</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 230 |
|
|
<a name="l02804"></a>02804 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 231 |
|
|
<a name="l02805"></a>02805 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 232 |
|
|
<a name="l02806"></a>02806 <span class="keyword">//CCR: no change</span>
|
| 233 |
|
|
<a name="l02807"></a>02807 <span class="vhdlkeyword">end</span>
|
| 234 |
|
|
<a name="l02808"></a>02808 <a class="code" href="ao68000_8v.html#a5458c8548afc8f7517bdc582c9946b2f">`ALU_MOVEP_M2R_3</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 235 |
|
|
<a name="l02809"></a>02809 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 236 |
|
|
<a name="l02810"></a>02810 <span class="keyword">//CCR: no change</span>
|
| 237 |
|
|
<a name="l02811"></a>02811 <span class="vhdlkeyword">end</span>
|
| 238 |
|
|
<a name="l02812"></a>02812 <a class="code" href="ao68000_8v.html#a8ec0074ca9c5cfec15aa93b92353e09b">`ALU_MOVEP_M2R_4</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 239 |
|
|
<a name="l02813"></a>02813 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 240 |
|
|
<a name="l02814"></a>02814 <span class="keyword">//CCR: no change</span>
|
| 241 |
|
|
<a name="l02815"></a>02815 <span class="vhdlkeyword">end</span>
|
| 242 |
|
|
<a name="l02816"></a>02816
|
| 243 |
|
|
<a name="l02817"></a>02817
|
| 244 |
|
|
<a name="l02818"></a>02818 <a class="code" href="ao68000_8v.html#aab7548aba43c6c12259a2a154ce2982b">`ALU_MOVEP_R2M_1</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 245 |
|
|
<a name="l02819"></a>02819 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>];
|
| 246 |
|
|
<a name="l02820"></a>02820 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>];
|
| 247 |
|
|
<a name="l02821"></a>02821 <span class="keyword">// CCR: no change</span>
|
| 248 |
|
|
<a name="l02822"></a>02822 <span class="vhdlkeyword">end</span>
|
| 249 |
|
|
<a name="l02823"></a>02823 <a class="code" href="ao68000_8v.html#a9918f4663f481092da549f3cb008721d">`ALU_MOVEP_R2M_2</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 250 |
|
|
<a name="l02824"></a>02824 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">6</span>] == <span class="vhdllogic">1'b1</span>) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>];
|
| 251 |
|
|
<a name="l02825"></a>02825 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 252 |
|
|
<a name="l02826"></a>02826 <span class="keyword">// CCR: no change</span>
|
| 253 |
|
|
<a name="l02827"></a>02827 <span class="vhdlkeyword">end</span>
|
| 254 |
|
|
<a name="l02828"></a>02828 <a class="code" href="ao68000_8v.html#aee5fc91f58c97ffa4d252e127c9e4226">`ALU_MOVEP_R2M_3</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 255 |
|
|
<a name="l02829"></a>02829 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>];
|
| 256 |
|
|
<a name="l02830"></a>02830 <span class="keyword">// CCR: no change</span>
|
| 257 |
|
|
<a name="l02831"></a>02831 <span class="vhdlkeyword">end</span>
|
| 258 |
|
|
<a name="l02832"></a>02832 <a class="code" href="ao68000_8v.html#a0bc85184fda7b9fcbf00afa29be91d42">`ALU_MOVEP_R2M_4</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 259 |
|
|
<a name="l02833"></a>02833 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 260 |
|
|
<a name="l02834"></a>02834 <span class="keyword">// CCR: no change</span>
|
| 261 |
|
|
<a name="l02835"></a>02835 <span class="vhdlkeyword">end</span>
|
| 262 |
|
|
<a name="l02836"></a>02836
|
| 263 |
|
|
<a name="l02837"></a>02837 <a class="code" href="ao68000_8v.html#a6a119b7268e4e0a78e0307ba0c693ccb">`ALU_SIGN_EXTEND</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 264 |
|
|
<a name="l02838"></a>02838 <span class="keyword">// move operand1 with sign-extension to result</span>
|
| 265 |
|
|
<a name="l02839"></a>02839 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 266 |
|
|
<a name="l02840"></a>02840 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
| 267 |
|
|
<a name="l02841"></a>02841 <span class="vhdlkeyword">end</span>
|
| 268 |
|
|
<a name="l02842"></a>02842 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 269 |
|
|
<a name="l02843"></a>02843 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>;
|
| 270 |
|
|
<a name="l02844"></a>02844 <span class="vhdlkeyword">end</span>
|
| 271 |
|
|
<a name="l02845"></a>02845 <span class="keyword">// CCR: no change</span>
|
| 272 |
|
|
<a name="l02846"></a>02846 <span class="vhdlkeyword">end</span>
|
| 273 |
|
|
<a name="l02847"></a>02847
|
| 274 |
|
|
<a name="l02848"></a>02848 <a class="code" href="ao68000_8v.html#ae497ab0b3e0550245c333bdb426d4236">`ALU_ARITHMETIC_LOGIC</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 275 |
|
|
<a name="l02849"></a>02849
|
| 276 |
|
|
<a name="l02850"></a>02850 <span class="keyword">// OR,OR to mem,OR to Dn</span>
|
| 277 |
|
|
<a name="l02851"></a>02851 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">0</span>]) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] | <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 278 |
|
|
<a name="l02852"></a>02852 <span class="keyword">// AND,AND to mem,AND to Dn</span>
|
| 279 |
|
|
<a name="l02853"></a>02853 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">1</span>]) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] & <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 280 |
|
|
<a name="l02854"></a>02854 <span class="keyword">// EORI,EOR</span>
|
| 281 |
|
|
<a name="l02855"></a>02855 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">2</span>]) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] ^ <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 282 |
|
|
<a name="l02856"></a>02856 <span class="keyword">// ADD,ADD to mem,ADD to Dn,ADDQ</span>
|
| 283 |
|
|
<a name="l02857"></a>02857 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">3</span>]) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 284 |
|
|
<a name="l02858"></a>02858 <span class="keyword">// SUBI,CMPI,CMPM,SUB to mem,SUB to Dn,CMP,SUBQ</span>
|
| 285 |
|
|
<a name="l02859"></a>02859 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">4</span>] | <a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">5</span>]) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 286 |
|
|
<a name="l02860"></a>02860
|
| 287 |
|
|
<a name="l02861"></a>02861 <span class="keyword">// Z</span>
|
| 288 |
|
|
<a name="l02862"></a>02862 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 289 |
|
|
<a name="l02863"></a>02863 <span class="keyword">// N</span>
|
| 290 |
|
|
<a name="l02864"></a>02864 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 291 |
|
|
<a name="l02865"></a>02865
|
| 292 |
|
|
<a name="l02866"></a>02866 <span class="keyword">// CMPI,CMPM,CMP</span>
|
| 293 |
|
|
<a name="l02867"></a>02867 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">5</span>]) <span class="vhdlkeyword">begin</span>
|
| 294 |
|
|
<a name="l02868"></a>02868 <span class="keyword">// C,V</span>
|
| 295 |
|
|
<a name="l02869"></a>02869 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 296 |
|
|
<a name="l02870"></a>02870 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 297 |
|
|
<a name="l02871"></a>02871 <span class="keyword">// X not affected</span>
|
| 298 |
|
|
<a name="l02872"></a>02872 <span class="vhdlkeyword">end</span>
|
| 299 |
|
|
<a name="l02873"></a>02873 <span class="keyword">// ADDI,ADD to mem,ADD to Dn,ADDQ</span>
|
| 300 |
|
|
<a name="l02874"></a>02874 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">3</span>]) <span class="vhdlkeyword">begin</span>
|
| 301 |
|
|
<a name="l02875"></a>02875 <span class="keyword">// C,X,V</span>
|
| 302 |
|
|
<a name="l02876"></a>02876 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 303 |
|
|
<a name="l02877"></a>02877 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 304 |
|
|
<a name="l02878"></a>02878 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 305 |
|
|
<a name="l02879"></a>02879 <span class="vhdlkeyword">end</span>
|
| 306 |
|
|
<a name="l02880"></a>02880 <span class="keyword">// SUBI,SUB to mem,SUB to Dn,SUBQ</span>
|
| 307 |
|
|
<a name="l02881"></a>02881 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">4</span>]) <span class="vhdlkeyword">begin</span>
|
| 308 |
|
|
<a name="l02882"></a>02882 <span class="keyword">// C,X,V</span>
|
| 309 |
|
|
<a name="l02883"></a>02883 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 310 |
|
|
<a name="l02884"></a>02884 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 311 |
|
|
<a name="l02885"></a>02885 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 312 |
|
|
<a name="l02886"></a>02886 <span class="vhdlkeyword">end</span>
|
| 313 |
|
|
<a name="l02887"></a>02887 <span class="keyword">// ANDI,EORI,ORI,EOR,OR to mem,AND to mem,OR to Dn,AND to Dn</span>
|
| 314 |
|
|
<a name="l02888"></a>02888 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 315 |
|
|
<a name="l02889"></a>02889 <span class="keyword">// C,V</span>
|
| 316 |
|
|
<a name="l02890"></a>02890 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 317 |
|
|
<a name="l02891"></a>02891 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 318 |
|
|
<a name="l02892"></a>02892 <span class="keyword">// X not affected</span>
|
| 319 |
|
|
<a name="l02893"></a>02893 <span class="vhdlkeyword">end</span>
|
| 320 |
|
|
<a name="l02894"></a>02894 <span class="vhdlkeyword">end</span>
|
| 321 |
|
|
<a name="l02895"></a>02895
|
| 322 |
|
|
<a name="l02896"></a>02896 <a class="code" href="ao68000_8v.html#a3e54001e73374bd4f7cfda3de55bd944">`ALU_ABCD_SBCD_ADDX_SUBX</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span> <span class="keyword">// 259 LE</span>
|
| 323 |
|
|
<a name="l02897"></a>02897 <span class="keyword">// ABCD</span>
|
| 324 |
|
|
<a name="l02898"></a>02898 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b100</span> ) <span class="vhdlkeyword">begin</span>
|
| 325 |
|
|
<a name="l02899"></a>02899 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} + {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} + {<span class="vhdllogic">4'b0</span>, <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>]};
|
| 326 |
|
|
<a name="l02900"></a>02900 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]} + {<span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]};
|
| 327 |
|
|
<a name="l02901"></a>02901
|
| 328 |
|
|
<a name="l02902"></a>02902 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">23</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] + {<span class="vhdllogic">7'b0</span>, <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>]};
|
| 329 |
|
|
<a name="l02903"></a>02903
|
| 330 |
|
|
<a name="l02904"></a>02904 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'd9</span>) ? (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] + <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>];
|
| 331 |
|
|
<a name="l02905"></a>02905 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'h1F</span>) ? (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd2</span>) :
|
| 332 |
|
|
<a name="l02906"></a>02906 (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] > <span class="vhdllogic">6'h0F</span>) ? (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd1</span>) :
|
| 333 |
|
|
<a name="l02907"></a>02907 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 334 |
|
|
<a name="l02908"></a>02908 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] + <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 335 |
|
|
<a name="l02909"></a>02909
|
| 336 |
|
|
<a name="l02910"></a>02910 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">17</span>:<span class="vhdllogic">14</span>];
|
| 337 |
|
|
<a name="l02911"></a>02911 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>];
|
| 338 |
|
|
<a name="l02912"></a>02912
|
| 339 |
|
|
<a name="l02913"></a>02913 <span class="keyword">// C</span>
|
| 340 |
|
|
<a name="l02914"></a>02914 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 341 |
|
|
<a name="l02915"></a>02915 <span class="keyword">// X = C</span>
|
| 342 |
|
|
<a name="l02916"></a>02916 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] > <span class="vhdllogic">6'd9</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 343 |
|
|
<a name="l02917"></a>02917
|
| 344 |
|
|
<a name="l02918"></a>02918 <span class="keyword">// V</span>
|
| 345 |
|
|
<a name="l02919"></a>02919 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">30</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 346 |
|
|
<a name="l02920"></a>02920 <span class="vhdlkeyword">end</span>
|
| 347 |
|
|
<a name="l02921"></a>02921 <span class="keyword">// SBCD</span>
|
| 348 |
|
|
<a name="l02922"></a>02922 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
| 349 |
|
|
<a name="l02923"></a>02923 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = <span class="vhdllogic">6'd32</span> + {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} - {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>]} - {<span class="vhdllogic">5'b0</span>, <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>]};
|
| 350 |
|
|
<a name="l02924"></a>02924 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = <span class="vhdllogic">6'd32</span> + {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]} - {<span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]};
|
| 351 |
|
|
<a name="l02925"></a>02925
|
| 352 |
|
|
<a name="l02926"></a>02926 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">23</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] - {<span class="vhdllogic">7'b0</span>, <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>]};
|
| 353 |
|
|
<a name="l02927"></a>02927
|
| 354 |
|
|
<a name="l02928"></a>02928 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] = (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd32</span>) ? (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] - <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>];
|
| 355 |
|
|
<a name="l02929"></a>02929 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd16</span>) ? (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd2</span>) :
|
| 356 |
|
|
<a name="l02930"></a>02930 (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">13</span>:<span class="vhdllogic">8</span>] < <span class="vhdllogic">6'd32</span>) ? (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd1</span>) :
|
| 357 |
|
|
<a name="l02931"></a>02931 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 358 |
|
|
<a name="l02932"></a>02932 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] = (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span> && <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>] == <span class="vhdllogic">1'b1</span>) ? (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] - <span class="vhdllogic">6'd6</span>) : <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>];
|
| 359 |
|
|
<a name="l02933"></a>02933
|
| 360 |
|
|
<a name="l02934"></a>02934 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">17</span>:<span class="vhdllogic">14</span>];
|
| 361 |
|
|
<a name="l02935"></a>02935 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>];
|
| 362 |
|
|
<a name="l02936"></a>02936
|
| 363 |
|
|
<a name="l02937"></a>02937 <span class="keyword">// C</span>
|
| 364 |
|
|
<a name="l02938"></a>02938 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 365 |
|
|
<a name="l02939"></a>02939 <span class="keyword">// X = C</span>
|
| 366 |
|
|
<a name="l02940"></a>02940 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">19</span>:<span class="vhdllogic">14</span>] < <span class="vhdllogic">6'd32</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 367 |
|
|
<a name="l02941"></a>02941
|
| 368 |
|
|
<a name="l02942"></a>02942 <span class="keyword">// V</span>
|
| 369 |
|
|
<a name="l02943"></a>02943 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">30</span>] == <span class="vhdllogic">1'b1</span> && <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b1</span> : <span class="vhdllogic">1'b0</span>;
|
| 370 |
|
|
<a name="l02944"></a>02944 <span class="vhdlkeyword">end</span>
|
| 371 |
|
|
<a name="l02945"></a>02945 <span class="keyword">// ADDX</span>
|
| 372 |
|
|
<a name="l02946"></a>02946 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b101</span> ) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>];
|
| 373 |
|
|
<a name="l02947"></a>02947 <span class="keyword">// SUBX</span>
|
| 374 |
|
|
<a name="l02948"></a>02948 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b001</span> ) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>];
|
| 375 |
|
|
<a name="l02949"></a>02949
|
| 376 |
|
|
<a name="l02950"></a>02950 <span class="keyword">// Z</span>
|
| 377 |
|
|
<a name="l02951"></a>02951 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 378 |
|
|
<a name="l02952"></a>02952 <span class="keyword">// N</span>
|
| 379 |
|
|
<a name="l02953"></a>02953 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 380 |
14 |
alfik |
<a name="l02954"></a>02954
|
| 381 |
16 |
alfik |
<a name="l02955"></a>02955 <span class="keyword">// ADDX</span>
|
| 382 |
|
|
<a name="l02956"></a>02956 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b101</span> ) <span class="vhdlkeyword">begin</span>
|
| 383 |
|
|
<a name="l02957"></a>02957 <span class="keyword">// C,X,V</span>
|
| 384 |
|
|
<a name="l02958"></a>02958 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 385 |
|
|
<a name="l02959"></a>02959 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 386 |
|
|
<a name="l02960"></a>02960 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 387 |
|
|
<a name="l02961"></a>02961 <span class="vhdlkeyword">end</span>
|
| 388 |
|
|
<a name="l02962"></a>02962 <span class="keyword">// SUBX</span>
|
| 389 |
|
|
<a name="l02963"></a>02963 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">3'b001</span> ) <span class="vhdlkeyword">begin</span>
|
| 390 |
|
|
<a name="l02964"></a>02964 <span class="keyword">// C,X,V</span>
|
| 391 |
|
|
<a name="l02965"></a>02965 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 392 |
|
|
<a name="l02966"></a>02966 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>); <span class="keyword">//=ccr[0];</span>
|
| 393 |
|
|
<a name="l02967"></a>02967 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 394 |
|
|
<a name="l02968"></a>02968 <span class="vhdlkeyword">end</span>
|
| 395 |
|
|
<a name="l02969"></a>02969 <span class="vhdlkeyword">end</span>
|
| 396 |
|
|
<a name="l02970"></a>02970
|
| 397 |
|
|
<a name="l02971"></a>02971 <a class="code" href="ao68000_8v.html#ac444f659b2726fd335e839dfadabbfe3">`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 398 |
|
|
<a name="l02972"></a>02972 <span class="keyword">// 32-bit load even for 8-bit and 16-bit operations</span>
|
| 399 |
|
|
<a name="l02973"></a>02973 <span class="keyword">// The extra bits will be anyway discarded during register / memory write</span>
|
| 400 |
|
|
<a name="l02974"></a>02974 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 401 |
|
|
<a name="l02975"></a>02975
|
| 402 |
|
|
<a name="l02976"></a>02976 <span class="keyword">// V cleared</span>
|
| 403 |
|
|
<a name="l02977"></a>02977 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 404 |
|
|
<a name="l02978"></a>02978 <span class="keyword">// C for ROXL,ROXR: set to X</span>
|
| 405 |
|
|
<a name="l02979"></a>02979 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">11</span>] | <a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">15</span>]) <span class="vhdlkeyword">begin</span>
|
| 406 |
|
|
<a name="l02980"></a>02980 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>];
|
| 407 |
|
|
<a name="l02981"></a>02981 <span class="vhdlkeyword">end</span>
|
| 408 |
|
|
<a name="l02982"></a>02982 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 409 |
|
|
<a name="l02983"></a>02983 <span class="keyword">// C cleared</span>
|
| 410 |
|
|
<a name="l02984"></a>02984 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 411 |
|
|
<a name="l02985"></a>02985 <span class="vhdlkeyword">end</span>
|
| 412 |
|
|
<a name="l02986"></a>02986
|
| 413 |
|
|
<a name="l02987"></a>02987 <span class="keyword">// N set</span>
|
| 414 |
|
|
<a name="l02988"></a>02988 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 415 |
|
|
<a name="l02989"></a>02989 <span class="keyword">// Z set</span>
|
| 416 |
|
|
<a name="l02990"></a>02990 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 417 |
|
|
<a name="l02991"></a>02991 <span class="vhdlkeyword">end</span>
|
| 418 |
|
|
<a name="l02992"></a>02992
|
| 419 |
|
|
<a name="l02993"></a>02993 <a class="code" href="ao68000_8v.html#ac946f278d039868214c441c11fcf2587">`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 420 |
|
|
<a name="l02994"></a>02994 <span class="keyword">// ASL / LSL / ROL / ROXL</span>
|
| 421 |
|
|
<a name="l02995"></a>02995 <span class="vhdlkeyword">if</span> (<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">8</span>] | <a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">9</span>] | <a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">10</span>] | <a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">11</span>]) <span class="vhdlkeyword">begin</span>
|
| 422 |
|
|
<a name="l02996"></a>02996 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = {<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#ab2b982ee64f25838bec8dba77728dfd8">lbit</a>};
|
| 423 |
|
|
<a name="l02997"></a>02997
|
| 424 |
|
|
<a name="l02998"></a>02998 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// C for ASL / LSL / ROL / ROXL</span>
|
| 425 |
|
|
<a name="l02999"></a>02999 <span class="vhdlkeyword">if</span> (<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">8</span>])
|
| 426 |
|
|
<a name="l03000"></a>03000 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= (<a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b0</span>)? (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> != <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) : <span class="vhdllogic">1'b1</span>; <span class="keyword">// V for ASL</span>
|
| 427 |
|
|
<a name="l03001"></a>03001 <span class="vhdlkeyword">else</span>
|
| 428 |
|
|
<a name="l03002"></a>03002 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V for LSL / ROL / ROXL</span>
|
| 429 |
|
|
<a name="l03003"></a>03003
|
| 430 |
|
|
<a name="l03004"></a>03004 <span class="vhdlkeyword">if</span> (!<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">10</span>]) <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>; <span class="keyword">// X for ASL / LSL / ROXL</span>
|
| 431 |
|
|
<a name="l03005"></a>03005 <span class="vhdlkeyword">end</span>
|
| 432 |
|
|
<a name="l03006"></a>03006 <span class="keyword">// ASR / LSR / ROR / ROXR</span>
|
| 433 |
|
|
<a name="l03007"></a>03007 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 434 |
|
|
<a name="l03008"></a>03008 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">6</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">1</span>];
|
| 435 |
|
|
<a name="l03009"></a>03009 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>] = (<a class="code" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a>[<span class="vhdllogic">0</span>]) ? <a class="code" href="classalu.html#a8035654de9f2902808f814526db0e1bc">rbit</a> : <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">8</span>];
|
| 436 |
|
|
<a name="l03010"></a>03010 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">14</span>:<span class="vhdllogic">8</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">9</span>];
|
| 437 |
|
|
<a name="l03011"></a>03011 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">15</span>] = (<a class="code" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a>[<span class="vhdllogic">1</span>]) ? <a class="code" href="classalu.html#a8035654de9f2902808f814526db0e1bc">rbit</a> : <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">16</span>];
|
| 438 |
|
|
<a name="l03012"></a>03012 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">30</span>:<span class="vhdllogic">16</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">17</span>];
|
| 439 |
|
|
<a name="l03013"></a>03013 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>] = <a class="code" href="classalu.html#a8035654de9f2902808f814526db0e1bc">rbit</a>;
|
| 440 |
|
|
<a name="l03014"></a>03014 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// C for ASR / LSR / ROR / ROXR</span>
|
| 441 |
|
|
<a name="l03015"></a>03015 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>; <span class="keyword">// V for ASR / LSR / ROR / ROXR</span>
|
| 442 |
|
|
<a name="l03016"></a>03016 <span class="vhdlkeyword">if</span> (!<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">14</span>]) <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">0</span>]; <span class="keyword">// X for ASR / LSR / ROXR</span>
|
| 443 |
|
|
<a name="l03017"></a>03017 <span class="vhdlkeyword">end</span>
|
| 444 |
|
|
<a name="l03018"></a>03018
|
| 445 |
|
|
<a name="l03019"></a>03019 <span class="keyword">// N set</span>
|
| 446 |
|
|
<a name="l03020"></a>03020 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 447 |
|
|
<a name="l03021"></a>03021 <span class="keyword">// Z set</span>
|
| 448 |
|
|
<a name="l03022"></a>03022 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 449 |
|
|
<a name="l03023"></a>03023 <span class="vhdlkeyword">end</span>
|
| 450 |
14 |
alfik |
<a name="l03024"></a>03024
|
| 451 |
16 |
alfik |
<a name="l03025"></a>03025 <a class="code" href="ao68000_8v.html#a268aa82704bd8f1c1548dfc69a12a951">`ALU_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 452 |
|
|
<a name="l03026"></a>03026 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>;
|
| 453 |
|
|
<a name="l03027"></a>03027
|
| 454 |
|
|
<a name="l03028"></a>03028 <span class="keyword">// X not affected</span>
|
| 455 |
|
|
<a name="l03029"></a>03029 <span class="keyword">// C cleared</span>
|
| 456 |
|
|
<a name="l03030"></a>03030 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 457 |
|
|
<a name="l03031"></a>03031 <span class="keyword">// V cleared</span>
|
| 458 |
|
|
<a name="l03032"></a>03032 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 459 |
|
|
<a name="l03033"></a>03033
|
| 460 |
|
|
<a name="l03034"></a>03034 <span class="keyword">// N set</span>
|
| 461 |
|
|
<a name="l03035"></a>03035 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 462 |
|
|
<a name="l03036"></a>03036 <span class="keyword">// Z set</span>
|
| 463 |
|
|
<a name="l03037"></a>03037 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 464 |
|
|
<a name="l03038"></a>03038 <span class="vhdlkeyword">end</span>
|
| 465 |
|
|
<a name="l03039"></a>03039
|
| 466 |
|
|
<a name="l03040"></a>03040 <a class="code" href="ao68000_8v.html#a30a87601d2ca38286bb0d486d59f6a07">`ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 467 |
|
|
<a name="l03041"></a>03041 <span class="keyword">// ADDA: 1101</span>
|
| 468 |
|
|
<a name="l03042"></a>03042 <span class="keyword">// CMPA: 1011</span>
|
| 469 |
|
|
<a name="l03043"></a>03043 <span class="keyword">// SUBA: 1001</span>
|
| 470 |
|
|
<a name="l03044"></a>03044 <span class="keyword">// ADDQ,SUBQ: 0101 xxx0,1</span>
|
| 471 |
|
|
<a name="l03045"></a>03045 <span class="keyword">// operation requires that operand2 was sign extended</span>
|
| 472 |
|
|
<a name="l03046"></a>03046
|
| 473 |
|
|
<a name="l03047"></a>03047 <span class="keyword">// ADDA,ADDQ</span>
|
| 474 |
|
|
<a name="l03048"></a>03048 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">6</span>]) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 475 |
|
|
<a name="l03049"></a>03049 <span class="keyword">// SUBA,CMPA,SUBQ</span>
|
| 476 |
|
|
<a name="l03050"></a>03050 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 477 |
|
|
<a name="l03051"></a>03051
|
| 478 |
|
|
<a name="l03052"></a>03052 <span class="keyword">// for CMPA</span>
|
| 479 |
|
|
<a name="l03053"></a>03053 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1011</span> ) <span class="vhdlkeyword">begin</span>
|
| 480 |
|
|
<a name="l03054"></a>03054 <span class="keyword">// Z</span>
|
| 481 |
|
|
<a name="l03055"></a>03055 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 482 |
|
|
<a name="l03056"></a>03056 <span class="keyword">// N</span>
|
| 483 |
|
|
<a name="l03057"></a>03057 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 484 |
|
|
<a name="l03058"></a>03058
|
| 485 |
|
|
<a name="l03059"></a>03059 <span class="keyword">// C,V</span>
|
| 486 |
|
|
<a name="l03060"></a>03060 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 487 |
|
|
<a name="l03061"></a>03061 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= (~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>);
|
| 488 |
|
|
<a name="l03062"></a>03062 <span class="keyword">// X not affected</span>
|
| 489 |
|
|
<a name="l03063"></a>03063 <span class="vhdlkeyword">end</span>
|
| 490 |
|
|
<a name="l03064"></a>03064 <span class="keyword">// for ADDA,SUBA,ADDQ,SUBQ: ccr not affected</span>
|
| 491 |
|
|
<a name="l03065"></a>03065 <span class="vhdlkeyword">end</span>
|
| 492 |
|
|
<a name="l03066"></a>03066
|
| 493 |
|
|
<a name="l03067"></a>03067 <a class="code" href="ao68000_8v.html#af0a4db089a5eb288abf9453ca2d79c26">`ALU_CHK</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 494 |
|
|
<a name="l03068"></a>03068 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>];
|
| 495 |
|
|
<a name="l03069"></a>03069
|
| 496 |
|
|
<a name="l03070"></a>03070 <span class="keyword">// undocumented behavior: Z flag, see 68knotes.txt</span>
|
| 497 |
|
|
<a name="l03071"></a>03071 <span class="keyword">//sr[2] <= (operand1[15:0] == 16'b0) ? 1'b1 : 1'b0;</span>
|
| 498 |
|
|
<a name="l03072"></a>03072 <span class="keyword">// undocumented behavior: C,V flags, see 68knotes.txt</span>
|
| 499 |
|
|
<a name="l03073"></a>03073 <span class="keyword">//sr[0] <= 1'b0;</span>
|
| 500 |
|
|
<a name="l03074"></a>03074 <span class="keyword">//sr[1] <= 1'b0;</span>
|
| 501 |
|
|
<a name="l03075"></a>03075
|
| 502 |
|
|
<a name="l03076"></a>03076 <span class="keyword">// C,X,V</span>
|
| 503 |
|
|
<a name="l03077"></a>03077 <span class="keyword">// sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);</span>
|
| 504 |
|
|
<a name="l03078"></a>03078 <span class="keyword">// sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];</span>
|
| 505 |
|
|
<a name="l03079"></a>03079 <span class="keyword">// sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);</span>
|
| 506 |
|
|
<a name="l03080"></a>03080 <span class="keyword">// +: 0-1, 0-0=0, 1-1=0</span>
|
| 507 |
|
|
<a name="l03081"></a>03081 <span class="keyword">// -: 0-0=1, 1-0, 1-1=1</span>
|
| 508 |
|
|
<a name="l03082"></a>03082 <span class="keyword">// operand1 - operand2 > 0</span>
|
| 509 |
|
|
<a name="l03083"></a>03083 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] != <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] && ((~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span>) | (~<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>) | (<a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">`Sm</a><span class="vhdlchar"></span> & ~<a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>)) == <span class="vhdllogic">1'b1</span> ) <span class="vhdlkeyword">begin</span>
|
| 510 |
|
|
<a name="l03084"></a>03084 <span class="keyword">// clear N</span>
|
| 511 |
|
|
<a name="l03085"></a>03085 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 512 |
|
|
<a name="l03086"></a>03086 <a class="code" href="classalu.html#ad39d03bb22df22560c4f5dc796382313">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 513 |
|
|
<a name="l03087"></a>03087 <span class="vhdlkeyword">end</span>
|
| 514 |
|
|
<a name="l03088"></a>03088 <span class="keyword">// operand1 < 0</span>
|
| 515 |
|
|
<a name="l03089"></a>03089 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span> ) <span class="vhdlkeyword">begin</span>
|
| 516 |
|
|
<a name="l03090"></a>03090 <span class="keyword">// set N</span>
|
| 517 |
|
|
<a name="l03091"></a>03091 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b1</span>;
|
| 518 |
|
|
<a name="l03092"></a>03092 <a class="code" href="classalu.html#ad39d03bb22df22560c4f5dc796382313">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 519 |
|
|
<a name="l03093"></a>03093 <span class="vhdlkeyword">end</span>
|
| 520 |
|
|
<a name="l03094"></a>03094 <span class="keyword">// no trap</span>
|
| 521 |
|
|
<a name="l03095"></a>03095 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 522 |
|
|
<a name="l03096"></a>03096 <span class="keyword">// N undefined: not affected</span>
|
| 523 |
|
|
<a name="l03097"></a>03097 <a class="code" href="classalu.html#ad39d03bb22df22560c4f5dc796382313">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 524 |
|
|
<a name="l03098"></a>03098 <span class="vhdlkeyword">end</span>
|
| 525 |
|
|
<a name="l03099"></a>03099
|
| 526 |
|
|
<a name="l03100"></a>03100 <span class="keyword">// X not affected</span>
|
| 527 |
|
|
<a name="l03101"></a>03101 <span class="vhdlkeyword">end</span>
|
| 528 |
|
|
<a name="l03102"></a>03102
|
| 529 |
|
|
<a name="l03103"></a>03103 <a class="code" href="ao68000_8v.html#aed07d190bb88f0cce7768028698020f9">`ALU_MULS_MULU_DIVS_DIVU</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 530 |
|
|
<a name="l03104"></a>03104
|
| 531 |
|
|
<a name="l03105"></a>03105 <span class="keyword">// division by 0</span>
|
| 532 |
|
|
<a name="l03106"></a>03106 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">16'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 533 |
|
|
<a name="l03107"></a>03107 <span class="keyword">// X not affected</span>
|
| 534 |
|
|
<a name="l03108"></a>03108 <span class="keyword">// C cleared</span>
|
| 535 |
|
|
<a name="l03109"></a>03109 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 536 |
|
|
<a name="l03110"></a>03110 <span class="keyword">// V,Z,N undefined: cleared</span>
|
| 537 |
|
|
<a name="l03111"></a>03111 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 538 |
|
|
<a name="l03112"></a>03112 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 539 |
|
|
<a name="l03113"></a>03113 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 540 |
|
|
<a name="l03114"></a>03114
|
| 541 |
|
|
<a name="l03115"></a>03115 <span class="keyword">// set trap</span>
|
| 542 |
|
|
<a name="l03116"></a>03116 <a class="code" href="classalu.html#ad39d03bb22df22560c4f5dc796382313">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 543 |
|
|
<a name="l03117"></a>03117 <span class="vhdlkeyword">end</span>
|
| 544 |
|
|
<a name="l03118"></a>03118 <span class="keyword">// division in idle state</span>
|
| 545 |
|
|
<a name="l03119"></a>03119 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a> == <span class="vhdllogic">5'd0</span>) <span class="vhdlkeyword">begin</span>
|
| 546 |
|
|
<a name="l03120"></a>03120 <a class="code" href="classalu.html#ad39d03bb22df22560c4f5dc796382313">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 547 |
|
|
<a name="l03121"></a>03121 <span class="vhdlkeyword">end</span>
|
| 548 |
|
|
<a name="l03122"></a>03122 <span class="keyword">// division overflow: divu, divs</span>
|
| 549 |
|
|
<a name="l03123"></a>03123 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> && <a class="code" href="classalu.html#abad1e1ed5e810e1a31e16550349b6bfb">div_overflow</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 550 |
|
|
<a name="l03124"></a>03124 <span class="keyword">// X not affected</span>
|
| 551 |
|
|
<a name="l03125"></a>03125 <span class="keyword">// C cleared</span>
|
| 552 |
|
|
<a name="l03126"></a>03126 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 553 |
|
|
<a name="l03127"></a>03127 <span class="keyword">// V set</span>
|
| 554 |
|
|
<a name="l03128"></a>03128 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b1</span>;
|
| 555 |
|
|
<a name="l03129"></a>03129 <span class="keyword">// Z,N undefined: cleared and set</span>
|
| 556 |
|
|
<a name="l03130"></a>03130 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 557 |
|
|
<a name="l03131"></a>03131 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= <span class="vhdllogic">1'b1</span>;
|
| 558 |
|
|
<a name="l03132"></a>03132
|
| 559 |
|
|
<a name="l03133"></a>03133 <span class="keyword">// set trap</span>
|
| 560 |
|
|
<a name="l03134"></a>03134 <a class="code" href="classalu.html#ad39d03bb22df22560c4f5dc796382313">alu_signal</a> <= <span class="vhdllogic">1'b1</span>;
|
| 561 |
|
|
<a name="l03135"></a>03135 <span class="vhdlkeyword">end</span>
|
| 562 |
|
|
<a name="l03136"></a>03136 <span class="keyword">// division</span>
|
| 563 |
|
|
<a name="l03137"></a>03137 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1000</span> ) <span class="vhdlkeyword">begin</span>
|
| 564 |
|
|
<a name="l03138"></a>03138 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <= {<a class="code" href="classalu.html#a3b4ed364cf9180375a05991a64005ea7">div_remainder</a>, <a class="code" href="classalu.html#a66f6b0eb96212740619af0f057d33546">div_quotient</a>};
|
| 565 |
|
|
<a name="l03139"></a>03139
|
| 566 |
|
|
<a name="l03140"></a>03140 <span class="keyword">// X not affected</span>
|
| 567 |
|
|
<a name="l03141"></a>03141 <span class="keyword">// C cleared</span>
|
| 568 |
|
|
<a name="l03142"></a>03142 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 569 |
|
|
<a name="l03143"></a>03143 <span class="keyword">// V cleared</span>
|
| 570 |
|
|
<a name="l03144"></a>03144 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 571 |
|
|
<a name="l03145"></a>03145 <span class="keyword">// Z</span>
|
| 572 |
|
|
<a name="l03146"></a>03146 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#a66f6b0eb96212740619af0f057d33546">div_quotient</a> == <span class="vhdllogic">16'b0</span>);
|
| 573 |
|
|
<a name="l03147"></a>03147 <span class="keyword">// N</span>
|
| 574 |
|
|
<a name="l03148"></a>03148 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#a66f6b0eb96212740619af0f057d33546">div_quotient</a>[<span class="vhdllogic">15</span>] == <span class="vhdllogic">1'b1</span>);
|
| 575 |
|
|
<a name="l03149"></a>03149
|
| 576 |
|
|
<a name="l03150"></a>03150 <span class="keyword">// set trap</span>
|
| 577 |
|
|
<a name="l03151"></a>03151 <a class="code" href="classalu.html#ad39d03bb22df22560c4f5dc796382313">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 578 |
|
|
<a name="l03152"></a>03152 <span class="vhdlkeyword">end</span>
|
| 579 |
|
|
<a name="l03153"></a>03153 <span class="keyword">// multiplication</span>
|
| 580 |
|
|
<a name="l03154"></a>03154 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">12</span>] == <span class="vhdllogic">4'b1100</span> ) <span class="vhdlkeyword">begin</span>
|
| 581 |
|
|
<a name="l03155"></a>03155 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#ac1b8a2e6c2bb6a12b10db4250f56135e">mult_result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 582 |
|
|
<a name="l03156"></a>03156
|
| 583 |
|
|
<a name="l03157"></a>03157 <span class="keyword">// X not affected</span>
|
| 584 |
|
|
<a name="l03158"></a>03158 <span class="keyword">// C cleared</span>
|
| 585 |
|
|
<a name="l03159"></a>03159 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 586 |
|
|
<a name="l03160"></a>03160 <span class="keyword">// V cleared</span>
|
| 587 |
|
|
<a name="l03161"></a>03161 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 588 |
|
|
<a name="l03162"></a>03162 <span class="keyword">// Z</span>
|
| 589 |
|
|
<a name="l03163"></a>03163 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#ac1b8a2e6c2bb6a12b10db4250f56135e">mult_result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">32'b0</span>);
|
| 590 |
|
|
<a name="l03164"></a>03164 <span class="keyword">// N</span>
|
| 591 |
|
|
<a name="l03165"></a>03165 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#ac1b8a2e6c2bb6a12b10db4250f56135e">mult_result</a>[<span class="vhdllogic">31</span>] == <span class="vhdllogic">1'b1</span>);
|
| 592 |
|
|
<a name="l03166"></a>03166
|
| 593 |
|
|
<a name="l03167"></a>03167 <span class="keyword">// set trap</span>
|
| 594 |
|
|
<a name="l03168"></a>03168 <a class="code" href="classalu.html#ad39d03bb22df22560c4f5dc796382313">alu_signal</a> <= <span class="vhdllogic">1'b0</span>;
|
| 595 |
|
|
<a name="l03169"></a>03169 <span class="vhdlkeyword">end</span>
|
| 596 |
|
|
<a name="l03170"></a>03170 <span class="vhdlkeyword">end</span>
|
| 597 |
|
|
<a name="l03171"></a>03171
|
| 598 |
|
|
<a name="l03172"></a>03172
|
| 599 |
|
|
<a name="l03173"></a>03173 <a class="code" href="ao68000_8v.html#a14b85ce3e5b4ede3b2c4e89f420c8c3c">`ALU_BCHG_BCLR_BSET_BTST</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span> <span class="keyword">// 97 LE</span>
|
| 600 |
|
|
<a name="l03174"></a>03174 <span class="keyword">// byte</span>
|
| 601 |
|
|
<a name="l03175"></a>03175 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] != <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
| 602 |
|
|
<a name="l03176"></a>03176 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= ~(<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[ <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ]);
|
| 603 |
|
|
<a name="l03177"></a>03177 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>;
|
| 604 |
|
|
<a name="l03178"></a>03178 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[ <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ] = (<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>) ? ~(<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[ <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">2</span>:<span class="vhdllogic">0</span>] ]) : (<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
| 605 |
|
|
<a name="l03179"></a>03179 <span class="vhdlkeyword">end</span>
|
| 606 |
|
|
<a name="l03180"></a>03180 <span class="keyword">// long</span>
|
| 607 |
|
|
<a name="l03181"></a>03181 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">5</span>:<span class="vhdllogic">3</span>] == <span class="vhdllogic">3'b000</span> ) <span class="vhdlkeyword">begin</span>
|
| 608 |
|
|
<a name="l03182"></a>03182 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= ~(<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[ <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ]);
|
| 609 |
|
|
<a name="l03183"></a>03183 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> = <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>;
|
| 610 |
|
|
<a name="l03184"></a>03184 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[ <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ] = (<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b01</span>) ? ~(<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[ <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] ]) : (<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">2'b10</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
| 611 |
|
|
<a name="l03185"></a>03185 <span class="vhdlkeyword">end</span>
|
| 612 |
|
|
<a name="l03186"></a>03186
|
| 613 |
|
|
<a name="l03187"></a>03187 <span class="keyword">// C,V,N,X not affected</span>
|
| 614 |
|
|
<a name="l03188"></a>03188 <span class="vhdlkeyword">end</span>
|
| 615 |
|
|
<a name="l03189"></a>03189
|
| 616 |
|
|
<a name="l03190"></a>03190 <a class="code" href="ao68000_8v.html#ac7de3ab6c8eec4381bde5e4f61b45761">`ALU_TAS</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 617 |
|
|
<a name="l03191"></a>03191 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] <= { <span class="vhdllogic">1'b1</span>, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">6</span>:<span class="vhdllogic">0</span>] };
|
| 618 |
|
|
<a name="l03192"></a>03192
|
| 619 |
|
|
<a name="l03193"></a>03193 <span class="keyword">// X not affected</span>
|
| 620 |
|
|
<a name="l03194"></a>03194 <span class="keyword">// C cleared</span>
|
| 621 |
|
|
<a name="l03195"></a>03195 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 622 |
|
|
<a name="l03196"></a>03196 <span class="keyword">// V cleared</span>
|
| 623 |
|
|
<a name="l03197"></a>03197 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 624 |
|
|
<a name="l03198"></a>03198
|
| 625 |
|
|
<a name="l03199"></a>03199 <span class="keyword">// N set</span>
|
| 626 |
|
|
<a name="l03200"></a>03200 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= (<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>] == <span class="vhdllogic">1'b1</span>);
|
| 627 |
|
|
<a name="l03201"></a>03201 <span class="keyword">// Z set</span>
|
| 628 |
|
|
<a name="l03202"></a>03202 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= (<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'b0</span>);
|
| 629 |
|
|
<a name="l03203"></a>03203 <span class="vhdlkeyword">end</span>
|
| 630 |
|
|
<a name="l03204"></a>03204
|
| 631 |
14 |
alfik |
<a name="l03205"></a>03205
|
| 632 |
16 |
alfik |
<a name="l03206"></a>03206 <a class="code" href="ao68000_8v.html#a07c7e53af3f4995a167966ba18c2728f">`ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 633 |
|
|
<a name="l03207"></a>03207 <span class="keyword">// NEGX / CLR / NEG / NOT</span>
|
| 634 |
|
|
<a name="l03208"></a>03208 <span class="keyword">// Optimization thanks to Frederic Requin</span>
|
| 635 |
|
|
<a name="l03209"></a>03209 <span class="vhdlkeyword">if</span> ((<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span>) || (<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span>) || (<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span>) || (<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span>))
|
| 636 |
|
|
<a name="l03210"></a>03210 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> = <span class="vhdllogic">32'b0</span> - (<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] & {<span class="vhdllogic">32</span>{<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">10</span>] | ~<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">9</span>]}}) - ((<a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] & ~<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">10</span>] & ~<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">9</span>]) | (<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">10</span>] & <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">9</span>]));
|
| 637 |
|
|
<a name="l03211"></a>03211 <span class="keyword">// NBCD</span>
|
| 638 |
|
|
<a name="l03212"></a>03212 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_00</span> ) <span class="vhdlkeyword">begin</span>
|
| 639 |
|
|
<a name="l03213"></a>03213 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">5'd25</span> - <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>];
|
| 640 |
|
|
<a name="l03214"></a>03214 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = (<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] > <span class="vhdllogic">4'd9</span>) ? (<span class="vhdllogic">5'd24</span> - <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]) : (<span class="vhdllogic">5'd25</span> - <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>]);
|
| 641 |
|
|
<a name="l03215"></a>03215
|
| 642 |
|
|
<a name="l03216"></a>03216 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span> && <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span> && <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] == <span class="vhdllogic">4'd9</span>) <span class="vhdlkeyword">begin</span>
|
| 643 |
|
|
<a name="l03217"></a>03217 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">4'd0</span>;
|
| 644 |
|
|
<a name="l03218"></a>03218 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <span class="vhdllogic">4'd0</span>;
|
| 645 |
|
|
<a name="l03219"></a>03219 <span class="vhdlkeyword">end</span>
|
| 646 |
|
|
<a name="l03220"></a>03220 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span> && (<a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd9</span> || <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">4'd15</span>)) <span class="vhdlkeyword">begin</span>
|
| 647 |
|
|
<a name="l03221"></a>03221 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <span class="vhdllogic">4'd0</span>;
|
| 648 |
|
|
<a name="l03222"></a>03222 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] = <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">4</span>] + <span class="vhdllogic">4'd1</span>;
|
| 649 |
|
|
<a name="l03223"></a>03223 <span class="vhdlkeyword">end</span>
|
| 650 |
|
|
<a name="l03224"></a>03224 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 651 |
|
|
<a name="l03225"></a>03225 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] = <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] + <span class="vhdllogic">4'd1</span>;
|
| 652 |
|
|
<a name="l03226"></a>03226 <span class="vhdlkeyword">end</span>
|
| 653 |
|
|
<a name="l03227"></a>03227
|
| 654 |
|
|
<a name="l03228"></a>03228 <span class="keyword">//V undefined: unchanged</span>
|
| 655 |
|
|
<a name="l03229"></a>03229 <span class="keyword">//Z</span>
|
| 656 |
|
|
<a name="l03230"></a>03230 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 657 |
|
|
<a name="l03231"></a>03231 <span class="keyword">//C,X</span>
|
| 658 |
|
|
<a name="l03232"></a>03232 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= (<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'd0</span> && <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>;
|
| 659 |
|
|
<a name="l03233"></a>03233 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] <= (<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">8'd0</span> && <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] == <span class="vhdllogic">1'b0</span>) ? <span class="vhdllogic">1'b0</span> : <span class="vhdllogic">1'b1</span>; <span class="keyword">//=C</span>
|
| 660 |
|
|
<a name="l03234"></a>03234 <span class="vhdlkeyword">end</span>
|
| 661 |
|
|
<a name="l03235"></a>03235 <span class="keyword">// SWAP</span>
|
| 662 |
|
|
<a name="l03236"></a>03236 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_01</span> ) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> = { <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>] };
|
| 663 |
|
|
<a name="l03237"></a>03237 <span class="keyword">// EXT byte to word</span>
|
| 664 |
|
|
<a name="l03238"></a>03238 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_10</span> ) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> = { <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>], {<span class="vhdllogic">8</span>{<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 665 |
|
|
<a name="l03239"></a>03239 <span class="keyword">// EXT word to long</span>
|
| 666 |
|
|
<a name="l03240"></a>03240 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_11</span> ) <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> = { {<span class="vhdllogic">16</span>{<a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
| 667 |
|
|
<a name="l03241"></a>03241
|
| 668 |
|
|
<a name="l03242"></a>03242 <span class="keyword">// N set if negative else clear</span>
|
| 669 |
|
|
<a name="l03243"></a>03243 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">3</span>] <= <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 670 |
|
|
<a name="l03244"></a>03244
|
| 671 |
|
|
<a name="l03245"></a>03245 <span class="keyword">// CLR,NOT,SWAP,EXT</span>
|
| 672 |
|
|
<a name="l03246"></a>03246 <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0010</span> || <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0110</span> || <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">6</span>] == <span class="vhdllogic">6'b1000_01</span> || <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">7</span>] == <span class="vhdllogic">5'b1000_1</span> ) <span class="vhdlkeyword">begin</span>
|
| 673 |
|
|
<a name="l03247"></a>03247 <span class="keyword">// X not affected</span>
|
| 674 |
|
|
<a name="l03248"></a>03248 <span class="keyword">// C,V cleared</span>
|
| 675 |
|
|
<a name="l03249"></a>03249 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 676 |
|
|
<a name="l03250"></a>03250 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <span class="vhdllogic">1'b0</span>;
|
| 677 |
|
|
<a name="l03251"></a>03251 <span class="keyword">// Z set</span>
|
| 678 |
|
|
<a name="l03252"></a>03252 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 679 |
|
|
<a name="l03253"></a>03253 <span class="vhdlkeyword">end</span>
|
| 680 |
|
|
<a name="l03254"></a>03254 <span class="keyword">// NEGX</span>
|
| 681 |
|
|
<a name="l03255"></a>03255 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0000</span> ) <span class="vhdlkeyword">begin</span>
|
| 682 |
|
|
<a name="l03256"></a>03256 <span class="keyword">// C set if borrow</span>
|
| 683 |
|
|
<a name="l03257"></a>03257 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 684 |
|
|
<a name="l03258"></a>03258 <span class="keyword">// X=C</span>
|
| 685 |
|
|
<a name="l03259"></a>03259 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 686 |
|
|
<a name="l03260"></a>03260 <span class="keyword">// V set if overflow</span>
|
| 687 |
|
|
<a name="l03261"></a>03261 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 688 |
|
|
<a name="l03262"></a>03262 <span class="keyword">// Z cleared if nonzero else unchanged</span>
|
| 689 |
|
|
<a name="l03263"></a>03263 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] & <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 690 |
|
|
<a name="l03264"></a>03264 <span class="vhdlkeyword">end</span>
|
| 691 |
|
|
<a name="l03265"></a>03265 <span class="keyword">// NEG</span>
|
| 692 |
|
|
<a name="l03266"></a>03266 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>( <a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] == <span class="vhdllogic">4'b0100</span> ) <span class="vhdlkeyword">begin</span>
|
| 693 |
|
|
<a name="l03267"></a>03267 <span class="keyword">// C clear if zero else set</span>
|
| 694 |
|
|
<a name="l03268"></a>03268 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">0</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 695 |
|
|
<a name="l03269"></a>03269 <span class="keyword">// X=C</span>
|
| 696 |
|
|
<a name="l03270"></a>03270 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">4</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> | <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 697 |
|
|
<a name="l03271"></a>03271 <span class="keyword">// V set if overflow</span>
|
| 698 |
|
|
<a name="l03272"></a>03272 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">1</span>] <= <a class="code" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">`Dm</a><span class="vhdlchar"></span> & <a class="code" href="classalu.html#a942f3773659fb9e9e38101743237144a">`Rm</a><span class="vhdlchar"></span>;
|
| 699 |
|
|
<a name="l03273"></a>03273 <span class="keyword">// Z set if zero else clear</span>
|
| 700 |
|
|
<a name="l03274"></a>03274 <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">2</span>] <= <a class="code" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">`Z</a><span class="vhdlchar"></span>;
|
| 701 |
|
|
<a name="l03275"></a>03275 <span class="vhdlkeyword">end</span>
|
| 702 |
|
|
<a name="l03276"></a>03276 <span class="vhdlkeyword">end</span>
|
| 703 |
|
|
<a name="l03277"></a>03277
|
| 704 |
|
|
<a name="l03278"></a>03278
|
| 705 |
|
|
<a name="l03279"></a>03279 <a class="code" href="ao68000_8v.html#a32c0e163ff437b07e40593ab59e42fe3">`ALU_SIMPLE_LONG_ADD</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 706 |
|
|
<a name="l03280"></a>03280 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] + <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 707 |
|
|
<a name="l03281"></a>03281
|
| 708 |
|
|
<a name="l03282"></a>03282 <span class="keyword">// CCR not affected</span>
|
| 709 |
|
|
<a name="l03283"></a>03283 <span class="vhdlkeyword">end</span>
|
| 710 |
|
|
<a name="l03284"></a>03284
|
| 711 |
|
|
<a name="l03285"></a>03285 <a class="code" href="ao68000_8v.html#aea6fee15f3d775b1a8d262490203c713">`ALU_SIMPLE_LONG_SUB</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 712 |
|
|
<a name="l03286"></a>03286 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] - <a class="code" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 713 |
|
|
<a name="l03287"></a>03287
|
| 714 |
|
|
<a name="l03288"></a>03288 <span class="keyword">// CCR not affected</span>
|
| 715 |
14 |
alfik |
<a name="l03289"></a>03289 <span class="vhdlkeyword">end</span>
|
| 716 |
|
|
<a name="l03290"></a>03290
|
| 717 |
16 |
alfik |
<a name="l03291"></a>03291 <a class="code" href="ao68000_8v.html#a5083d98f4b785fe7af85ba1114f678ff">`ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 718 |
|
|
<a name="l03292"></a>03292
|
| 719 |
|
|
<a name="l03293"></a>03293 <span class="keyword">// MOVE TO SR,RTE,STOP,ORI to SR,ANDI to SR,EORI to SR</span>
|
| 720 |
|
|
<a name="l03294"></a>03294 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a>[<span class="vhdllogic">16</span>]) <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a> <= { <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">15</span>], <span class="vhdllogic">1'b0</span>, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">13</span>], <span class="vhdllogic">2'b0</span>, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">10</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
| 721 |
|
|
<a name="l03295"></a>03295 <span class="keyword">// MOVE TO CCR,RTR,ORI to CCR,ANDI to CCR,EORI to CCR</span>
|
| 722 |
|
|
<a name="l03296"></a>03296 <span class="vhdlkeyword">else</span> <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a> <= { <a class="code" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>], <span class="vhdllogic">3'b0</span>, <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>[<span class="vhdllogic">4</span>:<span class="vhdllogic">0</span>] };
|
| 723 |
|
|
<a name="l03297"></a>03297 <span class="vhdlkeyword">end</span>
|
| 724 |
|
|
<a name="l03298"></a>03298
|
| 725 |
|
|
<a name="l03299"></a>03299 <a class="code" href="ao68000_8v.html#ab6d6f774c41848f9c33c7b393620be2d">`ALU_SIMPLE_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 726 |
|
|
<a name="l03300"></a>03300 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>;
|
| 727 |
|
|
<a name="l03301"></a>03301
|
| 728 |
|
|
<a name="l03302"></a>03302 <span class="keyword">// CCR not affected</span>
|
| 729 |
|
|
<a name="l03303"></a>03303 <span class="vhdlkeyword">end</span>
|
| 730 |
|
|
<a name="l03304"></a>03304
|
| 731 |
|
|
<a name="l03305"></a>03305 <a class="code" href="ao68000_8v.html#ac439a8b79bd4b213f0f33172bd5e5a73">`ALU_LINK_MOVE</a><span class="vhdlchar"></span>: <span class="vhdlkeyword">begin</span>
|
| 732 |
|
|
<a name="l03306"></a>03306 <span class="vhdlkeyword">if</span>(<a class="code" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">3'b111</span>) <span class="vhdlkeyword">begin</span>
|
| 733 |
|
|
<a name="l03307"></a>03307 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a> - <span class="vhdllogic">32'd4</span>;
|
| 734 |
|
|
<a name="l03308"></a>03308 <span class="vhdlkeyword">end</span>
|
| 735 |
|
|
<a name="l03309"></a>03309 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 736 |
|
|
<a name="l03310"></a>03310 <a class="code" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a> <= <a class="code" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a>;
|
| 737 |
|
|
<a name="l03311"></a>03311 <span class="vhdlkeyword">end</span>
|
| 738 |
|
|
<a name="l03312"></a>03312
|
| 739 |
|
|
<a name="l03313"></a>03313 <span class="keyword">// CCR not affected</span>
|
| 740 |
14 |
alfik |
<a name="l03314"></a>03314 <span class="vhdlkeyword">end</span>
|
| 741 |
|
|
<a name="l03315"></a>03315
|
| 742 |
16 |
alfik |
<a name="l03316"></a>03316 <span class="vhdlkeyword">endcase</span>
|
| 743 |
|
|
<a name="l03317"></a>03317 <span class="vhdlkeyword">end</span>
|
| 744 |
|
|
<a name="l03318"></a>03318 <span class="vhdlkeyword">end</span>
|
| 745 |
12 |
alfik |
</pre></div>
|
| 746 |
|
|
</div>
|
| 747 |
|
|
</div>
|
| 748 |
|
|
<hr/><h2>Member Data Documentation</h2>
|
| 749 |
16 |
alfik |
<a class="anchor" id="a322325f3e53ea8e7d70fbdc7f5d1b30b"></a><!-- doxytag: member="alu::clock" ref="a322325f3e53ea8e7d70fbdc7f5d1b30b" args="" -->
|
| 750 |
12 |
alfik |
<div class="memitem">
|
| 751 |
|
|
<div class="memproto">
|
| 752 |
|
|
<table class="memname">
|
| 753 |
|
|
<tr>
|
| 754 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a322325f3e53ea8e7d70fbdc7f5d1b30b">clock</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 755 |
12 |
alfik |
</tr>
|
| 756 |
|
|
</table>
|
| 757 |
|
|
</div>
|
| 758 |
|
|
<div class="memdoc">
|
| 759 |
|
|
|
| 760 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02626">2626</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 761 |
12 |
alfik |
|
| 762 |
|
|
</div>
|
| 763 |
|
|
</div>
|
| 764 |
16 |
alfik |
<a class="anchor" id="a2f01d99d4de620b6ce6c7c0a150a5fab"></a><!-- doxytag: member="alu::reset_n" ref="a2f01d99d4de620b6ce6c7c0a150a5fab" args="" -->
|
| 765 |
12 |
alfik |
<div class="memitem">
|
| 766 |
|
|
<div class="memproto">
|
| 767 |
|
|
<table class="memname">
|
| 768 |
|
|
<tr>
|
| 769 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a2f01d99d4de620b6ce6c7c0a150a5fab">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 770 |
12 |
alfik |
</tr>
|
| 771 |
|
|
</table>
|
| 772 |
|
|
</div>
|
| 773 |
|
|
<div class="memdoc">
|
| 774 |
|
|
|
| 775 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02627">2627</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 776 |
12 |
alfik |
|
| 777 |
|
|
</div>
|
| 778 |
|
|
</div>
|
| 779 |
16 |
alfik |
<a class="anchor" id="a5a9e1012e0cf7d30a4a4dcaf5486693c"></a><!-- doxytag: member="alu::address" ref="a5a9e1012e0cf7d30a4a4dcaf5486693c" args="" -->
|
| 780 |
12 |
alfik |
<div class="memitem">
|
| 781 |
|
|
<div class="memproto">
|
| 782 |
|
|
<table class="memname">
|
| 783 |
|
|
<tr>
|
| 784 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a5a9e1012e0cf7d30a4a4dcaf5486693c">address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 785 |
12 |
alfik |
</tr>
|
| 786 |
|
|
</table>
|
| 787 |
|
|
</div>
|
| 788 |
|
|
<div class="memdoc">
|
| 789 |
|
|
|
| 790 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02630">2630</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 791 |
12 |
alfik |
|
| 792 |
|
|
</div>
|
| 793 |
|
|
</div>
|
| 794 |
16 |
alfik |
<a class="anchor" id="a39ca5d8f12e053ccfd9ee7f131291e1e"></a><!-- doxytag: member="alu::ir" ref="a39ca5d8f12e053ccfd9ee7f131291e1e" args="" -->
|
| 795 |
12 |
alfik |
<div class="memitem">
|
| 796 |
|
|
<div class="memproto">
|
| 797 |
|
|
<table class="memname">
|
| 798 |
|
|
<tr>
|
| 799 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a39ca5d8f12e053ccfd9ee7f131291e1e">ir</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 800 |
12 |
alfik |
</tr>
|
| 801 |
|
|
</table>
|
| 802 |
|
|
</div>
|
| 803 |
|
|
<div class="memdoc">
|
| 804 |
|
|
|
| 805 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02632">2632</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 806 |
12 |
alfik |
|
| 807 |
|
|
</div>
|
| 808 |
|
|
</div>
|
| 809 |
16 |
alfik |
<a class="anchor" id="a46ed8f8b6e397f2f7a0998fe482d4f37"></a><!-- doxytag: member="alu::size" ref="a46ed8f8b6e397f2f7a0998fe482d4f37" args="" -->
|
| 810 |
12 |
alfik |
<div class="memitem">
|
| 811 |
|
|
<div class="memproto">
|
| 812 |
|
|
<table class="memname">
|
| 813 |
|
|
<tr>
|
| 814 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a46ed8f8b6e397f2f7a0998fe482d4f37">size</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 815 |
12 |
alfik |
</tr>
|
| 816 |
|
|
</table>
|
| 817 |
|
|
</div>
|
| 818 |
|
|
<div class="memdoc">
|
| 819 |
|
|
|
| 820 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02634">2634</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 821 |
12 |
alfik |
|
| 822 |
|
|
</div>
|
| 823 |
|
|
</div>
|
| 824 |
16 |
alfik |
<a class="anchor" id="a31ec6d555af040fbc75434758413148a"></a><!-- doxytag: member="alu::operand1" ref="a31ec6d555af040fbc75434758413148a" args="" -->
|
| 825 |
12 |
alfik |
<div class="memitem">
|
| 826 |
|
|
<div class="memproto">
|
| 827 |
|
|
<table class="memname">
|
| 828 |
|
|
<tr>
|
| 829 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a31ec6d555af040fbc75434758413148a">operand1</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 830 |
12 |
alfik |
</tr>
|
| 831 |
|
|
</table>
|
| 832 |
|
|
</div>
|
| 833 |
|
|
<div class="memdoc">
|
| 834 |
|
|
|
| 835 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02636">2636</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 836 |
12 |
alfik |
|
| 837 |
|
|
</div>
|
| 838 |
|
|
</div>
|
| 839 |
16 |
alfik |
<a class="anchor" id="a9f8815596ab2b013c85f9f7add9ca14b"></a><!-- doxytag: member="alu::operand2" ref="a9f8815596ab2b013c85f9f7add9ca14b" args="" -->
|
| 840 |
12 |
alfik |
<div class="memitem">
|
| 841 |
|
|
<div class="memproto">
|
| 842 |
|
|
<table class="memname">
|
| 843 |
|
|
<tr>
|
| 844 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a9f8815596ab2b013c85f9f7add9ca14b">operand2</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 845 |
12 |
alfik |
</tr>
|
| 846 |
|
|
</table>
|
| 847 |
|
|
</div>
|
| 848 |
|
|
<div class="memdoc">
|
| 849 |
|
|
|
| 850 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02637">2637</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 851 |
12 |
alfik |
|
| 852 |
|
|
</div>
|
| 853 |
|
|
</div>
|
| 854 |
16 |
alfik |
<a class="anchor" id="ab8bac09f28bae473ebf96e3c2c7e2806"></a><!-- doxytag: member="alu::interrupt_mask" ref="ab8bac09f28bae473ebf96e3c2c7e2806" args="" -->
|
| 855 |
12 |
alfik |
<div class="memitem">
|
| 856 |
|
|
<div class="memproto">
|
| 857 |
|
|
<table class="memname">
|
| 858 |
|
|
<tr>
|
| 859 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ab8bac09f28bae473ebf96e3c2c7e2806">interrupt_mask</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 860 |
12 |
alfik |
</tr>
|
| 861 |
|
|
</table>
|
| 862 |
|
|
</div>
|
| 863 |
|
|
<div class="memdoc">
|
| 864 |
|
|
|
| 865 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02639">2639</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 866 |
12 |
alfik |
|
| 867 |
|
|
</div>
|
| 868 |
|
|
</div>
|
| 869 |
16 |
alfik |
<a class="anchor" id="abd96864c4534e2905f0ac629d1bcfce1"></a><!-- doxytag: member="alu::alu_control" ref="abd96864c4534e2905f0ac629d1bcfce1" args="" -->
|
| 870 |
12 |
alfik |
<div class="memitem">
|
| 871 |
|
|
<div class="memproto">
|
| 872 |
|
|
<table class="memname">
|
| 873 |
|
|
<tr>
|
| 874 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#abd96864c4534e2905f0ac629d1bcfce1">alu_control</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 875 |
12 |
alfik |
</tr>
|
| 876 |
|
|
</table>
|
| 877 |
|
|
</div>
|
| 878 |
|
|
<div class="memdoc">
|
| 879 |
|
|
|
| 880 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02640">2640</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 881 |
12 |
alfik |
|
| 882 |
|
|
</div>
|
| 883 |
|
|
</div>
|
| 884 |
16 |
alfik |
<a class="anchor" id="a1432b02bc905189b2e869fd30ce1e0b6"></a><!-- doxytag: member="alu::sr" ref="a1432b02bc905189b2e869fd30ce1e0b6" args="" -->
|
| 885 |
12 |
alfik |
<div class="memitem">
|
| 886 |
|
|
<div class="memproto">
|
| 887 |
|
|
<table class="memname">
|
| 888 |
|
|
<tr>
|
| 889 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a1432b02bc905189b2e869fd30ce1e0b6">sr</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">15</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 890 |
12 |
alfik |
</tr>
|
| 891 |
|
|
</table>
|
| 892 |
|
|
</div>
|
| 893 |
|
|
<div class="memdoc">
|
| 894 |
|
|
|
| 895 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02642">2642</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 896 |
12 |
alfik |
|
| 897 |
|
|
</div>
|
| 898 |
|
|
</div>
|
| 899 |
16 |
alfik |
<a class="anchor" id="ad869ff0f455bd2bdcea8d232e72beecd"></a><!-- doxytag: member="alu::result" ref="ad869ff0f455bd2bdcea8d232e72beecd" args="" -->
|
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alfik |
<div class="memitem">
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<div class="memproto">
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<table class="memname">
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16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ad869ff0f455bd2bdcea8d232e72beecd">result</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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| 909 |
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| 910 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02643">2643</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 912 |
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</div>
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| 913 |
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</div>
|
| 914 |
16 |
alfik |
<a class="anchor" id="ad39d03bb22df22560c4f5dc796382313"></a><!-- doxytag: member="alu::alu_signal" ref="ad39d03bb22df22560c4f5dc796382313" args="" -->
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<table class="memname">
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alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ad39d03bb22df22560c4f5dc796382313">alu_signal</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 920 |
12 |
alfik |
</tr>
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</table>
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</div>
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<div class="memdoc">
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02645">2645</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 926 |
12 |
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| 927 |
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</div>
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</div>
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16 |
alfik |
<a class="anchor" id="ac76782f488b9491569955793b9b37762"></a><!-- doxytag: member="alu::alu_mult_div_ready" ref="ac76782f488b9491569955793b9b37762" args="" -->
|
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<div class="memitem">
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<table class="memname">
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alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ac76782f488b9491569955793b9b37762">alu_mult_div_ready</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02646">2646</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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12 |
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| 942 |
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</div>
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</div>
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| 944 |
16 |
alfik |
<a class="anchor" id="a290176de350bb9535f4186f96eeb4ba3"></a><!-- doxytag: member="alu::decoder_alu_reg" ref="a290176de350bb9535f4186f96eeb4ba3" args="" -->
|
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<div class="memitem">
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<table class="memname">
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alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a290176de350bb9535f4186f96eeb4ba3">decoder_alu_reg</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">17</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 950 |
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</tr>
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</table>
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</div>
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<div class="memdoc">
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| 954 |
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| 955 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02647">2647</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 956 |
12 |
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|
| 957 |
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</div>
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| 958 |
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</div>
|
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16 |
alfik |
<a class="anchor" id="a25ae8f83a524b562fb57cd0af6dee164"></a><!-- doxytag: member="alu::mult_div_sign" ref="a25ae8f83a524b562fb57cd0af6dee164" args="wire" -->
|
| 960 |
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<div class="memitem">
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| 961 |
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a25ae8f83a524b562fb57cd0af6dee164">mult_div_sign</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
|
| 965 |
12 |
alfik |
</tr>
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| 966 |
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</table>
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</div>
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| 968 |
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<div class="memdoc">
|
| 969 |
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|
| 970 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02658">2658</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 971 |
12 |
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|
| 972 |
|
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</div>
|
| 973 |
|
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</div>
|
| 974 |
16 |
alfik |
<a class="anchor" id="a3a2dd2d9816dba2aebe4a5cf5eeed521"></a><!-- doxytag: member="alu::div_count" ref="a3a2dd2d9816dba2aebe4a5cf5eeed521" args="reg[4:0]" -->
|
| 975 |
12 |
alfik |
<div class="memitem">
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<div class="memproto">
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| 977 |
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<table class="memname">
|
| 978 |
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<tr>
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| 979 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a3a2dd2d9816dba2aebe4a5cf5eeed521">div_count</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[4:0]]</code></td>
|
| 980 |
12 |
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</tr>
|
| 981 |
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</table>
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| 982 |
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</div>
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| 983 |
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<div class="memdoc">
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| 984 |
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|
| 985 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02661">2661</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 986 |
12 |
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|
| 987 |
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</div>
|
| 988 |
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</div>
|
| 989 |
16 |
alfik |
<a class="anchor" id="ac5f88cdff8f17d02e28927335c6f141d"></a><!-- doxytag: member="alu::quotient" ref="ac5f88cdff8f17d02e28927335c6f141d" args="reg[16:0]" -->
|
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<div class="memitem">
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| 991 |
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| 992 |
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ac5f88cdff8f17d02e28927335c6f141d">quotient</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[16:0]]</code></td>
|
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12 |
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</tr>
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| 996 |
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</table>
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</div>
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| 998 |
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<div class="memdoc">
|
| 999 |
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|
| 1000 |
16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02662">2662</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1001 |
12 |
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|
| 1002 |
|
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</div>
|
| 1003 |
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</div>
|
| 1004 |
16 |
alfik |
<a class="anchor" id="a108916b9974c024932e1e9874589c4ba"></a><!-- doxytag: member="alu::dividend" ref="a108916b9974c024932e1e9874589c4ba" args="reg[31:0]" -->
|
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<div class="memitem">
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| 1006 |
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| 1007 |
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<table class="memname">
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| 1008 |
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<tr>
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16 |
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a108916b9974c024932e1e9874589c4ba">dividend</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[31:0]]</code></td>
|
| 1010 |
12 |
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</tr>
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| 1011 |
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</table>
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| 1012 |
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</div>
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| 1013 |
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<div class="memdoc">
|
| 1014 |
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| 1015 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02663">2663</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1016 |
12 |
alfik |
|
| 1017 |
|
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</div>
|
| 1018 |
|
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</div>
|
| 1019 |
16 |
alfik |
<a class="anchor" id="ab4e5d750cf0d96eb715606c6166945cb"></a><!-- doxytag: member="alu::divider" ref="ab4e5d750cf0d96eb715606c6166945cb" args="reg[31:0]" -->
|
| 1020 |
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alfik |
<div class="memitem">
|
| 1021 |
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<div class="memproto">
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| 1022 |
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<table class="memname">
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| 1023 |
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<tr>
|
| 1024 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ab4e5d750cf0d96eb715606c6166945cb">divider</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[31:0]]</code></td>
|
| 1025 |
12 |
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</tr>
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| 1026 |
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</table>
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| 1027 |
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</div>
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| 1028 |
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<div class="memdoc">
|
| 1029 |
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|
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02663">2663</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1031 |
12 |
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|
| 1032 |
|
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</div>
|
| 1033 |
|
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</div>
|
| 1034 |
16 |
alfik |
<a class="anchor" id="a2fc8379eb8a0ee027596e29d34c0fbc7"></a><!-- doxytag: member="alu::div_diff" ref="a2fc8379eb8a0ee027596e29d34c0fbc7" args="wire[32:0]" -->
|
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<div class="memitem">
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<table class="memname">
|
| 1038 |
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<tr>
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16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a2fc8379eb8a0ee027596e29d34c0fbc7">div_diff</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[32:0]]</code></td>
|
| 1040 |
12 |
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</tr>
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</table>
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</div>
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| 1043 |
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<div class="memdoc">
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| 1044 |
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|
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16 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02666">2666</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1046 |
12 |
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|
| 1047 |
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</div>
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| 1048 |
|
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</div>
|
| 1049 |
16 |
alfik |
<a class="anchor" id="abad1e1ed5e810e1a31e16550349b6bfb"></a><!-- doxytag: member="alu::div_overflow" ref="abad1e1ed5e810e1a31e16550349b6bfb" args="wire" -->
|
| 1050 |
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<div class="memitem">
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<table class="memname">
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<tr>
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16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#abad1e1ed5e810e1a31e16550349b6bfb">div_overflow</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
|
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12 |
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</tr>
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</table>
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</div>
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<div class="memdoc">
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| 1059 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02669">2669</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
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12 |
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| 1062 |
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</div>
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</div>
|
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<a class="anchor" id="a66f6b0eb96212740619af0f057d33546"></a><!-- doxytag: member="alu::div_quotient" ref="a66f6b0eb96212740619af0f057d33546" args="wire[15:0]" -->
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<div class="memitem">
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a66f6b0eb96212740619af0f057d33546">div_quotient</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[15:0]]</code></td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02675">2675</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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12 |
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| 1077 |
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</div>
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| 1078 |
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</div>
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<a class="anchor" id="a3b4ed364cf9180375a05991a64005ea7"></a><!-- doxytag: member="alu::div_remainder" ref="a3b4ed364cf9180375a05991a64005ea7" args="wire[15:0]" -->
|
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a3b4ed364cf9180375a05991a64005ea7">div_remainder</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[15:0]]</code></td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02681">2681</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
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</div>
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<a class="anchor" id="ac1b8a2e6c2bb6a12b10db4250f56135e"></a><!-- doxytag: member="alu::mult_result" ref="ac1b8a2e6c2bb6a12b10db4250f56135e" args="wire[33:0]" -->
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<div class="memitem">
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<table class="memname">
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<tr>
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ac1b8a2e6c2bb6a12b10db4250f56135e">mult_result</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[33:0]]</code></td>
|
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02734">2734</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1106 |
12 |
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|
| 1107 |
|
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</div>
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</div>
|
| 1109 |
16 |
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<a class="anchor" id="a71bbcd2b437cc138ec4e56a2fb248d7e"></a><!-- doxytag: member="alu::interrupt_mask_copy" ref="a71bbcd2b437cc138ec4e56a2fb248d7e" args="reg[2:0]" -->
|
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<div class="memitem">
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| 1111 |
|
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<div class="memproto">
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| 1112 |
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<table class="memname">
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<tr>
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| 1114 |
16 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a71bbcd2b437cc138ec4e56a2fb248d7e">interrupt_mask_copy</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[2:0]]</code></td>
|
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12 |
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</tr>
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</table>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02765">2765</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="acd1a91ac2175444844ece34147d7baa4"></a><!-- doxytag: member="alu::was_interrupt" ref="acd1a91ac2175444844ece34147d7baa4" args="reg" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#acd1a91ac2175444844ece34147d7baa4">was_interrupt</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02766">2766</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ab2b982ee64f25838bec8dba77728dfd8"></a><!-- doxytag: member="alu::lbit" ref="ab2b982ee64f25838bec8dba77728dfd8" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ab2b982ee64f25838bec8dba77728dfd8">lbit</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02769">2769</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a8035654de9f2902808f814526db0e1bc"></a><!-- doxytag: member="alu::rbit" ref="a8035654de9f2902808f814526db0e1bc" args="wire" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a8035654de9f2902808f814526db0e1bc">rbit</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02771">2771</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a09fdad5ef76ddc7865c6e3a9cfc09123"></a><!-- doxytag: member="alu::Dm" ref="a09fdad5ef76ddc7865c6e3a9cfc09123" args="((size[0]==1'b1)?operand1[7]:(size[1]==1'b1)?operand1[15]:operand1[31])" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a09fdad5ef76ddc7865c6e3a9cfc09123">Dm</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02757">2757</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a6447478386a93e0306b7cb09937c23c3"></a><!-- doxytag: member="alu::lpm_mult" ref="a6447478386a93e0306b7cb09937c23c3" args="" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a6447478386a93e0306b7cb09937c23c3">lpm_mult</a></span> <b><span class="vhdlchar">muls</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02736">2736</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a942f3773659fb9e9e38101743237144a"></a><!-- doxytag: member="alu::Rm" ref="a942f3773659fb9e9e38101743237144a" args="((size[0]==1'b1)?result[7]:(size[1]==1'b1)?result[15]:result[31])" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a942f3773659fb9e9e38101743237144a">Rm</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02759">2759</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a52a04e7012270413af6cecfc29ce720a"></a><!-- doxytag: member="alu::Sm" ref="a52a04e7012270413af6cecfc29ce720a" args="((size[0]==1'b1)?operand2[7]:(size[1]==1'b1)?operand2[15]:operand2[31])" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#a52a04e7012270413af6cecfc29ce720a">Sm</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02755">2755</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="ac5469ea2de38c1332c5a56b6b6242d55"></a><!-- doxytag: member="alu::Z" ref="ac5469ea2de38c1332c5a56b6b6242d55" args="((size[0]==1'b1)?(result[7:0]==8'b0):(size[1]==1'b1)?(result[15:0]==16'b0):(result[31:0]==32'b0))" -->
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<td class="memname"><span class="stringliteral"><a class="el" href="classalu.html#ac5469ea2de38c1332c5a56b6b6242d55">Z</a></span> <b><span class="vhdlchar"> </span></b><code> [Define]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02761">2761</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
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<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li>
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 22:20:15 for ao68000 by 
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<a href="http://www.doxygen.org/index.html">
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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