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<title>ao68000: bus_control Module Reference</title>
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<a href="#Inputs">Inputs</a> |
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<a href="#Outputs">Outputs</a> |
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<a href="#Signals">Signals</a> |
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<a href="#Parameters">Parameters</a> |
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<a href="#Always Constructs">Always Constructs</a> </div>
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<div class="headertitle">
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<h1>bus_control Module Reference</h1> </div>
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<div class="contents">
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<!-- doxytag: class="bus_control" -->
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<p>Initiate WISHBONE MASTER bus cycles.
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<a href="#_details">More...</a></p>
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<!-- startSectionHeader --><div class="dynheader">
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Inheritance diagram for bus_control:<!-- endSectionHeader --></div>
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<img src="classbus__control.png" usemap="#bus_control_map" alt=""/>
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</div><!-- endSectionContent --></div>
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<p><a href="classbus__control-members.html">List of all members.</a></p>
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<table class="memberdecls">
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<tr><td colspan="2"><h2><a name="Always Constructs"></a>
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Always Constructs</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#ad06cdf24c29b1b82596011bac2c9169c">ALWAYS_0</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">CLK_I</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#af34450e53e6fd2fd36db7dff17caf063">ALWAYS_1</a> </td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">CLK_I</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td colspan="2"><h2><a name="Inputs"></a>
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Inputs</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">CLK_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a>  </td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a1ed42a631a71210de0231c9079f52f22">ipl_i</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td colspan="2"><h2><a name="Outputs"></a>
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Outputs</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#ada8208aac77c8a5b2d937d050a85ded6">BTE_O</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">reset_o</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> </td></tr>
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<tr><td colspan="2"><h2><a name="Parameters"></a>
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Parameters</h2></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd0</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a21f9753bb3594dcc9d190ef5c54071e6">S_RESET</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd1</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a35c0778e16a225b839acc35705428b6a">S_BLOCKED</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd2</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a22028b6e9c3a87066084eeb7e3ea66dc">S_INT_1</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd3</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a0957d5175230f9062a95b56e1db2fc53">S_READ_1</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd4</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a3067a17da274e211d0877d25ac1a1dec">S_READ_2</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd5</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#ae156bee4c9bdf06b34803d8d68d9f50f">S_READ_3</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd6</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd7</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a47878ecd24d5368e7396dd97ec9f4077">S_WRITE_1</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd8</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a4aaa0182c2987111710dd7a7e5f23609">S_WRITE_2</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd9</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a7c1c733e80689349399716f442a5db8d">S_WRITE_3</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd10</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a058fe5f10d0f20cf2635fba74eafb30a">S_PC_0</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd11</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a0224e82b22d3f1272d6cb604df02fd65">S_PC_1</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd12</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a4b9998b72c69db4dcd98755835413fda">S_PC_2</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd13</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a84be1a92cbb681a472f3e78c50d48953">S_PC_3</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd14</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#aec52b8e16695194dcbfefab239d8a94a">S_PC_4</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd15</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#abdb432663a596db90688fa0fa9d8d603">S_PC_5</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd16</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a95ac5f10cc1642a474302d109678e2c2">S_PC_6</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">5'd17</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#abc48f0e1c96b882d85f1b1033f985b61">FC_USER_DATA</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">3'd1</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#af182a23ace6536ef234233549e2de05c">FC_USER_PROGRAM</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">3'd2</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#ae4def0ea9761559826d03589c2727513">FC_SUPERVISOR_DATA</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">3'd5</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#ab1ee5e2a9796c9681a2401aaa7c623e3">FC_SUPERVISOR_PROGRAM</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">3'd6</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#aabcbc5528d37aad94c1c91f72abe9788">FC_CPU_SPACE</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">3'd7</span><span class="vhdlchar"> </span></b></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#ad3b1eccec1964a8067b4d458c0735bec">CTI_CLASSIC_CYCLE</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">3'd0</span><span class="vhdlchar"> </span></b></td></tr>
|
| 108 |
|
|
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a965b59e7efe4fa822995720d75210d72">CTI_CONST_CYCLE</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">3'd1</span><span class="vhdlchar"> </span></b></td></tr>
|
| 109 |
|
|
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">3'd2</span><span class="vhdlchar"> </span></b></td></tr>
|
| 110 |
|
|
<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">3'd7</span><span class="vhdlchar"> </span></b></td></tr>
|
| 111 |
|
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">8'd2</span><span class="vhdlchar"> </span></b></td></tr>
|
| 112 |
|
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classbus__control.html#a4d7a5b1d461b7f9e41ef71fe929ebc24">VECTOR_ADDRESS_TRAP</a>  </td><td class="memItemRight" valign="bottom"><b><span class="vhdldigit">8'd3</span><span class="vhdlchar"> </span></b></td></tr>
|
| 113 |
12 |
alfik |
<tr><td colspan="2"><h2><a name="Signals"></a>
|
| 114 |
|
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Signals</h2></td></tr>
|
| 115 |
13 |
alfik |
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__control.html#a518be1f0ea917cc51c7843115db83ce1">pc_i_plus_6</a> </td></tr>
|
| 116 |
|
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__control.html#ad4e505c885a6c941198d653beff91bf1">pc_i_plus_4</a> </td></tr>
|
| 117 |
|
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__control.html#af8d1410047baf49f9a20acaf85010d8f">address_i_plus_4</a> </td></tr>
|
| 118 |
|
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> </td></tr>
|
| 119 |
|
|
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> </td></tr>
|
| 120 |
|
|
<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a> </td></tr>
|
| 121 |
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td><td class="memItemRight" valign="bottom"><a class="el" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a> </td></tr>
|
| 122 |
12 |
alfik |
</table>
|
| 123 |
|
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
|
| 124 |
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<p>Initiate WISHBONE MASTER bus cycles. </p>
|
| 125 |
|
|
<p>The <a class="el" href="classbus__control.html" title="Initiate WISHBONE MASTER bus cycles.">bus_control</a> module is the only module that has contact with signals from outside of the IP core. It is responsible for initiating WISHBONE MASTER bus cycles. The cycles can be divided into:</p>
|
| 126 |
|
|
<ul>
|
| 127 |
|
|
<li>memory read cycles (supervisor data, supervisor program, user data, user program)</li>
|
| 128 |
|
|
<li>memory write cycles (supervisor data, user data),</li>
|
| 129 |
|
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<li>interrupt acknowledge.</li>
|
| 130 |
|
|
</ul>
|
| 131 |
|
|
<p>Every cycle is supplemented with the following tags:</p>
|
| 132 |
|
|
<ul>
|
| 133 |
|
|
<li>standard WISHBONE cycle tags: SGL_O, BLK_O, RMW_O,</li>
|
| 134 |
|
|
<li>register feedback WISHBONE address tags: CTI_O and BTE_O,</li>
|
| 135 |
|
|
<li><a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> specific cycle tag: fc_o which is equivalent to MC68000 function codes.</li>
|
| 136 |
|
|
</ul>
|
| 137 |
|
|
<p>The <a class="el" href="classbus__control.html" title="Initiate WISHBONE MASTER bus cycles.">bus_control</a> module is also responsible for registering interrupt inputs and initiating the interrupt acknowledge cycle in response to a microcode request. Microcode requests a interrupt acknowledge at the end of instruction processing, when the interrupt privilege level is higher than the current interrupt privilege mask, as specified in the MC68000 User's Manual.</p>
|
| 138 |
|
|
<p>Finally, <a class="el" href="classbus__control.html" title="Initiate WISHBONE MASTER bus cycles.">bus_control</a> controls also two <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> specific core outputs:</p>
|
| 139 |
|
|
<ul>
|
| 140 |
|
|
<li>blocked output, high when that the processor is blocked after encountering a double bus error. The only way to leave this block state is by reseting the <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> by the asynchronous reset input signal.</li>
|
| 141 |
|
|
<li>reset output, high when processing the RESET instruction. Can be used to reset external devices. </li>
|
| 142 |
|
|
</ul>
|
| 143 |
|
|
|
| 144 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00751">751</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 145 |
12 |
alfik |
<hr/><h2>Member Function Documentation</h2>
|
| 146 |
|
|
<a class="anchor" id="ad06cdf24c29b1b82596011bac2c9169c"></a><!-- doxytag: member="bus_control::ALWAYS_0" ref="ad06cdf24c29b1b82596011bac2c9169c" args="CLK_I, reset_n" -->
|
| 147 |
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<div class="memitem">
|
| 148 |
|
|
<div class="memproto">
|
| 149 |
|
|
<table class="memname">
|
| 150 |
|
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<tr>
|
| 151 |
|
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<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_0 <td></td>
|
| 152 |
13 |
alfik |
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">CLK_I</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
|
| 153 |
12 |
alfik |
</tr>
|
| 154 |
|
|
<tr>
|
| 155 |
|
|
<td class="paramkey"></td>
|
| 156 |
|
|
<td></td>
|
| 157 |
13 |
alfik |
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
|
| 158 |
12 |
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</tr>
|
| 159 |
|
|
<code> [Always Construct]</code></td>
|
| 160 |
|
|
</tr>
|
| 161 |
|
|
</table>
|
| 162 |
|
|
</div>
|
| 163 |
|
|
<div class="memdoc">
|
| 164 |
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|
| 165 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00880">880</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 166 |
12 |
alfik |
<div class="fragment"><pre class="fragment">
|
| 167 |
13 |
alfik |
<a name="l00880"></a>00880 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">CLK_I</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 168 |
|
|
<a name="l00881"></a>00881 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 169 |
|
|
<a name="l00882"></a>00882 <span class="vhdlchar">interrupt_mask_o</span> <= <span class="vhdllogic">3'b000</span>;
|
| 170 |
|
|
<a name="l00883"></a>00883 <a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a> <= <span class="vhdllogic">3'b000</span>;
|
| 171 |
|
|
<a name="l00884"></a>00884 <span class="vhdlkeyword">end</span>
|
| 172 |
|
|
<a name="l00885"></a>00885 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a1ed42a631a71210de0231c9079f52f22">ipl_i</a> > <span class="vhdlchar">ipm_i</span> && <span class="vhdlchar">do_interrupt_i</span> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 173 |
|
|
<a name="l00886"></a>00886 <span class="vhdlchar">interrupt_mask_o</span> <= <a class="code" href="classbus__control.html#a1ed42a631a71210de0231c9079f52f22">ipl_i</a>;
|
| 174 |
|
|
<a name="l00887"></a>00887 <a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a> <= <span class="vhdlchar">interrupt_mask_o</span>;
|
| 175 |
12 |
alfik |
<a name="l00888"></a>00888 <span class="vhdlkeyword">end</span>
|
| 176 |
13 |
alfik |
<a name="l00889"></a>00889 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 177 |
|
|
<a name="l00890"></a>00890 <span class="vhdlchar">interrupt_mask_o</span> <= <a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a>;
|
| 178 |
|
|
<a name="l00891"></a>00891 <span class="vhdlkeyword">end</span>
|
| 179 |
|
|
<a name="l00892"></a>00892 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 180 |
|
|
<a name="l00893"></a>00893 <span class="vhdlchar">interrupt_mask_o</span> <= <span class="vhdllogic">3'b000</span>;
|
| 181 |
|
|
<a name="l00894"></a>00894 <a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a> <= <span class="vhdllogic">3'b000</span>;
|
| 182 |
|
|
<a name="l00895"></a>00895 <span class="vhdlkeyword">end</span>
|
| 183 |
|
|
<a name="l00896"></a>00896 <span class="vhdlkeyword">end</span>
|
| 184 |
12 |
alfik |
</pre></div>
|
| 185 |
|
|
</div>
|
| 186 |
|
|
</div>
|
| 187 |
|
|
<a class="anchor" id="af34450e53e6fd2fd36db7dff17caf063"></a><!-- doxytag: member="bus_control::ALWAYS_1" ref="af34450e53e6fd2fd36db7dff17caf063" args="CLK_I, reset_n" -->
|
| 188 |
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|
<div class="memitem">
|
| 189 |
|
|
<div class="memproto">
|
| 190 |
|
|
<table class="memname">
|
| 191 |
|
|
<tr>
|
| 192 |
|
|
<td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_1 <td></td>
|
| 193 |
13 |
alfik |
<td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">CLK_I</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> , </td>
|
| 194 |
12 |
alfik |
</tr>
|
| 195 |
|
|
<tr>
|
| 196 |
|
|
<td class="paramkey"></td>
|
| 197 |
|
|
<td></td>
|
| 198 |
13 |
alfik |
<td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a></b> <span class="vhdlchar"> </span></b> <em><span class="vhdlkeyword"></span></em> ) </td>
|
| 199 |
12 |
alfik |
</tr>
|
| 200 |
|
|
<code> [Always Construct]</code></td>
|
| 201 |
|
|
</tr>
|
| 202 |
|
|
</table>
|
| 203 |
|
|
</div>
|
| 204 |
|
|
<div class="memdoc">
|
| 205 |
|
|
|
| 206 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00900">900</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 207 |
12 |
alfik |
<div class="fragment"><pre class="fragment">
|
| 208 |
13 |
alfik |
<a name="l00900"></a>00900 <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">CLK_I</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a>) <span class="vhdlkeyword">begin</span>
|
| 209 |
|
|
<a name="l00901"></a>00901 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 210 |
|
|
<a name="l00902"></a>00902 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 211 |
|
|
<a name="l00903"></a>00903 <span class="vhdlchar">interrupt_trap_o</span> <= <span class="vhdllogic">8'd0</span>;
|
| 212 |
|
|
<a name="l00904"></a>00904 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 213 |
|
|
<a name="l00905"></a>00905 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 214 |
|
|
<a name="l00906"></a>00906 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 215 |
|
|
<a name="l00907"></a>00907
|
| 216 |
|
|
<a name="l00908"></a>00908 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 217 |
|
|
<a name="l00909"></a>00909 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 218 |
|
|
<a name="l00910"></a>00910
|
| 219 |
|
|
<a name="l00911"></a>00911 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 220 |
|
|
<a name="l00912"></a>00912 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <span class="vhdllogic">30'd0</span>;
|
| 221 |
|
|
<a name="l00913"></a>00913 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= <span class="vhdllogic">32'd0</span>;
|
| 222 |
|
|
<a name="l00914"></a>00914 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0</span>;
|
| 223 |
|
|
<a name="l00915"></a>00915 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 224 |
|
|
<a name="l00916"></a>00916 <a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 225 |
|
|
<a name="l00917"></a>00917 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 226 |
|
|
<a name="l00918"></a>00918 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 227 |
|
|
<a name="l00919"></a>00919 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 228 |
|
|
<a name="l00920"></a>00920 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <span class="vhdllogic">3'd0</span>;
|
| 229 |
|
|
<a name="l00921"></a>00921 <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <span class="vhdllogic">3'd0</span>;
|
| 230 |
|
|
<a name="l00922"></a>00922 <a class="code" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">reset_o</a> <= <span class="vhdllogic">1'b0</span>;
|
| 231 |
|
|
<a name="l00923"></a>00923 <span class="vhdlchar">blocked_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 232 |
|
|
<a name="l00924"></a>00924 <span class="vhdlchar">data_read_o</span> <= <span class="vhdllogic">32'd0</span>;
|
| 233 |
|
|
<a name="l00925"></a>00925 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 234 |
|
|
<a name="l00926"></a>00926 <span class="vhdlchar">rw_state_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 235 |
|
|
<a name="l00927"></a>00927 <span class="vhdlchar">fc_state_o</span> <= <span class="vhdllogic">3'd0</span>;
|
| 236 |
|
|
<a name="l00928"></a>00928 <span class="vhdlchar">fault_address_state_o</span> <= <span class="vhdllogic">32'd0</span>;
|
| 237 |
|
|
<a name="l00929"></a>00929 <a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> <= <span class="vhdllogic">2'b0</span>;
|
| 238 |
|
|
<a name="l00930"></a>00930 <a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a> <= <span class="vhdllogic">8'd0</span>;
|
| 239 |
|
|
<a name="l00931"></a>00931 <span class="vhdlkeyword">end</span>
|
| 240 |
|
|
<a name="l00932"></a>00932 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 241 |
|
|
<a name="l00933"></a>00933 <span class="vhdlkeyword">case</span>(<a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a>)
|
| 242 |
|
|
<a name="l00934"></a>00934 <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>: <span class="vhdlkeyword">begin</span>
|
| 243 |
|
|
<a name="l00935"></a>00935 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 244 |
|
|
<a name="l00936"></a>00936 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 245 |
|
|
<a name="l00937"></a>00937 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 246 |
|
|
<a name="l00938"></a>00938 <a class="code" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">reset_o</a> <= <span class="vhdllogic">1'b0</span>;
|
| 247 |
|
|
<a name="l00939"></a>00939 <span class="vhdlchar">blocked_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 248 |
|
|
<a name="l00940"></a>00940
|
| 249 |
|
|
<a name="l00941"></a>00941 <span class="keyword">// block</span>
|
| 250 |
|
|
<a name="l00942"></a>00942 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_blocked_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 251 |
|
|
<a name="l00943"></a>00943 <span class="vhdlchar">blocked_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 252 |
|
|
<a name="l00944"></a>00944 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a35c0778e16a225b839acc35705428b6a">S_BLOCKED</a>;
|
| 253 |
|
|
<a name="l00945"></a>00945 <span class="vhdlkeyword">end</span>
|
| 254 |
|
|
<a name="l00946"></a>00946 <span class="keyword">// reset</span>
|
| 255 |
|
|
<a name="l00947"></a>00947 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_reset_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 256 |
|
|
<a name="l00948"></a>00948 <a class="code" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">reset_o</a> <= <span class="vhdllogic">1'b1</span>;
|
| 257 |
|
|
<a name="l00949"></a>00949 <a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a> <= <span class="vhdllogic">8'd124</span>;
|
| 258 |
|
|
<a name="l00950"></a>00950 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a21f9753bb3594dcc9d190ef5c54071e6">S_RESET</a>;
|
| 259 |
|
|
<a name="l00951"></a>00951 <span class="vhdlkeyword">end</span>
|
| 260 |
|
|
<a name="l00952"></a>00952 <span class="keyword">// read</span>
|
| 261 |
|
|
<a name="l00953"></a>00953 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 262 |
|
|
<a name="l00954"></a>00954 <a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 263 |
|
|
<a name="l00955"></a>00955 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= (<span class="vhdlchar">address_type_i</span> == <span class="vhdllogic">1'b0</span>) ? <a class="code" href="classbus__control.html#ae4def0ea9761559826d03589c2727513">FC_SUPERVISOR_DATA</a> : <a class="code" href="classbus__control.html#ab1ee5e2a9796c9681a2401aaa7c623e3">FC_SUPERVISOR_PROGRAM</a>;
|
| 264 |
|
|
<a name="l00956"></a>00956 <span class="vhdlkeyword">else</span> <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= (<span class="vhdlchar">address_type_i</span> == <span class="vhdllogic">1'b0</span>) ? <a class="code" href="classbus__control.html#abc48f0e1c96b882d85f1b1033f985b61">FC_USER_DATA</a> : <a class="code" href="classbus__control.html#af182a23ace6536ef234233549e2de05c">FC_USER_PROGRAM</a>;
|
| 265 |
|
|
<a name="l00957"></a>00957
|
| 266 |
|
|
<a name="l00958"></a>00958 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b0</span>)) <span class="vhdlkeyword">begin</span> <span class="keyword">// WORD or LONG WORD</span>
|
| 267 |
|
|
<a name="l00959"></a>00959 <span class="vhdlchar">fault_address_state_o</span> <= <span class="vhdlchar">address_i</span>;
|
| 268 |
|
|
<a name="l00960"></a>00960 <span class="vhdlchar">rw_state_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 269 |
|
|
<a name="l00961"></a>00961 <span class="vhdlchar">fc_state_o</span> <= (<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) ? ((<span class="vhdlchar">address_type_i</span> == <span class="vhdllogic">1'b0</span>) ? <a class="code" href="classbus__control.html#ae4def0ea9761559826d03589c2727513">FC_SUPERVISOR_DATA</a> : <a class="code" href="classbus__control.html#ab1ee5e2a9796c9681a2401aaa7c623e3">FC_SUPERVISOR_PROGRAM</a>) :
|
| 270 |
|
|
<a name="l00962"></a>00962 ((<span class="vhdlchar">address_type_i</span> == <span class="vhdllogic">1'b0</span>) ? <a class="code" href="classbus__control.html#abc48f0e1c96b882d85f1b1033f985b61">FC_USER_DATA</a> : <a class="code" href="classbus__control.html#af182a23ace6536ef234233549e2de05c">FC_USER_PROGRAM</a>);
|
| 271 |
|
|
<a name="l00963"></a>00963 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a4d7a5b1d461b7f9e41ef71fe929ebc24">VECTOR_ADDRESS_TRAP</a>;
|
| 272 |
|
|
<a name="l00964"></a>00964
|
| 273 |
|
|
<a name="l00965"></a>00965 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 274 |
|
|
<a name="l00966"></a>00966 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 275 |
|
|
<a name="l00967"></a>00967 <span class="vhdlkeyword">end</span>
|
| 276 |
|
|
<a name="l00968"></a>00968 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 277 |
|
|
<a name="l00969"></a>00969 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 278 |
|
|
<a name="l00970"></a>00970 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <span class="vhdlchar">address_i</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 279 |
|
|
<a name="l00971"></a>00971 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span>)? <span class="vhdllogic">4'b1000</span> :
|
| 280 |
|
|
<a name="l00972"></a>00972 (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b01</span>)? <span class="vhdllogic">4'b0100</span> :
|
| 281 |
|
|
<a name="l00973"></a>00973 (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span>)? <span class="vhdllogic">4'b0010</span> :
|
| 282 |
|
|
<a name="l00974"></a>00974 (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b11</span>)? <span class="vhdllogic">4'b0001</span> :
|
| 283 |
|
|
<a name="l00975"></a>00975 (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">2'b0</span>)? <span class="vhdllogic">4'b1100</span> :
|
| 284 |
|
|
<a name="l00976"></a>00976 (<span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b0</span> && <span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">2'b1</span>)? <span class="vhdllogic">4'b0011</span> :
|
| 285 |
|
|
<a name="l00977"></a>00977 <span class="vhdllogic">4'b1111</span>;
|
| 286 |
|
|
<a name="l00978"></a>00978 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 287 |
|
|
<a name="l00979"></a>00979
|
| 288 |
|
|
<a name="l00980"></a>00980 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 289 |
|
|
<a name="l00981"></a>00981 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 290 |
|
|
<a name="l00982"></a>00982 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 291 |
|
|
<a name="l00983"></a>00983 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 292 |
|
|
<a name="l00984"></a>00984 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 293 |
|
|
<a name="l00985"></a>00985 <span class="vhdlkeyword">end</span>
|
| 294 |
|
|
<a name="l00986"></a>00986 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 295 |
|
|
<a name="l00987"></a>00987 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 296 |
|
|
<a name="l00988"></a>00988 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 297 |
|
|
<a name="l00989"></a>00989 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 298 |
|
|
<a name="l00990"></a>00990 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a>;
|
| 299 |
|
|
<a name="l00991"></a>00991 <span class="vhdlkeyword">end</span>
|
| 300 |
|
|
<a name="l00992"></a>00992 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 301 |
|
|
<a name="l00993"></a>00993 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 302 |
|
|
<a name="l00994"></a>00994 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 303 |
|
|
<a name="l00995"></a>00995 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 304 |
|
|
<a name="l00996"></a>00996 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 305 |
|
|
<a name="l00997"></a>00997 <span class="vhdlkeyword">end</span>
|
| 306 |
|
|
<a name="l00998"></a>00998
|
| 307 |
|
|
<a name="l00999"></a>00999 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a0957d5175230f9062a95b56e1db2fc53">S_READ_1</a>;
|
| 308 |
|
|
<a name="l01000"></a>01000 <span class="vhdlkeyword">end</span>
|
| 309 |
|
|
<a name="l01001"></a>01001 <span class="vhdlkeyword">end</span>
|
| 310 |
|
|
<a name="l01002"></a>01002 <span class="keyword">// write</span>
|
| 311 |
|
|
<a name="l01003"></a>01003 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_write_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 312 |
|
|
<a name="l01004"></a>01004 <a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 313 |
|
|
<a name="l01005"></a>01005 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <a class="code" href="classbus__control.html#ae4def0ea9761559826d03589c2727513">FC_SUPERVISOR_DATA</a>;
|
| 314 |
|
|
<a name="l01006"></a>01006 <span class="vhdlkeyword">else</span> <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <a class="code" href="classbus__control.html#abc48f0e1c96b882d85f1b1033f985b61">FC_USER_DATA</a>;
|
| 315 |
|
|
<a name="l01007"></a>01007
|
| 316 |
|
|
<a name="l01008"></a>01008 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span> <span class="keyword">// WORD or LONG WORD</span>
|
| 317 |
|
|
<a name="l01009"></a>01009 <span class="vhdlchar">fault_address_state_o</span> <= <span class="vhdlchar">address_i</span>;
|
| 318 |
|
|
<a name="l01010"></a>01010 <span class="vhdlchar">rw_state_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 319 |
|
|
<a name="l01011"></a>01011 <span class="vhdlchar">fc_state_o</span> <= (<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) ? <a class="code" href="classbus__control.html#ae4def0ea9761559826d03589c2727513">FC_SUPERVISOR_DATA</a> : <a class="code" href="classbus__control.html#abc48f0e1c96b882d85f1b1033f985b61">FC_USER_DATA</a>;
|
| 320 |
|
|
<a name="l01012"></a>01012 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a4d7a5b1d461b7f9e41ef71fe929ebc24">VECTOR_ADDRESS_TRAP</a>;
|
| 321 |
|
|
<a name="l01013"></a>01013
|
| 322 |
|
|
<a name="l01014"></a>01014 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 323 |
|
|
<a name="l01015"></a>01015 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 324 |
|
|
<a name="l01016"></a>01016 <span class="vhdlkeyword">end</span>
|
| 325 |
|
|
<a name="l01017"></a>01017 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 326 |
|
|
<a name="l01018"></a>01018 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 327 |
|
|
<a name="l01019"></a>01019 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <span class="vhdlchar">address_i</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 328 |
|
|
<a name="l01020"></a>01020 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 329 |
|
|
<a name="l01021"></a>01021
|
| 330 |
|
|
<a name="l01022"></a>01022 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 331 |
|
|
<a name="l01023"></a>01023 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>] };
|
| 332 |
|
|
<a name="l01024"></a>01024 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0011</span>;
|
| 333 |
|
|
<a name="l01025"></a>01025 <span class="vhdlkeyword">end</span>
|
| 334 |
|
|
<a name="l01026"></a>01026 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 335 |
|
|
<a name="l01027"></a>01027 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 336 |
|
|
<a name="l01028"></a>01028 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1111</span>;
|
| 337 |
|
|
<a name="l01029"></a>01029 <span class="vhdlkeyword">end</span>
|
| 338 |
|
|
<a name="l01030"></a>01030 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 339 |
|
|
<a name="l01031"></a>01031 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
| 340 |
|
|
<a name="l01032"></a>01032 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0011</span>;
|
| 341 |
|
|
<a name="l01033"></a>01033 <span class="vhdlkeyword">end</span>
|
| 342 |
|
|
<a name="l01034"></a>01034 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 343 |
|
|
<a name="l01035"></a>01035 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 344 |
|
|
<a name="l01036"></a>01036 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1100</span>;
|
| 345 |
|
|
<a name="l01037"></a>01037 <span class="vhdlkeyword">end</span>
|
| 346 |
|
|
<a name="l01038"></a>01038 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b11</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 347 |
|
|
<a name="l01039"></a>01039 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdllogic">24'b0</span>, <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 348 |
|
|
<a name="l01040"></a>01040 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0001</span>;
|
| 349 |
|
|
<a name="l01041"></a>01041 <span class="vhdlkeyword">end</span>
|
| 350 |
|
|
<a name="l01042"></a>01042 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 351 |
|
|
<a name="l01043"></a>01043 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdllogic">16'b0</span>, <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">8'b0</span> };
|
| 352 |
|
|
<a name="l01044"></a>01044 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0010</span>;
|
| 353 |
|
|
<a name="l01045"></a>01045 <span class="vhdlkeyword">end</span>
|
| 354 |
|
|
<a name="l01046"></a>01046 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b01</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 355 |
|
|
<a name="l01047"></a>01047 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdllogic">8'b0</span>, <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 356 |
|
|
<a name="l01048"></a>01048 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b0100</span>;
|
| 357 |
|
|
<a name="l01049"></a>01049 <span class="vhdlkeyword">end</span>
|
| 358 |
|
|
<a name="l01050"></a>01050 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 359 |
|
|
<a name="l01051"></a>01051 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">24'b0</span> };
|
| 360 |
|
|
<a name="l01052"></a>01052 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1000</span>;
|
| 361 |
|
|
<a name="l01053"></a>01053 <span class="vhdlkeyword">end</span>
|
| 362 |
|
|
<a name="l01054"></a>01054
|
| 363 |
|
|
<a name="l01055"></a>01055 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 364 |
|
|
<a name="l01056"></a>01056 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 365 |
|
|
<a name="l01057"></a>01057 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 366 |
|
|
<a name="l01058"></a>01058 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 367 |
|
|
<a name="l01059"></a>01059 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 368 |
|
|
<a name="l01060"></a>01060 <span class="vhdlkeyword">end</span>
|
| 369 |
|
|
<a name="l01061"></a>01061 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 370 |
|
|
<a name="l01062"></a>01062 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 371 |
|
|
<a name="l01063"></a>01063 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 372 |
|
|
<a name="l01064"></a>01064 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 373 |
|
|
<a name="l01065"></a>01065 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a>;
|
| 374 |
|
|
<a name="l01066"></a>01066 <span class="vhdlkeyword">end</span>
|
| 375 |
|
|
<a name="l01067"></a>01067 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 376 |
|
|
<a name="l01068"></a>01068 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 377 |
|
|
<a name="l01069"></a>01069 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 378 |
|
|
<a name="l01070"></a>01070 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 379 |
|
|
<a name="l01071"></a>01071 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 380 |
|
|
<a name="l01072"></a>01072 <span class="vhdlkeyword">end</span>
|
| 381 |
|
|
<a name="l01073"></a>01073
|
| 382 |
|
|
<a name="l01074"></a>01074 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a47878ecd24d5368e7396dd97ec9f4077">S_WRITE_1</a>;
|
| 383 |
|
|
<a name="l01075"></a>01075 <span class="vhdlkeyword">end</span>
|
| 384 |
|
|
<a name="l01076"></a>01076 <span class="vhdlkeyword">end</span>
|
| 385 |
|
|
<a name="l01077"></a>01077 <span class="keyword">// pc</span>
|
| 386 |
|
|
<a name="l01078"></a>01078 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">prefetch_ir_valid_o</span> == <span class="vhdllogic">1'b0</span> || <span class="vhdlchar">pc_change_i</span> != <span class="vhdllogic">2'b00</span>) <span class="vhdlkeyword">begin</span>
|
| 387 |
|
|
<a name="l01079"></a>01079
|
| 388 |
|
|
<a name="l01080"></a>01080 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">prefetch_ir_valid_o</span> == <span class="vhdllogic">1'b0</span> || <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b10</span> || <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b11</span>) <span class="vhdlkeyword">begin</span>
|
| 389 |
|
|
<a name="l01081"></a>01081 <span class="keyword">// load 4 words: [79:16] in 2,3 cycles</span>
|
| 390 |
|
|
<a name="l01082"></a>01082 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 391 |
|
|
<a name="l01083"></a>01083 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 392 |
|
|
<a name="l01084"></a>01084 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 393 |
|
|
<a name="l01085"></a>01085
|
| 394 |
|
|
<a name="l01086"></a>01086 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a058fe5f10d0f20cf2635fba74eafb30a">S_PC_0</a>;
|
| 395 |
|
|
<a name="l01087"></a>01087 <span class="vhdlkeyword">end</span>
|
| 396 |
|
|
<a name="l01088"></a>01088 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">prefetch_ir_valid_80_o</span> == <span class="vhdllogic">1'b0</span> && <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b01</span>) <span class="vhdlkeyword">begin</span>
|
| 397 |
|
|
<a name="l01089"></a>01089 <span class="keyword">// load 2 words: [31:0] in 1 cycle</span>
|
| 398 |
|
|
<a name="l01090"></a>01090 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 399 |
|
|
<a name="l01091"></a>01091 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 400 |
|
|
<a name="l01092"></a>01092 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 401 |
|
|
<a name="l01093"></a>01093
|
| 402 |
|
|
<a name="l01094"></a>01094 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">63</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 403 |
|
|
<a name="l01095"></a>01095 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a058fe5f10d0f20cf2635fba74eafb30a">S_PC_0</a>;
|
| 404 |
|
|
<a name="l01096"></a>01096 <span class="vhdlkeyword">end</span>
|
| 405 |
|
|
<a name="l01097"></a>01097 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 406 |
|
|
<a name="l01098"></a>01098 <span class="keyword">// do not load any words</span>
|
| 407 |
|
|
<a name="l01099"></a>01099 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 408 |
|
|
<a name="l01100"></a>01100 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 409 |
|
|
<a name="l01101"></a>01101 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 410 |
12 |
alfik |
<a name="l01102"></a>01102
|
| 411 |
13 |
alfik |
<a name="l01103"></a>01103 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">63</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 412 |
|
|
<a name="l01104"></a>01104 <span class="vhdlkeyword">end</span>
|
| 413 |
|
|
<a name="l01105"></a>01105
|
| 414 |
|
|
<a name="l01106"></a>01106
|
| 415 |
|
|
<a name="l01107"></a>01107 <span class="vhdlkeyword">end</span>
|
| 416 |
|
|
<a name="l01108"></a>01108 <span class="keyword">// interrupt</span>
|
| 417 |
|
|
<a name="l01109"></a>01109 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_interrupt_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 418 |
|
|
<a name="l01110"></a>01110 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 419 |
|
|
<a name="l01111"></a>01111 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= { <span class="vhdllogic">27'b111_1111_1111_1111_1111_1111_1111</span>, <a class="code" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a> };
|
| 420 |
|
|
<a name="l01112"></a>01112 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1111</span>;
|
| 421 |
|
|
<a name="l01113"></a>01113 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 422 |
|
|
<a name="l01114"></a>01114 <a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 423 |
|
|
<a name="l01115"></a>01115
|
| 424 |
|
|
<a name="l01116"></a>01116 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 425 |
|
|
<a name="l01117"></a>01117 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 426 |
|
|
<a name="l01118"></a>01118 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 427 |
|
|
<a name="l01119"></a>01119 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 428 |
|
|
<a name="l01120"></a>01120
|
| 429 |
|
|
<a name="l01121"></a>01121 <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <a class="code" href="classbus__control.html#aabcbc5528d37aad94c1c91f72abe9788">FC_CPU_SPACE</a>;
|
| 430 |
|
|
<a name="l01122"></a>01122
|
| 431 |
|
|
<a name="l01123"></a>01123 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a22028b6e9c3a87066084eeb7e3ea66dc">S_INT_1</a>;
|
| 432 |
|
|
<a name="l01124"></a>01124 <span class="vhdlkeyword">end</span>
|
| 433 |
|
|
<a name="l01125"></a>01125 <span class="vhdlkeyword">end</span>
|
| 434 |
12 |
alfik |
<a name="l01126"></a>01126
|
| 435 |
13 |
alfik |
<a name="l01127"></a>01127 <a class="code" href="classbus__control.html#a21f9753bb3594dcc9d190ef5c54071e6">S_RESET</a>: <span class="vhdlkeyword">begin</span>
|
| 436 |
|
|
<a name="l01128"></a>01128 <a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a> <= <a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a> - <span class="vhdllogic">8'd1</span>;
|
| 437 |
|
|
<a name="l01129"></a>01129
|
| 438 |
|
|
<a name="l01130"></a>01130 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a> == <span class="vhdllogic">8'd0</span>) <span class="vhdlkeyword">begin</span>
|
| 439 |
|
|
<a name="l01131"></a>01131 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 440 |
|
|
<a name="l01132"></a>01132 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 441 |
|
|
<a name="l01133"></a>01133 <span class="vhdlkeyword">end</span>
|
| 442 |
12 |
alfik |
<a name="l01134"></a>01134 <span class="vhdlkeyword">end</span>
|
| 443 |
|
|
<a name="l01135"></a>01135
|
| 444 |
13 |
alfik |
<a name="l01136"></a>01136 <a class="code" href="classbus__control.html#a35c0778e16a225b839acc35705428b6a">S_BLOCKED</a>: <span class="vhdlkeyword">begin</span>
|
| 445 |
|
|
<a name="l01137"></a>01137 <span class="vhdlkeyword">end</span>
|
| 446 |
|
|
<a name="l01138"></a>01138
|
| 447 |
|
|
<a name="l01139"></a>01139 <a class="code" href="classbus__control.html#a22028b6e9c3a87066084eeb7e3ea66dc">S_INT_1</a>: <span class="vhdlkeyword">begin</span>
|
| 448 |
|
|
<a name="l01140"></a>01140 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 449 |
|
|
<a name="l01141"></a>01141 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 450 |
|
|
<a name="l01142"></a>01142 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 451 |
|
|
<a name="l01143"></a>01143
|
| 452 |
|
|
<a name="l01144"></a>01144 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>];
|
| 453 |
|
|
<a name="l01145"></a>01145
|
| 454 |
|
|
<a name="l01146"></a>01146 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 455 |
|
|
<a name="l01147"></a>01147 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 456 |
|
|
<a name="l01148"></a>01148 <span class="vhdlkeyword">end</span>
|
| 457 |
|
|
<a name="l01149"></a>01149 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 458 |
|
|
<a name="l01150"></a>01150 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 459 |
|
|
<a name="l01151"></a>01151 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 460 |
|
|
<a name="l01152"></a>01152
|
| 461 |
|
|
<a name="l01153"></a>01153 <span class="vhdlchar">interrupt_trap_o</span> <= <span class="vhdllogic">8'd24</span> + { <span class="vhdllogic">5'b0</span>, <span class="vhdlchar">interrupt_mask_o</span> };
|
| 462 |
|
|
<a name="l01154"></a>01154
|
| 463 |
|
|
<a name="l01155"></a>01155 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 464 |
|
|
<a name="l01156"></a>01156 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 465 |
|
|
<a name="l01157"></a>01157 <span class="vhdlkeyword">end</span>
|
| 466 |
|
|
<a name="l01158"></a>01158 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 467 |
|
|
<a name="l01159"></a>01159 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 468 |
|
|
<a name="l01160"></a>01160 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 469 |
|
|
<a name="l01161"></a>01161
|
| 470 |
|
|
<a name="l01162"></a>01162 <span class="vhdlchar">interrupt_trap_o</span> <= <span class="vhdllogic">8'd24</span>; <span class="keyword">// spurious interrupt</span>
|
| 471 |
|
|
<a name="l01163"></a>01163
|
| 472 |
|
|
<a name="l01164"></a>01164 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 473 |
|
|
<a name="l01165"></a>01165 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 474 |
|
|
<a name="l01166"></a>01166 <span class="vhdlkeyword">end</span>
|
| 475 |
|
|
<a name="l01167"></a>01167 <span class="vhdlkeyword">end</span>
|
| 476 |
|
|
<a name="l01168"></a>01168
|
| 477 |
|
|
<a name="l01169"></a>01169 <a class="code" href="classbus__control.html#a058fe5f10d0f20cf2635fba74eafb30a">S_PC_0</a>: <span class="vhdlkeyword">begin</span>
|
| 478 |
|
|
<a name="l01170"></a>01170 <a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 479 |
|
|
<a name="l01171"></a>01171 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <a class="code" href="classbus__control.html#ab1ee5e2a9796c9681a2401aaa7c623e3">FC_SUPERVISOR_PROGRAM</a>;
|
| 480 |
|
|
<a name="l01172"></a>01172 <span class="vhdlkeyword">else</span> <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a> <= <a class="code" href="classbus__control.html#af182a23ace6536ef234233549e2de05c">FC_USER_PROGRAM</a>;
|
| 481 |
|
|
<a name="l01173"></a>01173
|
| 482 |
|
|
<a name="l01174"></a>01174 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 483 |
|
|
<a name="l01175"></a>01175 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 484 |
|
|
<a name="l01176"></a>01176 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 485 |
|
|
<a name="l01177"></a>01177 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 486 |
|
|
<a name="l01178"></a>01178
|
| 487 |
|
|
<a name="l01179"></a>01179 <span class="vhdlchar">fault_address_state_o</span> <= <span class="vhdlchar">pc_i</span>;
|
| 488 |
|
|
<a name="l01180"></a>01180 <span class="vhdlchar">rw_state_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 489 |
|
|
<a name="l01181"></a>01181 <span class="vhdlchar">fc_state_o</span> <= (<span class="vhdlchar">supervisor_i</span> == <span class="vhdllogic">1'b1</span>) ? <a class="code" href="classbus__control.html#ab1ee5e2a9796c9681a2401aaa7c623e3">FC_SUPERVISOR_PROGRAM</a> : <a class="code" href="classbus__control.html#af182a23ace6536ef234233549e2de05c">FC_USER_PROGRAM</a>;
|
| 490 |
|
|
<a name="l01182"></a>01182 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a4d7a5b1d461b7f9e41ef71fe929ebc24">VECTOR_ADDRESS_TRAP</a>;
|
| 491 |
|
|
<a name="l01183"></a>01183
|
| 492 |
|
|
<a name="l01184"></a>01184 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 493 |
|
|
<a name="l01185"></a>01185 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 494 |
|
|
<a name="l01186"></a>01186 <span class="vhdlkeyword">end</span>
|
| 495 |
|
|
<a name="l01187"></a>01187 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 496 |
|
|
<a name="l01188"></a>01188 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 497 |
12 |
alfik |
<a name="l01189"></a>01189
|
| 498 |
13 |
alfik |
<a name="l01190"></a>01190 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">prefetch_ir_valid_32_o</span> == <span class="vhdllogic">1'b0</span>) <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <span class="vhdlchar">pc_i</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 499 |
|
|
<a name="l01191"></a>01191 <span class="vhdlkeyword">else</span> <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <a class="code" href="classbus__control.html#a518be1f0ea917cc51c7843115db83ce1">pc_i_plus_6</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 500 |
|
|
<a name="l01192"></a>01192
|
| 501 |
|
|
<a name="l01193"></a>01193 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= (<span class="vhdlchar">pc_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span>)? <span class="vhdllogic">4'b0011</span> :
|
| 502 |
|
|
<a name="l01194"></a>01194 <span class="vhdllogic">4'b1111</span>;
|
| 503 |
|
|
<a name="l01195"></a>01195 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 504 |
|
|
<a name="l01196"></a>01196
|
| 505 |
|
|
<a name="l01197"></a>01197 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">prefetch_ir_valid_32_o</span> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 506 |
|
|
<a name="l01198"></a>01198 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 507 |
|
|
<a name="l01199"></a>01199 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 508 |
|
|
<a name="l01200"></a>01200 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 509 |
|
|
<a name="l01201"></a>01201 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a>;
|
| 510 |
|
|
<a name="l01202"></a>01202 <span class="vhdlkeyword">end</span>
|
| 511 |
|
|
<a name="l01203"></a>01203 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 512 |
|
|
<a name="l01204"></a>01204 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 513 |
|
|
<a name="l01205"></a>01205 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 514 |
|
|
<a name="l01206"></a>01206 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 515 |
|
|
<a name="l01207"></a>01207 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 516 |
|
|
<a name="l01208"></a>01208 <span class="vhdlkeyword">end</span>
|
| 517 |
12 |
alfik |
<a name="l01209"></a>01209
|
| 518 |
13 |
alfik |
<a name="l01210"></a>01210 <a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> <= <span class="vhdlchar">pc_change_i</span>;
|
| 519 |
|
|
<a name="l01211"></a>01211 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 520 |
|
|
<a name="l01212"></a>01212
|
| 521 |
|
|
<a name="l01213"></a>01213 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a0224e82b22d3f1272d6cb604df02fd65">S_PC_1</a>;
|
| 522 |
|
|
<a name="l01214"></a>01214 <span class="vhdlkeyword">end</span>
|
| 523 |
|
|
<a name="l01215"></a>01215 <span class="vhdlkeyword">end</span>
|
| 524 |
12 |
alfik |
<a name="l01216"></a>01216
|
| 525 |
13 |
alfik |
<a name="l01217"></a>01217 <a class="code" href="classbus__control.html#a0224e82b22d3f1272d6cb604df02fd65">S_PC_1</a>: <span class="vhdlkeyword">begin</span>
|
| 526 |
|
|
<a name="l01218"></a>01218 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_change_i</span> != <span class="vhdllogic">2'b00</span>) <a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> <= <span class="vhdlchar">pc_change_i</span>;
|
| 527 |
|
|
<a name="l01219"></a>01219
|
| 528 |
|
|
<a name="l01220"></a>01220 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 529 |
|
|
<a name="l01221"></a>01221 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> == <a class="code" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a>) <span class="vhdlkeyword">begin</span>
|
| 530 |
|
|
<a name="l01222"></a>01222 <span class="keyword">//CYC_O <= 1'b1;</span>
|
| 531 |
|
|
<a name="l01223"></a>01223 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <a class="code" href="classbus__control.html#ad4e505c885a6c941198d653beff91bf1">pc_i_plus_4</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 532 |
|
|
<a name="l01224"></a>01224 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1111</span>;
|
| 533 |
|
|
<a name="l01225"></a>01225 <span class="keyword">//STB_O <= 1'b1;</span>
|
| 534 |
|
|
<a name="l01226"></a>01226 <span class="keyword">//WE_O <= 1'b0;</span>
|
| 535 |
|
|
<a name="l01227"></a>01227
|
| 536 |
|
|
<a name="l01228"></a>01228 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span>) <span class="vhdlkeyword">begin</span>
|
| 537 |
|
|
<a name="l01229"></a>01229 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 538 |
|
|
<a name="l01230"></a>01230 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 539 |
|
|
<a name="l01231"></a>01231 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 540 |
|
|
<a name="l01232"></a>01232 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a>;
|
| 541 |
|
|
<a name="l01233"></a>01233 <span class="vhdlkeyword">end</span>
|
| 542 |
|
|
<a name="l01234"></a>01234 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 543 |
|
|
<a name="l01235"></a>01235 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 544 |
|
|
<a name="l01236"></a>01236 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 545 |
|
|
<a name="l01237"></a>01237 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 546 |
|
|
<a name="l01238"></a>01238 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 547 |
|
|
<a name="l01239"></a>01239 <span class="vhdlkeyword">end</span>
|
| 548 |
12 |
alfik |
<a name="l01240"></a>01240
|
| 549 |
13 |
alfik |
<a name="l01241"></a>01241 <span class="keyword">//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;</span>
|
| 550 |
|
|
<a name="l01242"></a>01242 <span class="keyword">//else fc_o <= FC_USER_PROGRAM;</span>
|
| 551 |
12 |
alfik |
<a name="l01243"></a>01243
|
| 552 |
13 |
alfik |
<a name="l01244"></a>01244 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span>) <span class="vhdlchar">prefetch_ir_o</span> <= { <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">64'b0</span> };
|
| 553 |
|
|
<a name="l01245"></a>01245 <span class="vhdlkeyword">else</span> <span class="vhdlchar">prefetch_ir_o</span> <= { <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">48'b0</span> };
|
| 554 |
|
|
<a name="l01246"></a>01246
|
| 555 |
|
|
<a name="l01247"></a>01247 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a84be1a92cbb681a472f3e78c50d48953">S_PC_3</a>;
|
| 556 |
|
|
<a name="l01248"></a>01248 <span class="vhdlkeyword">end</span>
|
| 557 |
|
|
<a name="l01249"></a>01249 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 558 |
|
|
<a name="l01250"></a>01250 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 559 |
|
|
<a name="l01251"></a>01251 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 560 |
|
|
<a name="l01252"></a>01252
|
| 561 |
|
|
<a name="l01253"></a>01253 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> == <span class="vhdllogic">2'b10</span> || <a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> == <span class="vhdllogic">2'b11</span> || <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b10</span> || <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b11</span>) <span class="vhdlkeyword">begin</span>
|
| 562 |
|
|
<a name="l01254"></a>01254 <span class="keyword">// load 4 words: [79:16] in 2,3 cycles</span>
|
| 563 |
|
|
<a name="l01255"></a>01255 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 564 |
|
|
<a name="l01256"></a>01256 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 565 |
|
|
<a name="l01257"></a>01257 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 566 |
|
|
<a name="l01258"></a>01258
|
| 567 |
|
|
<a name="l01259"></a>01259 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a058fe5f10d0f20cf2635fba74eafb30a">S_PC_0</a>;
|
| 568 |
|
|
<a name="l01260"></a>01260 <span class="vhdlkeyword">end</span>
|
| 569 |
|
|
<a name="l01261"></a>01261 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a> == <span class="vhdllogic">2'b01</span> || <span class="vhdlchar">pc_change_i</span> == <span class="vhdllogic">2'b01</span>) <span class="vhdlkeyword">begin</span>
|
| 570 |
|
|
<a name="l01262"></a>01262 <span class="keyword">// do not load any words</span>
|
| 571 |
|
|
<a name="l01263"></a>01263 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 572 |
|
|
<a name="l01264"></a>01264 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 573 |
|
|
<a name="l01265"></a>01265 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 574 |
|
|
<a name="l01266"></a>01266
|
| 575 |
|
|
<a name="l01267"></a>01267 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">63</span>:<span class="vhdllogic">32</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 576 |
|
|
<a name="l01268"></a>01268 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 577 |
|
|
<a name="l01269"></a>01269 <span class="vhdlkeyword">end</span>
|
| 578 |
|
|
<a name="l01270"></a>01270 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 579 |
|
|
<a name="l01271"></a>01271 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 580 |
|
|
<a name="l01272"></a>01272 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 581 |
|
|
<a name="l01273"></a>01273 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 582 |
|
|
<a name="l01274"></a>01274
|
| 583 |
|
|
<a name="l01275"></a>01275 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">79</span>:<span class="vhdllogic">32</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] };
|
| 584 |
|
|
<a name="l01276"></a>01276 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 585 |
|
|
<a name="l01277"></a>01277 <span class="vhdlkeyword">end</span>
|
| 586 |
|
|
<a name="l01278"></a>01278 <span class="vhdlkeyword">end</span>
|
| 587 |
|
|
<a name="l01279"></a>01279 <span class="vhdlkeyword">end</span>
|
| 588 |
|
|
<a name="l01280"></a>01280 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 589 |
|
|
<a name="l01281"></a>01281 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 590 |
|
|
<a name="l01282"></a>01282 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 591 |
|
|
<a name="l01283"></a>01283
|
| 592 |
|
|
<a name="l01284"></a>01284 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a4b9998b72c69db4dcd98755835413fda">S_PC_2</a>;
|
| 593 |
|
|
<a name="l01285"></a>01285 <span class="vhdlkeyword">end</span>
|
| 594 |
|
|
<a name="l01286"></a>01286 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 595 |
|
|
<a name="l01287"></a>01287 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 596 |
|
|
<a name="l01288"></a>01288 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 597 |
|
|
<a name="l01289"></a>01289
|
| 598 |
|
|
<a name="l01290"></a>01290 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 599 |
|
|
<a name="l01291"></a>01291 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 600 |
|
|
<a name="l01292"></a>01292 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 601 |
|
|
<a name="l01293"></a>01293 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 602 |
|
|
<a name="l01294"></a>01294
|
| 603 |
|
|
<a name="l01295"></a>01295 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 604 |
|
|
<a name="l01296"></a>01296 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 605 |
|
|
<a name="l01297"></a>01297 <span class="vhdlkeyword">end</span>
|
| 606 |
|
|
<a name="l01298"></a>01298 <span class="vhdlkeyword">end</span>
|
| 607 |
|
|
<a name="l01299"></a>01299 <a class="code" href="classbus__control.html#a4b9998b72c69db4dcd98755835413fda">S_PC_2</a>: <span class="vhdlkeyword">begin</span>
|
| 608 |
|
|
<a name="l01300"></a>01300 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 609 |
|
|
<a name="l01301"></a>01301 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 610 |
|
|
<a name="l01302"></a>01302
|
| 611 |
|
|
<a name="l01303"></a>01303 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a0224e82b22d3f1272d6cb604df02fd65">S_PC_1</a>;
|
| 612 |
|
|
<a name="l01304"></a>01304 <span class="vhdlkeyword">end</span>
|
| 613 |
|
|
<a name="l01305"></a>01305 <a class="code" href="classbus__control.html#a84be1a92cbb681a472f3e78c50d48953">S_PC_3</a>: <span class="vhdlkeyword">begin</span>
|
| 614 |
|
|
<a name="l01306"></a>01306 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 615 |
|
|
<a name="l01307"></a>01307 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">pc_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span>) <span class="vhdlkeyword">begin</span>
|
| 616 |
|
|
<a name="l01308"></a>01308 <span class="keyword">//CYC_O <= 1'b1;</span>
|
| 617 |
|
|
<a name="l01309"></a>01309 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <a class="code" href="classbus__control.html#a518be1f0ea917cc51c7843115db83ce1">pc_i_plus_6</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 618 |
|
|
<a name="l01310"></a>01310 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1111</span>;
|
| 619 |
|
|
<a name="l01311"></a>01311 <span class="keyword">//STB_O <= 1'b1;</span>
|
| 620 |
|
|
<a name="l01312"></a>01312 <span class="keyword">//WE_O <= 1'b0;</span>
|
| 621 |
|
|
<a name="l01313"></a>01313
|
| 622 |
|
|
<a name="l01314"></a>01314 <a class="code" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 623 |
|
|
<a name="l01315"></a>01315 <a class="code" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 624 |
|
|
<a name="l01316"></a>01316 <a class="code" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 625 |
|
|
<a name="l01317"></a>01317 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 626 |
12 |
alfik |
<a name="l01318"></a>01318
|
| 627 |
13 |
alfik |
<a name="l01319"></a>01319 <span class="keyword">//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;</span>
|
| 628 |
|
|
<a name="l01320"></a>01320 <span class="keyword">//else fc_o <= FC_USER_PROGRAM;</span>
|
| 629 |
|
|
<a name="l01321"></a>01321
|
| 630 |
|
|
<a name="l01322"></a>01322 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">79</span>:<span class="vhdllogic">64</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">32'b0</span> };
|
| 631 |
|
|
<a name="l01323"></a>01323
|
| 632 |
|
|
<a name="l01324"></a>01324 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#abdb432663a596db90688fa0fa9d8d603">S_PC_5</a>;
|
| 633 |
|
|
<a name="l01325"></a>01325 <span class="vhdlkeyword">end</span>
|
| 634 |
|
|
<a name="l01326"></a>01326 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 635 |
|
|
<a name="l01327"></a>01327 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 636 |
|
|
<a name="l01328"></a>01328 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 637 |
|
|
<a name="l01329"></a>01329
|
| 638 |
|
|
<a name="l01330"></a>01330 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">79</span>:<span class="vhdllogic">48</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 639 |
|
|
<a name="l01331"></a>01331
|
| 640 |
|
|
<a name="l01332"></a>01332 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 641 |
|
|
<a name="l01333"></a>01333 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 642 |
|
|
<a name="l01334"></a>01334 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 643 |
|
|
<a name="l01335"></a>01335 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 644 |
|
|
<a name="l01336"></a>01336 <span class="vhdlkeyword">end</span>
|
| 645 |
|
|
<a name="l01337"></a>01337 <span class="vhdlkeyword">end</span>
|
| 646 |
|
|
<a name="l01338"></a>01338 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 647 |
|
|
<a name="l01339"></a>01339 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 648 |
|
|
<a name="l01340"></a>01340 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 649 |
|
|
<a name="l01341"></a>01341
|
| 650 |
|
|
<a name="l01342"></a>01342 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#aec52b8e16695194dcbfefab239d8a94a">S_PC_4</a>;
|
| 651 |
|
|
<a name="l01343"></a>01343 <span class="vhdlkeyword">end</span>
|
| 652 |
|
|
<a name="l01344"></a>01344 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 653 |
|
|
<a name="l01345"></a>01345 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 654 |
|
|
<a name="l01346"></a>01346 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 655 |
|
|
<a name="l01347"></a>01347
|
| 656 |
|
|
<a name="l01348"></a>01348 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 657 |
|
|
<a name="l01349"></a>01349 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 658 |
|
|
<a name="l01350"></a>01350 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 659 |
|
|
<a name="l01351"></a>01351 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 660 |
|
|
<a name="l01352"></a>01352
|
| 661 |
|
|
<a name="l01353"></a>01353 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 662 |
|
|
<a name="l01354"></a>01354 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 663 |
|
|
<a name="l01355"></a>01355 <span class="vhdlkeyword">end</span>
|
| 664 |
|
|
<a name="l01356"></a>01356 <span class="vhdlkeyword">end</span>
|
| 665 |
|
|
<a name="l01357"></a>01357 <a class="code" href="classbus__control.html#aec52b8e16695194dcbfefab239d8a94a">S_PC_4</a>: <span class="vhdlkeyword">begin</span>
|
| 666 |
|
|
<a name="l01358"></a>01358 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 667 |
|
|
<a name="l01359"></a>01359 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 668 |
|
|
<a name="l01360"></a>01360
|
| 669 |
|
|
<a name="l01361"></a>01361 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a84be1a92cbb681a472f3e78c50d48953">S_PC_3</a>;
|
| 670 |
|
|
<a name="l01362"></a>01362 <span class="vhdlkeyword">end</span>
|
| 671 |
|
|
<a name="l01363"></a>01363 <a class="code" href="classbus__control.html#abdb432663a596db90688fa0fa9d8d603">S_PC_5</a>: <span class="vhdlkeyword">begin</span>
|
| 672 |
|
|
<a name="l01364"></a>01364 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 673 |
|
|
<a name="l01365"></a>01365 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 674 |
|
|
<a name="l01366"></a>01366 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 675 |
|
|
<a name="l01367"></a>01367
|
| 676 |
|
|
<a name="l01368"></a>01368 <span class="vhdlchar">prefetch_ir_o</span> <= { <span class="vhdlchar">prefetch_ir_o</span>[<span class="vhdllogic">79</span>:<span class="vhdllogic">32</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>] };
|
| 677 |
|
|
<a name="l01369"></a>01369
|
| 678 |
|
|
<a name="l01370"></a>01370 <span class="vhdlchar">prefetch_ir_valid_32_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 679 |
|
|
<a name="l01371"></a>01371 <span class="vhdlchar">prefetch_ir_valid_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 680 |
|
|
<a name="l01372"></a>01372 <span class="vhdlchar">prefetch_ir_valid_80_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 681 |
|
|
<a name="l01373"></a>01373 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 682 |
|
|
<a name="l01374"></a>01374 <span class="vhdlkeyword">end</span>
|
| 683 |
|
|
<a name="l01375"></a>01375 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 684 |
|
|
<a name="l01376"></a>01376 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 685 |
|
|
<a name="l01377"></a>01377 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 686 |
|
|
<a name="l01378"></a>01378
|
| 687 |
|
|
<a name="l01379"></a>01379 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a95ac5f10cc1642a474302d109678e2c2">S_PC_6</a>;
|
| 688 |
|
|
<a name="l01380"></a>01380 <span class="vhdlkeyword">end</span>
|
| 689 |
|
|
<a name="l01381"></a>01381 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 690 |
|
|
<a name="l01382"></a>01382 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 691 |
|
|
<a name="l01383"></a>01383 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 692 |
|
|
<a name="l01384"></a>01384
|
| 693 |
|
|
<a name="l01385"></a>01385 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 694 |
|
|
<a name="l01386"></a>01386 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 695 |
|
|
<a name="l01387"></a>01387 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 696 |
|
|
<a name="l01388"></a>01388 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 697 |
|
|
<a name="l01389"></a>01389
|
| 698 |
|
|
<a name="l01390"></a>01390 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 699 |
|
|
<a name="l01391"></a>01391 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 700 |
|
|
<a name="l01392"></a>01392 <span class="vhdlkeyword">end</span>
|
| 701 |
|
|
<a name="l01393"></a>01393 <span class="vhdlkeyword">end</span>
|
| 702 |
|
|
<a name="l01394"></a>01394 <a class="code" href="classbus__control.html#a95ac5f10cc1642a474302d109678e2c2">S_PC_6</a>: <span class="vhdlkeyword">begin</span>
|
| 703 |
|
|
<a name="l01395"></a>01395 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 704 |
|
|
<a name="l01396"></a>01396 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 705 |
12 |
alfik |
<a name="l01397"></a>01397
|
| 706 |
13 |
alfik |
<a name="l01398"></a>01398 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#abdb432663a596db90688fa0fa9d8d603">S_PC_5</a>;
|
| 707 |
|
|
<a name="l01399"></a>01399 <span class="vhdlkeyword">end</span>
|
| 708 |
|
|
<a name="l01400"></a>01400
|
| 709 |
|
|
<a name="l01401"></a>01401 <span class="keyword">//*******************</span>
|
| 710 |
|
|
<a name="l01402"></a>01402 <a class="code" href="classbus__control.html#a0957d5175230f9062a95b56e1db2fc53">S_READ_1</a>: <span class="vhdlkeyword">begin</span>
|
| 711 |
|
|
<a name="l01403"></a>01403 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 712 |
|
|
<a name="l01404"></a>01404 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 713 |
|
|
<a name="l01405"></a>01405 <span class="keyword">//CYC_O <= 1'b1;</span>
|
| 714 |
|
|
<a name="l01406"></a>01406 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <a class="code" href="classbus__control.html#af8d1410047baf49f9a20acaf85010d8f">address_i_plus_4</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 715 |
|
|
<a name="l01407"></a>01407 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1100</span>;
|
| 716 |
|
|
<a name="l01408"></a>01408 <span class="keyword">//STB_O <= 1'b1;</span>
|
| 717 |
|
|
<a name="l01409"></a>01409 <span class="keyword">//WE_O <= 1'b0;</span>
|
| 718 |
|
|
<a name="l01410"></a>01410
|
| 719 |
|
|
<a name="l01411"></a>01411 <span class="keyword">//SGL_O <= 1'b0;</span>
|
| 720 |
|
|
<a name="l01412"></a>01412 <span class="keyword">//BLK_O <= 1'b1;</span>
|
| 721 |
|
|
<a name="l01413"></a>01413 <span class="keyword">//RMW_O <= 1'b0;</span>
|
| 722 |
|
|
<a name="l01414"></a>01414 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 723 |
12 |
alfik |
<a name="l01415"></a>01415
|
| 724 |
13 |
alfik |
<a name="l01416"></a>01416 <span class="keyword">//if(supervisor_i == 1'b1) fc_o <= (address_type_i == 1'b0) ? FC_SUPERVISOR_DATA : FC_SUPERVISOR_PROGRAM;</span>
|
| 725 |
|
|
<a name="l01417"></a>01417 <span class="keyword">//else fc_o <= (address_type_i == 1'b0) ? FC_USER_DATA : FC_USER_PROGRAM;</span>
|
| 726 |
|
|
<a name="l01418"></a>01418
|
| 727 |
|
|
<a name="l01419"></a>01419 <span class="vhdlchar">data_read_o</span> <= { <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 728 |
|
|
<a name="l01420"></a>01420
|
| 729 |
|
|
<a name="l01421"></a>01421 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a3067a17da274e211d0877d25ac1a1dec">S_READ_2</a>;
|
| 730 |
|
|
<a name="l01422"></a>01422 <span class="vhdlkeyword">end</span>
|
| 731 |
|
|
<a name="l01423"></a>01423 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 732 |
|
|
<a name="l01424"></a>01424 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">read_modify_write_i</span> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 733 |
|
|
<a name="l01425"></a>01425 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 734 |
|
|
<a name="l01426"></a>01426 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 735 |
|
|
<a name="l01427"></a>01427 <span class="vhdlkeyword">end</span>
|
| 736 |
|
|
<a name="l01428"></a>01428 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 737 |
|
|
<a name="l01429"></a>01429 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 738 |
|
|
<a name="l01430"></a>01430 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 739 |
|
|
<a name="l01431"></a>01431 <span class="vhdlkeyword">end</span>
|
| 740 |
|
|
<a name="l01432"></a>01432
|
| 741 |
|
|
<a name="l01433"></a>01433 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">0</span>];
|
| 742 |
|
|
<a name="l01434"></a>01434 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] };
|
| 743 |
|
|
<a name="l01435"></a>01435 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">1</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">16</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>] };
|
| 744 |
|
|
<a name="l01436"></a>01436 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b11</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">7</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>] };
|
| 745 |
|
|
<a name="l01437"></a>01437 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">15</span>:<span class="vhdllogic">8</span>] };
|
| 746 |
|
|
<a name="l01438"></a>01438 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b01</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">23</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">23</span>:<span class="vhdllogic">16</span>] };
|
| 747 |
|
|
<a name="l01439"></a>01439 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b00</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlchar">data_read_o</span> <= { {<span class="vhdllogic">24</span>{<a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>]}}, <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">24</span>] };
|
| 748 |
|
|
<a name="l01440"></a>01440
|
| 749 |
|
|
<a name="l01441"></a>01441 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 750 |
|
|
<a name="l01442"></a>01442 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 751 |
|
|
<a name="l01443"></a>01443 <span class="vhdlkeyword">end</span>
|
| 752 |
|
|
<a name="l01444"></a>01444 <span class="vhdlkeyword">end</span>
|
| 753 |
|
|
<a name="l01445"></a>01445 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 754 |
|
|
<a name="l01446"></a>01446 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 755 |
|
|
<a name="l01447"></a>01447 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 756 |
|
|
<a name="l01448"></a>01448
|
| 757 |
|
|
<a name="l01449"></a>01449 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 758 |
|
|
<a name="l01450"></a>01450 <span class="vhdlkeyword">end</span>
|
| 759 |
|
|
<a name="l01451"></a>01451 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 760 |
|
|
<a name="l01452"></a>01452 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 761 |
|
|
<a name="l01453"></a>01453 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 762 |
|
|
<a name="l01454"></a>01454
|
| 763 |
|
|
<a name="l01455"></a>01455 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 764 |
|
|
<a name="l01456"></a>01456 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 765 |
|
|
<a name="l01457"></a>01457 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 766 |
|
|
<a name="l01458"></a>01458 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 767 |
|
|
<a name="l01459"></a>01459
|
| 768 |
|
|
<a name="l01460"></a>01460 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 769 |
|
|
<a name="l01461"></a>01461 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 770 |
|
|
<a name="l01462"></a>01462 <span class="vhdlkeyword">end</span>
|
| 771 |
|
|
<a name="l01463"></a>01463 <span class="vhdlkeyword">end</span>
|
| 772 |
|
|
<a name="l01464"></a>01464 <a class="code" href="classbus__control.html#a3067a17da274e211d0877d25ac1a1dec">S_READ_2</a>: <span class="vhdlkeyword">begin</span>
|
| 773 |
|
|
<a name="l01465"></a>01465 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 774 |
|
|
<a name="l01466"></a>01466 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 775 |
|
|
<a name="l01467"></a>01467 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 776 |
|
|
<a name="l01468"></a>01468
|
| 777 |
|
|
<a name="l01469"></a>01469 <span class="vhdlchar">data_read_o</span> <= { <span class="vhdlchar">data_read_o</span>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>], <a class="code" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">16</span>] };
|
| 778 |
12 |
alfik |
<a name="l01470"></a>01470
|
| 779 |
13 |
alfik |
<a name="l01471"></a>01471 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 780 |
|
|
<a name="l01472"></a>01472 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 781 |
|
|
<a name="l01473"></a>01473
|
| 782 |
|
|
<a name="l01474"></a>01474 <span class="vhdlkeyword">end</span>
|
| 783 |
|
|
<a name="l01475"></a>01475 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 784 |
|
|
<a name="l01476"></a>01476 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 785 |
|
|
<a name="l01477"></a>01477 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 786 |
|
|
<a name="l01478"></a>01478
|
| 787 |
|
|
<a name="l01479"></a>01479 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#ae156bee4c9bdf06b34803d8d68d9f50f">S_READ_3</a>;
|
| 788 |
|
|
<a name="l01480"></a>01480 <span class="vhdlkeyword">end</span>
|
| 789 |
|
|
<a name="l01481"></a>01481 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 790 |
|
|
<a name="l01482"></a>01482 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 791 |
|
|
<a name="l01483"></a>01483 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 792 |
|
|
<a name="l01484"></a>01484
|
| 793 |
|
|
<a name="l01485"></a>01485 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 794 |
|
|
<a name="l01486"></a>01486 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 795 |
|
|
<a name="l01487"></a>01487 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 796 |
|
|
<a name="l01488"></a>01488 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 797 |
|
|
<a name="l01489"></a>01489
|
| 798 |
|
|
<a name="l01490"></a>01490 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 799 |
|
|
<a name="l01491"></a>01491 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 800 |
|
|
<a name="l01492"></a>01492 <span class="vhdlkeyword">end</span>
|
| 801 |
|
|
<a name="l01493"></a>01493
|
| 802 |
|
|
<a name="l01494"></a>01494 <span class="vhdlkeyword">end</span>
|
| 803 |
|
|
<a name="l01495"></a>01495 <a class="code" href="classbus__control.html#ae156bee4c9bdf06b34803d8d68d9f50f">S_READ_3</a>: <span class="vhdlkeyword">begin</span>
|
| 804 |
|
|
<a name="l01496"></a>01496 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 805 |
|
|
<a name="l01497"></a>01497 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 806 |
12 |
alfik |
<a name="l01498"></a>01498
|
| 807 |
13 |
alfik |
<a name="l01499"></a>01499 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a3067a17da274e211d0877d25ac1a1dec">S_READ_2</a>;
|
| 808 |
|
|
<a name="l01500"></a>01500 <span class="vhdlkeyword">end</span>
|
| 809 |
|
|
<a name="l01501"></a>01501
|
| 810 |
|
|
<a name="l01502"></a>01502
|
| 811 |
|
|
<a name="l01503"></a>01503 <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>: <span class="vhdlkeyword">begin</span>
|
| 812 |
|
|
<a name="l01504"></a>01504 <span class="vhdlchar">jmp_address_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 813 |
|
|
<a name="l01505"></a>01505 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 814 |
|
|
<a name="l01506"></a>01506
|
| 815 |
|
|
<a name="l01507"></a>01507 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">do_read_i</span> == <span class="vhdllogic">1'b0</span> && <span class="vhdlchar">do_write_i</span> == <span class="vhdllogic">1'b0</span> && <span class="vhdlchar">do_interrupt_i</span> == <span class="vhdllogic">1'b0</span> && <span class="vhdlchar">do_reset_i</span> == <span class="vhdllogic">1'b0</span>) <span class="vhdlkeyword">begin</span>
|
| 816 |
|
|
<a name="l01508"></a>01508 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b0</span>;
|
| 817 |
|
|
<a name="l01509"></a>01509 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 818 |
|
|
<a name="l01510"></a>01510 <span class="vhdlkeyword">end</span>
|
| 819 |
|
|
<a name="l01511"></a>01511 <span class="vhdlkeyword">end</span>
|
| 820 |
|
|
<a name="l01512"></a>01512
|
| 821 |
|
|
<a name="l01513"></a>01513 <span class="keyword">//**********************</span>
|
| 822 |
|
|
<a name="l01514"></a>01514 <a class="code" href="classbus__control.html#a47878ecd24d5368e7396dd97ec9f4077">S_WRITE_1</a>: <span class="vhdlkeyword">begin</span>
|
| 823 |
|
|
<a name="l01515"></a>01515 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 824 |
|
|
<a name="l01516"></a>01516 <span class="vhdlkeyword">if</span>(<span class="vhdlchar">address_i</span>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] == <span class="vhdllogic">2'b10</span> && <span class="vhdlchar">size_i</span>[<span class="vhdllogic">2</span>] == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 825 |
|
|
<a name="l01517"></a>01517 <span class="keyword">//CYC_O <= 1'b1;</span>
|
| 826 |
|
|
<a name="l01518"></a>01518 <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a> <= <a class="code" href="classbus__control.html#af8d1410047baf49f9a20acaf85010d8f">address_i_plus_4</a>[<span class="vhdllogic">31</span>:<span class="vhdllogic">2</span>];
|
| 827 |
|
|
<a name="l01519"></a>01519 <span class="keyword">//STB_O <= 1'b1;</span>
|
| 828 |
|
|
<a name="l01520"></a>01520 <span class="keyword">//WE_O <= 1'b1;</span>
|
| 829 |
12 |
alfik |
<a name="l01521"></a>01521
|
| 830 |
13 |
alfik |
<a name="l01522"></a>01522 <a class="code" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a> <= { <span class="vhdlchar">data_write_i</span>[<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>], <span class="vhdllogic">16'b0</span> };
|
| 831 |
|
|
<a name="l01523"></a>01523 <a class="code" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a> <= <span class="vhdllogic">4'b1100</span>;
|
| 832 |
|
|
<a name="l01524"></a>01524
|
| 833 |
|
|
<a name="l01525"></a>01525 <span class="keyword">//SGL_O <= 1'b0;</span>
|
| 834 |
|
|
<a name="l01526"></a>01526 <span class="keyword">//BLK_O <= 1'b1;</span>
|
| 835 |
|
|
<a name="l01527"></a>01527 <span class="keyword">//RMW_O <= 1'b0;</span>
|
| 836 |
|
|
<a name="l01528"></a>01528 <a class="code" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a> <= <a class="code" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a>;
|
| 837 |
12 |
alfik |
<a name="l01529"></a>01529
|
| 838 |
13 |
alfik |
<a name="l01530"></a>01530 <span class="keyword">//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_DATA;</span>
|
| 839 |
|
|
<a name="l01531"></a>01531 <span class="keyword">//else fc_o <= FC_USER_DATA;</span>
|
| 840 |
|
|
<a name="l01532"></a>01532
|
| 841 |
|
|
<a name="l01533"></a>01533 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a4aaa0182c2987111710dd7a7e5f23609">S_WRITE_2</a>;
|
| 842 |
|
|
<a name="l01534"></a>01534 <span class="vhdlkeyword">end</span>
|
| 843 |
|
|
<a name="l01535"></a>01535 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
|
| 844 |
|
|
<a name="l01536"></a>01536 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 845 |
|
|
<a name="l01537"></a>01537 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 846 |
|
|
<a name="l01538"></a>01538
|
| 847 |
|
|
<a name="l01539"></a>01539 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 848 |
|
|
<a name="l01540"></a>01540 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 849 |
|
|
<a name="l01541"></a>01541 <span class="vhdlkeyword">end</span>
|
| 850 |
|
|
<a name="l01542"></a>01542 <span class="vhdlkeyword">end</span>
|
| 851 |
|
|
<a name="l01543"></a>01543 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 852 |
|
|
<a name="l01544"></a>01544 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 853 |
|
|
<a name="l01545"></a>01545 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 854 |
|
|
<a name="l01546"></a>01546
|
| 855 |
|
|
<a name="l01547"></a>01547 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a>;
|
| 856 |
|
|
<a name="l01548"></a>01548 <span class="vhdlkeyword">end</span>
|
| 857 |
|
|
<a name="l01549"></a>01549 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 858 |
|
|
<a name="l01550"></a>01550 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 859 |
|
|
<a name="l01551"></a>01551 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 860 |
|
|
<a name="l01552"></a>01552
|
| 861 |
|
|
<a name="l01553"></a>01553 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 862 |
|
|
<a name="l01554"></a>01554 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 863 |
|
|
<a name="l01555"></a>01555 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 864 |
|
|
<a name="l01556"></a>01556 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 865 |
|
|
<a name="l01557"></a>01557
|
| 866 |
|
|
<a name="l01558"></a>01558 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 867 |
|
|
<a name="l01559"></a>01559 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 868 |
|
|
<a name="l01560"></a>01560 <span class="vhdlkeyword">end</span>
|
| 869 |
|
|
<a name="l01561"></a>01561
|
| 870 |
|
|
<a name="l01562"></a>01562 <span class="vhdlkeyword">end</span>
|
| 871 |
|
|
<a name="l01563"></a>01563 <a class="code" href="classbus__control.html#a4aaa0182c2987111710dd7a7e5f23609">S_WRITE_2</a>: <span class="vhdlkeyword">begin</span>
|
| 872 |
|
|
<a name="l01564"></a>01564 <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 873 |
|
|
<a name="l01565"></a>01565 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 874 |
|
|
<a name="l01566"></a>01566 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 875 |
12 |
alfik |
<a name="l01567"></a>01567
|
| 876 |
13 |
alfik |
<a name="l01568"></a>01568 <span class="vhdlchar">finished_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 877 |
|
|
<a name="l01569"></a>01569 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 878 |
|
|
<a name="l01570"></a>01570
|
| 879 |
|
|
<a name="l01571"></a>01571 <span class="vhdlkeyword">end</span>
|
| 880 |
|
|
<a name="l01572"></a>01572 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 881 |
|
|
<a name="l01573"></a>01573 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 882 |
|
|
<a name="l01574"></a>01574 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 883 |
|
|
<a name="l01575"></a>01575
|
| 884 |
|
|
<a name="l01576"></a>01576 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a7c1c733e80689349399716f442a5db8d">S_WRITE_3</a>;
|
| 885 |
|
|
<a name="l01577"></a>01577 <span class="vhdlkeyword">end</span>
|
| 886 |
|
|
<a name="l01578"></a>01578 <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a> == <span class="vhdllogic">1'b1</span>) <span class="vhdlkeyword">begin</span>
|
| 887 |
|
|
<a name="l01579"></a>01579 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 888 |
|
|
<a name="l01580"></a>01580 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b0</span>;
|
| 889 |
|
|
<a name="l01581"></a>01581
|
| 890 |
|
|
<a name="l01582"></a>01582 <span class="vhdlchar">fault_address_state_o</span> <= { <a class="code" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a>, <span class="vhdllogic">2'b00</span> };
|
| 891 |
|
|
<a name="l01583"></a>01583 <span class="vhdlchar">rw_state_o</span> <= ~<a class="code" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a>;
|
| 892 |
|
|
<a name="l01584"></a>01584 <span class="vhdlchar">fc_state_o</span> <= <a class="code" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a>;
|
| 893 |
|
|
<a name="l01585"></a>01585 <span class="vhdlchar">interrupt_trap_o</span> <= <a class="code" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a>;
|
| 894 |
|
|
<a name="l01586"></a>01586
|
| 895 |
|
|
<a name="l01587"></a>01587 <span class="vhdlchar">jmp_bus_trap_o</span> <= <span class="vhdllogic">1'b1</span>;
|
| 896 |
|
|
<a name="l01588"></a>01588 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a>;
|
| 897 |
|
|
<a name="l01589"></a>01589 <span class="vhdlkeyword">end</span>
|
| 898 |
|
|
<a name="l01590"></a>01590
|
| 899 |
|
|
<a name="l01591"></a>01591 <span class="vhdlkeyword">end</span>
|
| 900 |
|
|
<a name="l01592"></a>01592 <a class="code" href="classbus__control.html#a7c1c733e80689349399716f442a5db8d">S_WRITE_3</a>: <span class="vhdlkeyword">begin</span>
|
| 901 |
|
|
<a name="l01593"></a>01593 <a class="code" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 902 |
|
|
<a name="l01594"></a>01594 <a class="code" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a> <= <span class="vhdllogic">1'b1</span>;
|
| 903 |
12 |
alfik |
<a name="l01595"></a>01595
|
| 904 |
13 |
alfik |
<a name="l01596"></a>01596 <a class="code" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a> <= <a class="code" href="classbus__control.html#a4aaa0182c2987111710dd7a7e5f23609">S_WRITE_2</a>;
|
| 905 |
|
|
<a name="l01597"></a>01597 <span class="vhdlkeyword">end</span>
|
| 906 |
|
|
<a name="l01598"></a>01598
|
| 907 |
|
|
<a name="l01599"></a>01599 <span class="vhdlkeyword">endcase</span>
|
| 908 |
|
|
<a name="l01600"></a>01600 <span class="vhdlkeyword">end</span>
|
| 909 |
|
|
<a name="l01601"></a>01601 <span class="vhdlkeyword">end</span>
|
| 910 |
12 |
alfik |
</pre></div>
|
| 911 |
|
|
</div>
|
| 912 |
|
|
</div>
|
| 913 |
|
|
<hr/><h2>Member Data Documentation</h2>
|
| 914 |
13 |
alfik |
<a class="anchor" id="a21f9753bb3594dcc9d190ef5c54071e6"></a><!-- doxytag: member="bus_control::S_RESET" ref="a21f9753bb3594dcc9d190ef5c54071e6" args="5'd1" -->
|
| 915 |
12 |
alfik |
<div class="memitem">
|
| 916 |
|
|
<div class="memproto">
|
| 917 |
|
|
<table class="memname">
|
| 918 |
|
|
<tr>
|
| 919 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a21f9753bb3594dcc9d190ef5c54071e6">S_RESET</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd1</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 920 |
12 |
alfik |
</tr>
|
| 921 |
|
|
</table>
|
| 922 |
|
|
</div>
|
| 923 |
|
|
<div class="memdoc">
|
| 924 |
|
|
|
| 925 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 926 |
12 |
alfik |
|
| 927 |
|
|
</div>
|
| 928 |
|
|
</div>
|
| 929 |
13 |
alfik |
<a class="anchor" id="a35c0778e16a225b839acc35705428b6a"></a><!-- doxytag: member="bus_control::S_BLOCKED" ref="a35c0778e16a225b839acc35705428b6a" args="5'd2" -->
|
| 930 |
12 |
alfik |
<div class="memitem">
|
| 931 |
|
|
<div class="memproto">
|
| 932 |
|
|
<table class="memname">
|
| 933 |
|
|
<tr>
|
| 934 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a35c0778e16a225b839acc35705428b6a">S_BLOCKED</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd2</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 935 |
12 |
alfik |
</tr>
|
| 936 |
|
|
</table>
|
| 937 |
|
|
</div>
|
| 938 |
|
|
<div class="memdoc">
|
| 939 |
|
|
|
| 940 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 941 |
12 |
alfik |
|
| 942 |
|
|
</div>
|
| 943 |
|
|
</div>
|
| 944 |
13 |
alfik |
<a class="anchor" id="a22028b6e9c3a87066084eeb7e3ea66dc"></a><!-- doxytag: member="bus_control::S_INT_1" ref="a22028b6e9c3a87066084eeb7e3ea66dc" args="5'd3" -->
|
| 945 |
12 |
alfik |
<div class="memitem">
|
| 946 |
|
|
<div class="memproto">
|
| 947 |
|
|
<table class="memname">
|
| 948 |
|
|
<tr>
|
| 949 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a22028b6e9c3a87066084eeb7e3ea66dc">S_INT_1</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd3</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 950 |
12 |
alfik |
</tr>
|
| 951 |
|
|
</table>
|
| 952 |
|
|
</div>
|
| 953 |
|
|
<div class="memdoc">
|
| 954 |
|
|
|
| 955 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 956 |
12 |
alfik |
|
| 957 |
|
|
</div>
|
| 958 |
|
|
</div>
|
| 959 |
13 |
alfik |
<a class="anchor" id="a0957d5175230f9062a95b56e1db2fc53"></a><!-- doxytag: member="bus_control::S_READ_1" ref="a0957d5175230f9062a95b56e1db2fc53" args="5'd4" -->
|
| 960 |
12 |
alfik |
<div class="memitem">
|
| 961 |
|
|
<div class="memproto">
|
| 962 |
|
|
<table class="memname">
|
| 963 |
|
|
<tr>
|
| 964 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a0957d5175230f9062a95b56e1db2fc53">S_READ_1</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd4</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 965 |
12 |
alfik |
</tr>
|
| 966 |
|
|
</table>
|
| 967 |
|
|
</div>
|
| 968 |
|
|
<div class="memdoc">
|
| 969 |
|
|
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a3067a17da274e211d0877d25ac1a1dec"></a><!-- doxytag: member="bus_control::S_READ_2" ref="a3067a17da274e211d0877d25ac1a1dec" args="5'd5" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a3067a17da274e211d0877d25ac1a1dec">S_READ_2</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd5</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
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12 |
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</tr>
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</table>
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<div class="memdoc">
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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12 |
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</div>
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</div>
|
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13 |
alfik |
<a class="anchor" id="ae156bee4c9bdf06b34803d8d68d9f50f"></a><!-- doxytag: member="bus_control::S_READ_3" ref="ae156bee4c9bdf06b34803d8d68d9f50f" args="5'd6" -->
|
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12 |
alfik |
<div class="memitem">
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<div class="memproto">
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<table class="memname">
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13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#ae156bee4c9bdf06b34803d8d68d9f50f">S_READ_3</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd6</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
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12 |
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</tr>
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</table>
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</div>
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<div class="memdoc">
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
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12 |
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|
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</div>
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</div>
|
| 1004 |
13 |
alfik |
<a class="anchor" id="a747a215da45fa6482e2a11f6d94c2cb8"></a><!-- doxytag: member="bus_control::S_WAIT" ref="a747a215da45fa6482e2a11f6d94c2cb8" args="5'd7" -->
|
| 1005 |
12 |
alfik |
<div class="memitem">
|
| 1006 |
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<div class="memproto">
|
| 1007 |
|
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<table class="memname">
|
| 1008 |
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<tr>
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13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a747a215da45fa6482e2a11f6d94c2cb8">S_WAIT</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd7</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1010 |
12 |
alfik |
</tr>
|
| 1011 |
|
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</table>
|
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|
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</div>
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<div class="memdoc">
|
| 1014 |
|
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| 1015 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1016 |
12 |
alfik |
|
| 1017 |
|
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</div>
|
| 1018 |
|
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</div>
|
| 1019 |
13 |
alfik |
<a class="anchor" id="a47878ecd24d5368e7396dd97ec9f4077"></a><!-- doxytag: member="bus_control::S_WRITE_1" ref="a47878ecd24d5368e7396dd97ec9f4077" args="5'd8" -->
|
| 1020 |
12 |
alfik |
<div class="memitem">
|
| 1021 |
|
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<div class="memproto">
|
| 1022 |
|
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<table class="memname">
|
| 1023 |
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<tr>
|
| 1024 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a47878ecd24d5368e7396dd97ec9f4077">S_WRITE_1</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd8</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1025 |
12 |
alfik |
</tr>
|
| 1026 |
|
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</table>
|
| 1027 |
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</div>
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<div class="memdoc">
|
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1031 |
12 |
alfik |
|
| 1032 |
|
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</div>
|
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|
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</div>
|
| 1034 |
13 |
alfik |
<a class="anchor" id="a4aaa0182c2987111710dd7a7e5f23609"></a><!-- doxytag: member="bus_control::S_WRITE_2" ref="a4aaa0182c2987111710dd7a7e5f23609" args="5'd9" -->
|
| 1035 |
12 |
alfik |
<div class="memitem">
|
| 1036 |
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<div class="memproto">
|
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|
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<table class="memname">
|
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<tr>
|
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13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a4aaa0182c2987111710dd7a7e5f23609">S_WRITE_2</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd9</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1040 |
12 |
alfik |
</tr>
|
| 1041 |
|
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</table>
|
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</div>
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<div class="memdoc">
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1046 |
12 |
alfik |
|
| 1047 |
|
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</div>
|
| 1048 |
|
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</div>
|
| 1049 |
13 |
alfik |
<a class="anchor" id="a7c1c733e80689349399716f442a5db8d"></a><!-- doxytag: member="bus_control::S_WRITE_3" ref="a7c1c733e80689349399716f442a5db8d" args="5'd10" -->
|
| 1050 |
12 |
alfik |
<div class="memitem">
|
| 1051 |
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<div class="memproto">
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<table class="memname">
|
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13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a7c1c733e80689349399716f442a5db8d">S_WRITE_3</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd10</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1055 |
12 |
alfik |
</tr>
|
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|
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</table>
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</div>
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<div class="memdoc">
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1061 |
12 |
alfik |
|
| 1062 |
|
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</div>
|
| 1063 |
|
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</div>
|
| 1064 |
13 |
alfik |
<a class="anchor" id="a058fe5f10d0f20cf2635fba74eafb30a"></a><!-- doxytag: member="bus_control::S_PC_0" ref="a058fe5f10d0f20cf2635fba74eafb30a" args="5'd11" -->
|
| 1065 |
12 |
alfik |
<div class="memitem">
|
| 1066 |
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<div class="memproto">
|
| 1067 |
|
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<table class="memname">
|
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<tr>
|
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13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a058fe5f10d0f20cf2635fba74eafb30a">S_PC_0</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd11</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1070 |
12 |
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</tr>
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| 1071 |
|
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</table>
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|
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</div>
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<div class="memdoc">
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1076 |
12 |
alfik |
|
| 1077 |
|
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</div>
|
| 1078 |
|
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</div>
|
| 1079 |
13 |
alfik |
<a class="anchor" id="a0224e82b22d3f1272d6cb604df02fd65"></a><!-- doxytag: member="bus_control::S_PC_1" ref="a0224e82b22d3f1272d6cb604df02fd65" args="5'd12" -->
|
| 1080 |
12 |
alfik |
<div class="memitem">
|
| 1081 |
|
|
<div class="memproto">
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| 1082 |
|
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<table class="memname">
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| 1084 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a0224e82b22d3f1272d6cb604df02fd65">S_PC_1</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd12</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1085 |
12 |
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</tr>
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| 1086 |
|
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</table>
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</div>
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<div class="memdoc">
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1091 |
12 |
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| 1092 |
|
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</div>
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| 1093 |
|
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</div>
|
| 1094 |
13 |
alfik |
<a class="anchor" id="a4b9998b72c69db4dcd98755835413fda"></a><!-- doxytag: member="bus_control::S_PC_2" ref="a4b9998b72c69db4dcd98755835413fda" args="5'd13" -->
|
| 1095 |
12 |
alfik |
<div class="memitem">
|
| 1096 |
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<div class="memproto">
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| 1097 |
|
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a4b9998b72c69db4dcd98755835413fda">S_PC_2</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd13</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
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</tr>
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| 1101 |
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</table>
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</div>
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<div class="memdoc">
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1106 |
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| 1107 |
|
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</div>
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| 1108 |
|
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</div>
|
| 1109 |
13 |
alfik |
<a class="anchor" id="a84be1a92cbb681a472f3e78c50d48953"></a><!-- doxytag: member="bus_control::S_PC_3" ref="a84be1a92cbb681a472f3e78c50d48953" args="5'd14" -->
|
| 1110 |
12 |
alfik |
<div class="memitem">
|
| 1111 |
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|
<div class="memproto">
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| 1112 |
|
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<table class="memname">
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13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a84be1a92cbb681a472f3e78c50d48953">S_PC_3</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd14</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
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</tr>
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| 1116 |
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</table>
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| 1117 |
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</div>
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<div class="memdoc">
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| 1119 |
|
|
|
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1121 |
12 |
alfik |
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| 1122 |
|
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</div>
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| 1123 |
|
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</div>
|
| 1124 |
13 |
alfik |
<a class="anchor" id="aec52b8e16695194dcbfefab239d8a94a"></a><!-- doxytag: member="bus_control::S_PC_4" ref="aec52b8e16695194dcbfefab239d8a94a" args="5'd15" -->
|
| 1125 |
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<div class="memitem">
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| 1126 |
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<div class="memproto">
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| 1127 |
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<table class="memname">
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| 1128 |
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#aec52b8e16695194dcbfefab239d8a94a">S_PC_4</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd15</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1130 |
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</tr>
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| 1131 |
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</table>
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| 1132 |
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</div>
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| 1133 |
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<div class="memdoc">
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| 1134 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1136 |
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| 1137 |
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</div>
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| 1138 |
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</div>
|
| 1139 |
13 |
alfik |
<a class="anchor" id="abdb432663a596db90688fa0fa9d8d603"></a><!-- doxytag: member="bus_control::S_PC_5" ref="abdb432663a596db90688fa0fa9d8d603" args="5'd16" -->
|
| 1140 |
12 |
alfik |
<div class="memitem">
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| 1141 |
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<div class="memproto">
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| 1142 |
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<table class="memname">
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| 1143 |
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alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#abdb432663a596db90688fa0fa9d8d603">S_PC_5</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd16</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
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</tr>
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| 1146 |
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</table>
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</div>
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<div class="memdoc">
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| 1149 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
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| 1152 |
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</div>
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| 1153 |
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</div>
|
| 1154 |
13 |
alfik |
<a class="anchor" id="a95ac5f10cc1642a474302d109678e2c2"></a><!-- doxytag: member="bus_control::S_PC_6" ref="a95ac5f10cc1642a474302d109678e2c2" args="5'd17" -->
|
| 1155 |
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<div class="memitem">
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| 1156 |
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<div class="memproto">
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| 1157 |
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<table class="memname">
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| 1158 |
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| 1159 |
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alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a95ac5f10cc1642a474302d109678e2c2">S_PC_6</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd17</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
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| 1161 |
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</table>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1167 |
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| 1168 |
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</div>
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| 1169 |
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alfik |
<a class="anchor" id="abc48f0e1c96b882d85f1b1033f985b61"></a><!-- doxytag: member="bus_control::FC_USER_DATA" ref="abc48f0e1c96b882d85f1b1033f985b61" args="3'd1" -->
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<div class="memitem">
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| 1171 |
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<div class="memproto">
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| 1172 |
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<table class="memname">
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| 1173 |
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#abc48f0e1c96b882d85f1b1033f985b61">FC_USER_DATA</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">3'd1</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1175 |
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</tr>
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| 1176 |
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</table>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00859">859</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1181 |
12 |
alfik |
|
| 1182 |
|
|
</div>
|
| 1183 |
|
|
</div>
|
| 1184 |
13 |
alfik |
<a class="anchor" id="af182a23ace6536ef234233549e2de05c"></a><!-- doxytag: member="bus_control::FC_USER_PROGRAM" ref="af182a23ace6536ef234233549e2de05c" args="3'd2" -->
|
| 1185 |
12 |
alfik |
<div class="memitem">
|
| 1186 |
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<div class="memproto">
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| 1187 |
|
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<table class="memname">
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| 1188 |
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<tr>
|
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13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#af182a23ace6536ef234233549e2de05c">FC_USER_PROGRAM</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">3'd2</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1190 |
12 |
alfik |
</tr>
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| 1191 |
|
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</table>
|
| 1192 |
|
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</div>
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<div class="memdoc">
|
| 1194 |
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|
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00859">859</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1196 |
12 |
alfik |
|
| 1197 |
|
|
</div>
|
| 1198 |
|
|
</div>
|
| 1199 |
13 |
alfik |
<a class="anchor" id="ae4def0ea9761559826d03589c2727513"></a><!-- doxytag: member="bus_control::FC_SUPERVISOR_DATA" ref="ae4def0ea9761559826d03589c2727513" args="3'd5" -->
|
| 1200 |
12 |
alfik |
<div class="memitem">
|
| 1201 |
|
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<div class="memproto">
|
| 1202 |
|
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<table class="memname">
|
| 1203 |
|
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<tr>
|
| 1204 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#ae4def0ea9761559826d03589c2727513">FC_SUPERVISOR_DATA</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">3'd5</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1205 |
12 |
alfik |
</tr>
|
| 1206 |
|
|
</table>
|
| 1207 |
|
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</div>
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<div class="memdoc">
|
| 1209 |
|
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|
| 1210 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00859">859</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1211 |
12 |
alfik |
|
| 1212 |
|
|
</div>
|
| 1213 |
|
|
</div>
|
| 1214 |
13 |
alfik |
<a class="anchor" id="ab1ee5e2a9796c9681a2401aaa7c623e3"></a><!-- doxytag: member="bus_control::FC_SUPERVISOR_PROGRAM" ref="ab1ee5e2a9796c9681a2401aaa7c623e3" args="3'd6" -->
|
| 1215 |
12 |
alfik |
<div class="memitem">
|
| 1216 |
|
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<div class="memproto">
|
| 1217 |
|
|
<table class="memname">
|
| 1218 |
|
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<tr>
|
| 1219 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#ab1ee5e2a9796c9681a2401aaa7c623e3">FC_SUPERVISOR_PROGRAM</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">3'd6</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1220 |
12 |
alfik |
</tr>
|
| 1221 |
|
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</table>
|
| 1222 |
|
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</div>
|
| 1223 |
|
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<div class="memdoc">
|
| 1224 |
|
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|
| 1225 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00859">859</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1226 |
12 |
alfik |
|
| 1227 |
|
|
</div>
|
| 1228 |
|
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</div>
|
| 1229 |
13 |
alfik |
<a class="anchor" id="aabcbc5528d37aad94c1c91f72abe9788"></a><!-- doxytag: member="bus_control::FC_CPU_SPACE" ref="aabcbc5528d37aad94c1c91f72abe9788" args="3'd7" -->
|
| 1230 |
12 |
alfik |
<div class="memitem">
|
| 1231 |
|
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<div class="memproto">
|
| 1232 |
|
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<table class="memname">
|
| 1233 |
|
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<tr>
|
| 1234 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#aabcbc5528d37aad94c1c91f72abe9788">FC_CPU_SPACE</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">3'd7</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1235 |
12 |
alfik |
</tr>
|
| 1236 |
|
|
</table>
|
| 1237 |
|
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</div>
|
| 1238 |
|
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<div class="memdoc">
|
| 1239 |
|
|
|
| 1240 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00859">859</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1241 |
12 |
alfik |
|
| 1242 |
|
|
</div>
|
| 1243 |
|
|
</div>
|
| 1244 |
13 |
alfik |
<a class="anchor" id="ad3b1eccec1964a8067b4d458c0735bec"></a><!-- doxytag: member="bus_control::CTI_CLASSIC_CYCLE" ref="ad3b1eccec1964a8067b4d458c0735bec" args="3'd0" -->
|
| 1245 |
12 |
alfik |
<div class="memitem">
|
| 1246 |
|
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<div class="memproto">
|
| 1247 |
|
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<table class="memname">
|
| 1248 |
|
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<tr>
|
| 1249 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#ad3b1eccec1964a8067b4d458c0735bec">CTI_CLASSIC_CYCLE</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">3'd0</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1250 |
12 |
alfik |
</tr>
|
| 1251 |
|
|
</table>
|
| 1252 |
|
|
</div>
|
| 1253 |
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<div class="memdoc">
|
| 1254 |
|
|
|
| 1255 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00866">866</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1256 |
12 |
alfik |
|
| 1257 |
|
|
</div>
|
| 1258 |
|
|
</div>
|
| 1259 |
13 |
alfik |
<a class="anchor" id="a965b59e7efe4fa822995720d75210d72"></a><!-- doxytag: member="bus_control::CTI_CONST_CYCLE" ref="a965b59e7efe4fa822995720d75210d72" args="3'd1" -->
|
| 1260 |
12 |
alfik |
<div class="memitem">
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| 1261 |
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<div class="memproto">
|
| 1262 |
|
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<table class="memname">
|
| 1263 |
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<tr>
|
| 1264 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a965b59e7efe4fa822995720d75210d72">CTI_CONST_CYCLE</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">3'd1</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1265 |
12 |
alfik |
</tr>
|
| 1266 |
|
|
</table>
|
| 1267 |
|
|
</div>
|
| 1268 |
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<div class="memdoc">
|
| 1269 |
|
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|
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13 |
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00866">866</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1271 |
12 |
alfik |
|
| 1272 |
|
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</div>
|
| 1273 |
|
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</div>
|
| 1274 |
13 |
alfik |
<a class="anchor" id="a587193dd5369e15500f18b273973e48f"></a><!-- doxytag: member="bus_control::CTI_INCR_CYCLE" ref="a587193dd5369e15500f18b273973e48f" args="3'd2" -->
|
| 1275 |
12 |
alfik |
<div class="memitem">
|
| 1276 |
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<div class="memproto">
|
| 1277 |
|
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<table class="memname">
|
| 1278 |
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<tr>
|
| 1279 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a587193dd5369e15500f18b273973e48f">CTI_INCR_CYCLE</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">3'd2</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1280 |
12 |
alfik |
</tr>
|
| 1281 |
|
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</table>
|
| 1282 |
|
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</div>
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<div class="memdoc">
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| 1284 |
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00866">866</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
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12 |
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| 1287 |
|
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</div>
|
| 1288 |
|
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</div>
|
| 1289 |
13 |
alfik |
<a class="anchor" id="a745c9ea9f195abbc1590ef5d8144d19f"></a><!-- doxytag: member="bus_control::CTI_END_OF_BURST" ref="a745c9ea9f195abbc1590ef5d8144d19f" args="3'd7" -->
|
| 1290 |
12 |
alfik |
<div class="memitem">
|
| 1291 |
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<div class="memproto">
|
| 1292 |
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<table class="memname">
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alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a745c9ea9f195abbc1590ef5d8144d19f">CTI_END_OF_BURST</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">3'd7</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1295 |
12 |
alfik |
</tr>
|
| 1296 |
|
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</table>
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| 1297 |
|
|
</div>
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<div class="memdoc">
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| 1299 |
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|
|
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00866">866</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
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12 |
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| 1302 |
|
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</div>
|
| 1303 |
|
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</div>
|
| 1304 |
13 |
alfik |
<a class="anchor" id="a554ae3cd6bed134747a67f5fd44ed40c"></a><!-- doxytag: member="bus_control::VECTOR_BUS_TRAP" ref="a554ae3cd6bed134747a67f5fd44ed40c" args="8'd2" -->
|
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12 |
alfik |
<div class="memitem">
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| 1306 |
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| 1309 |
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a554ae3cd6bed134747a67f5fd44ed40c">VECTOR_BUS_TRAP</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">7</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">8'd2</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1310 |
12 |
alfik |
</tr>
|
| 1311 |
|
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</table>
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| 1312 |
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</div>
|
| 1313 |
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<div class="memdoc">
|
| 1314 |
|
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|
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13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00872">872</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1316 |
12 |
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|
| 1317 |
|
|
</div>
|
| 1318 |
|
|
</div>
|
| 1319 |
13 |
alfik |
<a class="anchor" id="a4d7a5b1d461b7f9e41ef71fe929ebc24"></a><!-- doxytag: member="bus_control::VECTOR_ADDRESS_TRAP" ref="a4d7a5b1d461b7f9e41ef71fe929ebc24" args="8'd3" -->
|
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<div class="memitem">
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| 1321 |
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<div class="memproto">
|
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|
<table class="memname">
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13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a4d7a5b1d461b7f9e41ef71fe929ebc24">VECTOR_ADDRESS_TRAP</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">8'd3</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
|
| 1325 |
12 |
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</tr>
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| 1326 |
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</table>
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</div>
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<div class="memdoc">
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| 1329 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00872">872</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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12 |
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| 1332 |
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</div>
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| 1333 |
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</div>
|
| 1334 |
13 |
alfik |
<a class="anchor" id="a03d903903e3fd9379ec49fe4c0e91305"></a><!-- doxytag: member="bus_control::current_state" ref="a03d903903e3fd9379ec49fe4c0e91305" args="reg[4:0]" -->
|
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<div class="memitem">
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a03d903903e3fd9379ec49fe4c0e91305">current_state</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[4:0]]</code></td>
|
| 1340 |
12 |
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</tr>
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| 1341 |
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</table>
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| 1342 |
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</div>
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<div class="memdoc">
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00876">876</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
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12 |
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| 1347 |
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</div>
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| 1348 |
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</div>
|
| 1349 |
13 |
alfik |
<a class="anchor" id="abf59719bc7d27f3e4bb7e18ab9b096d5"></a><!-- doxytag: member="bus_control::reset_counter" ref="abf59719bc7d27f3e4bb7e18ab9b096d5" args="reg[7:0]" -->
|
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<div class="memitem">
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#abf59719bc7d27f3e4bb7e18ab9b096d5">reset_counter</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[7:0]]</code></td>
|
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</tr>
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| 1356 |
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</table>
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</div>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00877">877</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
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| 1363 |
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</div>
|
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13 |
alfik |
<a class="anchor" id="a883aab87490e47ed6082c6edbec30019"></a><!-- doxytag: member="bus_control::last_interrupt_mask" ref="a883aab87490e47ed6082c6edbec30019" args="reg[2:0]" -->
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<div class="memitem">
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a883aab87490e47ed6082c6edbec30019">last_interrupt_mask</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[2:0]]</code></td>
|
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</tr>
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</table>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00879">879</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a73ba36a3d5b3653f63c1dad0fc5eb9ee"></a><!-- doxytag: member="bus_control::CLK_I" ref="a73ba36a3d5b3653f63c1dad0fc5eb9ee" args="" -->
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<div class="memitem">
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a73ba36a3d5b3653f63c1dad0fc5eb9ee">CLK_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 1385 |
12 |
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</tr>
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</table>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00754">754</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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13 |
alfik |
<a class="anchor" id="a27663128a68fdb385e31a4f008cfd334"></a><!-- doxytag: member="bus_control::reset_n" ref="a27663128a68fdb385e31a4f008cfd334" args="" -->
|
| 1395 |
12 |
alfik |
<div class="memitem">
|
| 1396 |
|
|
<div class="memproto">
|
| 1397 |
|
|
<table class="memname">
|
| 1398 |
|
|
<tr>
|
| 1399 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a27663128a68fdb385e31a4f008cfd334">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 1400 |
12 |
alfik |
</tr>
|
| 1401 |
|
|
</table>
|
| 1402 |
|
|
</div>
|
| 1403 |
|
|
<div class="memdoc">
|
| 1404 |
|
|
|
| 1405 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00755">755</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1406 |
12 |
alfik |
|
| 1407 |
|
|
</div>
|
| 1408 |
|
|
</div>
|
| 1409 |
13 |
alfik |
<a class="anchor" id="ac02fc636a45f310c29ae0e3492517a52"></a><!-- doxytag: member="bus_control::CYC_O" ref="ac02fc636a45f310c29ae0e3492517a52" args="" -->
|
| 1410 |
12 |
alfik |
<div class="memitem">
|
| 1411 |
|
|
<div class="memproto">
|
| 1412 |
|
|
<table class="memname">
|
| 1413 |
|
|
<tr>
|
| 1414 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#ac02fc636a45f310c29ae0e3492517a52">CYC_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1415 |
12 |
alfik |
</tr>
|
| 1416 |
|
|
</table>
|
| 1417 |
|
|
</div>
|
| 1418 |
|
|
<div class="memdoc">
|
| 1419 |
|
|
|
| 1420 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00757">757</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1421 |
12 |
alfik |
|
| 1422 |
|
|
</div>
|
| 1423 |
|
|
</div>
|
| 1424 |
13 |
alfik |
<a class="anchor" id="aeefb698aba598e430f11def15eb7322d"></a><!-- doxytag: member="bus_control::ADR_O" ref="aeefb698aba598e430f11def15eb7322d" args="" -->
|
| 1425 |
12 |
alfik |
<div class="memitem">
|
| 1426 |
|
|
<div class="memproto">
|
| 1427 |
|
|
<table class="memname">
|
| 1428 |
|
|
<tr>
|
| 1429 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#aeefb698aba598e430f11def15eb7322d">ADR_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">2</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1430 |
12 |
alfik |
</tr>
|
| 1431 |
|
|
</table>
|
| 1432 |
|
|
</div>
|
| 1433 |
|
|
<div class="memdoc">
|
| 1434 |
|
|
|
| 1435 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00758">758</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1436 |
12 |
alfik |
|
| 1437 |
|
|
</div>
|
| 1438 |
|
|
</div>
|
| 1439 |
13 |
alfik |
<a class="anchor" id="af89b3735286037b835a636b42f3b29bb"></a><!-- doxytag: member="bus_control::DAT_O" ref="af89b3735286037b835a636b42f3b29bb" args="" -->
|
| 1440 |
12 |
alfik |
<div class="memitem">
|
| 1441 |
|
|
<div class="memproto">
|
| 1442 |
|
|
<table class="memname">
|
| 1443 |
|
|
<tr>
|
| 1444 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#af89b3735286037b835a636b42f3b29bb">DAT_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1445 |
12 |
alfik |
</tr>
|
| 1446 |
|
|
</table>
|
| 1447 |
|
|
</div>
|
| 1448 |
|
|
<div class="memdoc">
|
| 1449 |
|
|
|
| 1450 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00759">759</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1451 |
12 |
alfik |
|
| 1452 |
|
|
</div>
|
| 1453 |
|
|
</div>
|
| 1454 |
13 |
alfik |
<a class="anchor" id="a1e4db6a76c19f91d7aa404bfa83a16a5"></a><!-- doxytag: member="bus_control::DAT_I" ref="a1e4db6a76c19f91d7aa404bfa83a16a5" args="" -->
|
| 1455 |
12 |
alfik |
<div class="memitem">
|
| 1456 |
|
|
<div class="memproto">
|
| 1457 |
|
|
<table class="memname">
|
| 1458 |
|
|
<tr>
|
| 1459 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a1e4db6a76c19f91d7aa404bfa83a16a5">DAT_I</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 1460 |
12 |
alfik |
</tr>
|
| 1461 |
|
|
</table>
|
| 1462 |
|
|
</div>
|
| 1463 |
|
|
<div class="memdoc">
|
| 1464 |
|
|
|
| 1465 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00760">760</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1466 |
12 |
alfik |
|
| 1467 |
|
|
</div>
|
| 1468 |
|
|
</div>
|
| 1469 |
13 |
alfik |
<a class="anchor" id="a5155e2d5fd75ab4c30d8f3d096efdba8"></a><!-- doxytag: member="bus_control::SEL_O" ref="a5155e2d5fd75ab4c30d8f3d096efdba8" args="" -->
|
| 1470 |
12 |
alfik |
<div class="memitem">
|
| 1471 |
|
|
<div class="memproto">
|
| 1472 |
|
|
<table class="memname">
|
| 1473 |
|
|
<tr>
|
| 1474 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a5155e2d5fd75ab4c30d8f3d096efdba8">SEL_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1475 |
12 |
alfik |
</tr>
|
| 1476 |
|
|
</table>
|
| 1477 |
|
|
</div>
|
| 1478 |
|
|
<div class="memdoc">
|
| 1479 |
|
|
|
| 1480 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00761">761</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1481 |
12 |
alfik |
|
| 1482 |
|
|
</div>
|
| 1483 |
|
|
</div>
|
| 1484 |
13 |
alfik |
<a class="anchor" id="ac32a625690b5f1353f7bc2b396165c6f"></a><!-- doxytag: member="bus_control::STB_O" ref="ac32a625690b5f1353f7bc2b396165c6f" args="" -->
|
| 1485 |
12 |
alfik |
<div class="memitem">
|
| 1486 |
|
|
<div class="memproto">
|
| 1487 |
|
|
<table class="memname">
|
| 1488 |
|
|
<tr>
|
| 1489 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#ac32a625690b5f1353f7bc2b396165c6f">STB_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1490 |
12 |
alfik |
</tr>
|
| 1491 |
|
|
</table>
|
| 1492 |
|
|
</div>
|
| 1493 |
|
|
<div class="memdoc">
|
| 1494 |
|
|
|
| 1495 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00762">762</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1496 |
12 |
alfik |
|
| 1497 |
|
|
</div>
|
| 1498 |
|
|
</div>
|
| 1499 |
13 |
alfik |
<a class="anchor" id="a00bd08cfbd1319965b0595eed52b69b0"></a><!-- doxytag: member="bus_control::WE_O" ref="a00bd08cfbd1319965b0595eed52b69b0" args="" -->
|
| 1500 |
12 |
alfik |
<div class="memitem">
|
| 1501 |
|
|
<div class="memproto">
|
| 1502 |
|
|
<table class="memname">
|
| 1503 |
|
|
<tr>
|
| 1504 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a00bd08cfbd1319965b0595eed52b69b0">WE_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1505 |
12 |
alfik |
</tr>
|
| 1506 |
|
|
</table>
|
| 1507 |
|
|
</div>
|
| 1508 |
|
|
<div class="memdoc">
|
| 1509 |
|
|
|
| 1510 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00763">763</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1511 |
12 |
alfik |
|
| 1512 |
|
|
</div>
|
| 1513 |
|
|
</div>
|
| 1514 |
13 |
alfik |
<a class="anchor" id="a5d59f5931f8e2738510b3281d6b18c46"></a><!-- doxytag: member="bus_control::ACK_I" ref="a5d59f5931f8e2738510b3281d6b18c46" args="" -->
|
| 1515 |
12 |
alfik |
<div class="memitem">
|
| 1516 |
|
|
<div class="memproto">
|
| 1517 |
|
|
<table class="memname">
|
| 1518 |
|
|
<tr>
|
| 1519 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a5d59f5931f8e2738510b3281d6b18c46">ACK_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 1520 |
12 |
alfik |
</tr>
|
| 1521 |
|
|
</table>
|
| 1522 |
|
|
</div>
|
| 1523 |
|
|
<div class="memdoc">
|
| 1524 |
|
|
|
| 1525 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00765">765</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1526 |
12 |
alfik |
|
| 1527 |
|
|
</div>
|
| 1528 |
|
|
</div>
|
| 1529 |
13 |
alfik |
<a class="anchor" id="a450449748cb33c8f4a0e748326962cb7"></a><!-- doxytag: member="bus_control::ERR_I" ref="a450449748cb33c8f4a0e748326962cb7" args="" -->
|
| 1530 |
12 |
alfik |
<div class="memitem">
|
| 1531 |
|
|
<div class="memproto">
|
| 1532 |
|
|
<table class="memname">
|
| 1533 |
|
|
<tr>
|
| 1534 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a450449748cb33c8f4a0e748326962cb7">ERR_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 1535 |
12 |
alfik |
</tr>
|
| 1536 |
|
|
</table>
|
| 1537 |
|
|
</div>
|
| 1538 |
|
|
<div class="memdoc">
|
| 1539 |
|
|
|
| 1540 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00766">766</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1541 |
12 |
alfik |
|
| 1542 |
|
|
</div>
|
| 1543 |
|
|
</div>
|
| 1544 |
13 |
alfik |
<a class="anchor" id="a48f4d92b50745589e8cd4e95289ed052"></a><!-- doxytag: member="bus_control::RTY_I" ref="a48f4d92b50745589e8cd4e95289ed052" args="" -->
|
| 1545 |
12 |
alfik |
<div class="memitem">
|
| 1546 |
|
|
<div class="memproto">
|
| 1547 |
|
|
<table class="memname">
|
| 1548 |
|
|
<tr>
|
| 1549 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a48f4d92b50745589e8cd4e95289ed052">RTY_I</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
|
| 1550 |
12 |
alfik |
</tr>
|
| 1551 |
|
|
</table>
|
| 1552 |
|
|
</div>
|
| 1553 |
|
|
<div class="memdoc">
|
| 1554 |
|
|
|
| 1555 |
|
|
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00767">767</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1556 |
|
|
|
| 1557 |
|
|
</div>
|
| 1558 |
|
|
</div>
|
| 1559 |
13 |
alfik |
<a class="anchor" id="afe77400d3ddeb16113b255b6a2ff96bb"></a><!-- doxytag: member="bus_control::SGL_O" ref="afe77400d3ddeb16113b255b6a2ff96bb" args="" -->
|
| 1560 |
12 |
alfik |
<div class="memitem">
|
| 1561 |
|
|
<div class="memproto">
|
| 1562 |
|
|
<table class="memname">
|
| 1563 |
|
|
<tr>
|
| 1564 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#afe77400d3ddeb16113b255b6a2ff96bb">SGL_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1565 |
12 |
alfik |
</tr>
|
| 1566 |
|
|
</table>
|
| 1567 |
|
|
</div>
|
| 1568 |
|
|
<div class="memdoc">
|
| 1569 |
|
|
|
| 1570 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00770">770</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1571 |
12 |
alfik |
|
| 1572 |
|
|
</div>
|
| 1573 |
|
|
</div>
|
| 1574 |
13 |
alfik |
<a class="anchor" id="ae5746117903f05636c8dd5d92da8101e"></a><!-- doxytag: member="bus_control::BLK_O" ref="ae5746117903f05636c8dd5d92da8101e" args="" -->
|
| 1575 |
12 |
alfik |
<div class="memitem">
|
| 1576 |
|
|
<div class="memproto">
|
| 1577 |
|
|
<table class="memname">
|
| 1578 |
|
|
<tr>
|
| 1579 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#ae5746117903f05636c8dd5d92da8101e">BLK_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1580 |
12 |
alfik |
</tr>
|
| 1581 |
|
|
</table>
|
| 1582 |
|
|
</div>
|
| 1583 |
|
|
<div class="memdoc">
|
| 1584 |
|
|
|
| 1585 |
13 |
alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00771">771</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1586 |
12 |
alfik |
|
| 1587 |
|
|
</div>
|
| 1588 |
|
|
</div>
|
| 1589 |
13 |
alfik |
<a class="anchor" id="a71a8bcc489819f6f16cc3a8f741b9af2"></a><!-- doxytag: member="bus_control::RMW_O" ref="a71a8bcc489819f6f16cc3a8f741b9af2" args="" -->
|
| 1590 |
12 |
alfik |
<div class="memitem">
|
| 1591 |
|
|
<div class="memproto">
|
| 1592 |
|
|
<table class="memname">
|
| 1593 |
|
|
<tr>
|
| 1594 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a71a8bcc489819f6f16cc3a8f741b9af2">RMW_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1595 |
12 |
alfik |
</tr>
|
| 1596 |
|
|
</table>
|
| 1597 |
|
|
</div>
|
| 1598 |
|
|
<div class="memdoc">
|
| 1599 |
|
|
|
| 1600 |
|
|
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00772">772</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
|
| 1601 |
|
|
|
| 1602 |
|
|
</div>
|
| 1603 |
|
|
</div>
|
| 1604 |
13 |
alfik |
<a class="anchor" id="abe7853fb7148b9d4875b715d75acda8b"></a><!-- doxytag: member="bus_control::CTI_O" ref="abe7853fb7148b9d4875b715d75acda8b" args="" -->
|
| 1605 |
12 |
alfik |
<div class="memitem">
|
| 1606 |
|
|
<div class="memproto">
|
| 1607 |
|
|
<table class="memname">
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<tr>
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#abe7853fb7148b9d4875b715d75acda8b">CTI_O</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00775">775</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
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</div>
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<a class="anchor" id="ada8208aac77c8a5b2d937d050a85ded6"></a><!-- doxytag: member="bus_control::BTE_O" ref="ada8208aac77c8a5b2d937d050a85ded6" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#ada8208aac77c8a5b2d937d050a85ded6">BTE_O</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00776">776</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
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</div>
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alfik |
<a class="anchor" id="a5969bfa47db3634b63de3d21e9160305"></a><!-- doxytag: member="bus_control::fc_o" ref="a5969bfa47db3634b63de3d21e9160305" args="" -->
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alfik |
<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a5969bfa47db3634b63de3d21e9160305">fc_o</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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alfik |
</tr>
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| 1641 |
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</table>
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</div>
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<div class="memdoc">
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| 1644 |
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| 1645 |
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00779">779</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
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</div>
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alfik |
<a class="anchor" id="a1ed42a631a71210de0231c9079f52f22"></a><!-- doxytag: member="bus_control::ipl_i" ref="a1ed42a631a71210de0231c9079f52f22" args="" -->
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alfik |
<div class="memitem">
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<div class="memproto">
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<table class="memname">
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alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a1ed42a631a71210de0231c9079f52f22">ipl_i</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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| 1659 |
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alfik |
<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00782">782</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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12 |
alfik |
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| 1662 |
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</div>
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| 1663 |
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</div>
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13 |
alfik |
<a class="anchor" id="aac566bab00fcb5eb780c4cd72532ad1d"></a><!-- doxytag: member="bus_control::reset_o" ref="aac566bab00fcb5eb780c4cd72532ad1d" args="" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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| 1669 |
13 |
alfik |
<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#aac566bab00fcb5eb780c4cd72532ad1d">reset_o</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
|
| 1670 |
12 |
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00783">783</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1677 |
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</div>
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</div>
|
| 1679 |
13 |
alfik |
<a class="anchor" id="a518be1f0ea917cc51c7843115db83ce1"></a><!-- doxytag: member="bus_control::pc_i_plus_6" ref="a518be1f0ea917cc51c7843115db83ce1" args="wire[31:0]" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a518be1f0ea917cc51c7843115db83ce1">pc_i_plus_6</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00829">829</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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| 1692 |
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</div>
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</div>
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<a class="anchor" id="ad4e505c885a6c941198d653beff91bf1"></a><!-- doxytag: member="bus_control::pc_i_plus_4" ref="ad4e505c885a6c941198d653beff91bf1" args="wire[31:0]" -->
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<div class="memitem">
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<table class="memname">
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<tr>
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#ad4e505c885a6c941198d653beff91bf1">pc_i_plus_4</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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</tr>
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</table>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00831">831</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
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</div>
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<a class="anchor" id="af8d1410047baf49f9a20acaf85010d8f"></a><!-- doxytag: member="bus_control::address_i_plus_4" ref="af8d1410047baf49f9a20acaf85010d8f" args="wire[31:0]" -->
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<div class="memitem">
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<div class="memproto">
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<table class="memname">
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<tr>
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#af8d1410047baf49f9a20acaf85010d8f">address_i_plus_4</a></span> <b><span class="vhdlchar"> </span></b> <code> [wire[31:0]]</code></td>
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</tr>
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</table>
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</div>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00834">834</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
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</div>
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<a class="anchor" id="aea70fb3c869e1251bc09e527021c8f1b"></a><!-- doxytag: member="bus_control::saved_pc_change" ref="aea70fb3c869e1251bc09e527021c8f1b" args="reg[1:0]" -->
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<div class="memitem">
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<table class="memname">
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#aea70fb3c869e1251bc09e527021c8f1b">saved_pc_change</a></span> <b><span class="vhdlchar"> </span></b> <code> [reg[1:0]]</code></td>
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</tr>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00837">837</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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</div>
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</div>
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<a class="anchor" id="a2520890033d3b3447fc8bd3ac1be2987"></a><!-- doxytag: member="bus_control::S_INIT" ref="a2520890033d3b3447fc8bd3ac1be2987" args="5'd0" -->
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<div class="memitem">
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<td class="memname"><span class="stringliteral"><a class="el" href="classbus__control.html#a2520890033d3b3447fc8bd3ac1be2987">S_INIT</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">4</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdldigit">5'd0</span><span class="vhdlchar"> </span></b> <code> [Parameter]</code></td>
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</tr>
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</table>
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<div class="memdoc">
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l00839">839</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
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<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li>
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</ul>
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<hr class="footer"/><address class="footer"><small>Generated on Sat Jan 15 2011 16:45:29 for ao68000 by 
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<a href="http://www.doxygen.org/index.html">
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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</body>
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