OpenCores
URL https://opencores.org/ocsvn/ao68000/ao68000/trunk

Subversion Repositories ao68000

[/] [ao68000/] [trunk/] [doc/] [doxygen/] [html/] [page_old_notes.html] - Blame information for rev 12

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 alfik 
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
2 
<html xmlns="http://www.w3.org/1999/xhtml">
3 
<head>
4 
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
5 
<title>ao68000: Old ao68000 notes</title>
6 
<link href="tabs.css" rel="stylesheet" type="text/css"/>
7 
<link href="doxygen.css" rel="stylesheet" type="text/css"/>
8 
</head>
9 
<body>
10 
<!-- Generated by Doxygen 1.7.2 -->
11 
<div class="navigation" id="top">
12 
  <div class="tabs">
13 
    <ul class="tablist">
14 
      <li><a href="index.html"><span>Main&#160;Page</span></a></li>
15 
      <li><a href="modules.html"><span>Modules</span></a></li>
16 
      <li><a href="annotated.html"><span>Design&#160;Unit&#160;List</span></a></li>
17 
      <li><a href="files.html"><span>Files</span></a></li>
18 
    </ul>
19 
  </div>
20 
  <div class="navpath">
21 
    <ul>
22 
      <li><a class="el" href="index.html">index</a>      </li>
23 
    </ul>
24 
  </div>
25 
</div>
26 
<div class="header">
27 
  <div class="headertitle">
28 
<h1>Old <a class="el" href="classao68000.html" title="ao68000 top level module.">ao68000</a> notes </h1>  </div>
29 
</div>
30 
<div class="contents">
31 
<div class="fragment"><pre class="fragment">*******************************************************************************************************************************************
32 
NOTE: The information bellow is not current. It is here only for historical reasons.
33 
*******************************************************************************************************************************************
34 
 
35 
if( ir[15:12] == 4'b0000 &amp;&amp; ir[8] == 1'b0 &amp;&amp; ir[11:9] != 3'b100 &amp;&amp; ir[11:9] != 3'b110 &amp;&amp;
36 
    ir[15:0] != 16'b0000_000_0_00_111100 &amp;&amp; ir[15:0] != 16'b0000_000_0_01_111100 &amp;&amp;
37 
    ir[15:0] != 16'b0000_001_0_00_111100 &amp;&amp; ir[15:0] != 16'b0000_001_0_01_111100 &amp;&amp;
38 
    ir[15:0] != 16'b0000_101_0_00_111100 &amp;&amp; ir[15:0] != 16'b0000_101_0_01_111100
39 
)
40 
    ANDI,EORI,ORI,ADDI,SUBI
41 
+++
42 
    if( ir[7:6] == 2'b00 ) load ir1[7:0] to operand1[7:0]
43 
    else if( ir[7:6] == 2'b01 ) load ir1[15:0] to operand1[15:0]
44 
    else if( ir[7:6] == 2'b10 ) load { ir1, ir2 } to operand1[31:0]
45 
 
46 
    move operand1 to operand2
47 
 
48 
    operation size:
49 
    if( ir[7:6] == 2'b00 ) byte
50 
    else if( ir[7:6] == 2'b01 ) word
51 
    else if( ir[7:6] == 2'b10 ) long
52 
 
53 
    load (ea) from ir[5:0] to operand1: data alter
54 
                                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
55 
                                (xxx).W 111 000, (xxx).L 111 001
56 
 
57 
    perform ALU operation:
58 
        if( ir[11:9] == 3'b000 ) OR
59 
        else if( ir[11:9] == 3'b001 ) AND
60 
        else if( ir[11:9] == 3'b010 ) SUB
61 
        else if( ir[11:9] == 3'b011 ) ADD
62 
        else if( ir[11:9] == 3'b101 ) EOR
63 
 
64 
    update CCR:
65 
        ANDI,EORI,ORI:    X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
66 
        ADDI,SUBI: same as ADD: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared;
67 
            N set if result negative else cleared
68 
 
69 
    save result to (ea) from ir[5:0]
70 
 
71 
    update PC
72 
 
73 
if( ir[15:0] == 16'b0000_000_0_00_111100 || ir[15:0] == 16'b0000_000_0_01_111100 ||
74 
    ir[15:0] == 16'b0000_001_0_00_111100 || ir[15:0] == 16'b0000_001_0_01_111100 ||
75 
    ir[15:0] == 16'b0000_101_0_00_111100 || ir[15:0] == 16'b0000_101_0_01_111100
76 
)
77 
    ORI to CCR,ORI to SR,ANDI to CCR,ANDI to SR,EORI to CCR,EORI to SR
78 
+++
79 
    if( ir[7:6] == 2'b00 ) load ir1[7:0] to operand1[7:0]
80 
    else if( ir[7:6] == 2'b01 ) load ir1[15:0] to operand1[15:0]
81 
    else if( ir[7:6] == 2'b10 ) load { ir1, ir2 } to operand1[31:0]
82 
 
83 
    move operand1 to operand2
84 
 
85 
    operation size:
86 
    if( ir[7:6] == 2'b00 ) byte
87 
    else if( ir[7:6] == 2'b01 ) word
88 
    else if( ir[7:6] == 2'b10 ) long
89 
 
90 
    move SR to operand1
91 
 
92 
    perform ALU operation:
93 
        if( ir[11:9] == 3'b000 ) OR
94 
        else if( ir[11:9] == 3'b001 ) AND
95 
        else if( ir[11:9] == 3'b101 ) EOR
96 
 
97 
    move result to operand1
98 
 
99 
    save operand1 to CCR/SR
100 
 
101 
    update CCR:
102 
        result
103 
 
104 
    update PC
105 
 
106 
if( ir[15:12] == 4'b0000 &amp;&amp; ir[8] == 1'b0 &amp;&amp; ir[11:9] = 3'b110 )
107 
    CMPI
108 
+++
109 
    if( ir[7:6] == 2'b00 ) load ir1[7:0] to operand2[7:0]
110 
    else if( ir[7:6] == 2'b01 ) load ir1[15:0] to operand2[15:0]
111 
    else if( ir[7:6] == 2'b10 ) load { ir1, ir2 } to operand2[31:0]
112 
 
113 
    operation size:
114 
    if( ir[7:6] == 2'b00 ) byte
115 
    else if( ir[7:6] == 2'b01 ) word
116 
    else if( ir[7:6] == 2'b10 ) long
117 
 
118 
    load (ea) from ir[5:0] to operand1: data alter
119 
                                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
120 
                                (xxx).W 111 000, (xxx).L 111 001
121 
 
122 
    perform ALU operation:
123 
        if( ir[11:9] == 3'b110 ) CMP=SUB
124 
 
125 
    update CCR:
126 
        CMPI: same as CMP: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared;
127 
            N set if negative else cleared
128 
 
129 
    update PC
130 
 
131 
if( ir[15:12] == 4'b0000 &amp;&amp; ir[11:8] == 4'b1000 &amp;&amp; ir[7:6] != 2'b00 )
132 
    BCHG,BCLR,BSET immediate
133 
+++
134 
    load ir1[7:0] to operand1[7:0]
135 
 
136 
    move operand1 to operand2
137 
 
138 
    load (ea) form ir[5:0] to operand1: data alter
139 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
140 
                                (xxx).W 111 000, (xxx).L 111 001
141 
 
142 
    operation size:
143 
    if( ir[5:3] == 3'b000 ) long
144 
    else if( ir[5:3] != 3'b000 ) byte
145 
 
146 
    perform bit operation:
147 
    test( &lt;number&gt; of Destination ) -&gt; Z; test( &lt;number&gt; of Destination )[0][1] -&gt; &lt;bit number&gt; of Destination
148 
    if( ir[7:6] == 2'b01 ) BCHG
149 
    else if( ir[7:6] == 2'b10 ) BCLR
150 
    else if( ir[7:6] == 2'b11 ) BSET
151 
 
152 
    update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared
153 
 
154 
    save result to (ea) form ir[5:0]
155 
 
156 
    update PC
157 
 
158 
if( ir[15:12] == 4'b0000 &amp;&amp; ir[11:8] == 4'b1000 &amp;&amp; ir[7:6] == 2'b00 )
159 
    BTST immediate
160 
+++
161 
    load ir1[7:0] to operand1[7:0]
162 
 
163 
    move operand1 to operand2
164 
 
165 
    load (ea) form ir[5:0] to operand1: data address
166 
        data address:            Dn 000,                    (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
167 
                                (xxx).W 111 000, (xxx).L 111 001,                (d16, PC) 111 010, (d8, PC, Xn) 111 011
168 
 
169 
    operation size:
170 
    if( ir[5:3] == 3'b000 ) long
171 
    else if( ir[5:3] != 3'b000 ) byte
172 
 
173 
    perform bit operation:
174 
    test( &lt;number&gt; of Destination ) -&gt; Z
175 
    if( ir[7:6] == 2'b00 ) BTST
176 
 
177 
    update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared
178 
 
179 
    update PC
180 
 
181 
if( ir[15:12] == 4'b0000 &amp;&amp; ir[8] == 1'b1 &amp;&amp; ir[5:3] != 3'b001 &amp;&amp; ir[8:6] != 3'b100 )
182 
    BCHG,BCLR,BSET register
183 
+++
184 
    load (ea) from ir[11:9] to operand1[7:0]: Dn
185 
 
186 
    move operand1 to operand2
187 
 
188 
    load (ea) form ir[5:0] to operand1: data alter
189 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
190 
                                (xxx).W 111 000, (xxx).L 111 001
191 
 
192 
    operation size:
193 
    if( ir[5:3] == 3'b000 ) long
194 
    else if( ir[5:3] != 3'b000 ) byte
195 
 
196 
    perform bit operation:
197 
    test( &lt;number&gt; of Destination ) -&gt; Z; test( &lt;number&gt; of Destination )[0][1] -&gt; &lt;bit number&gt; of Destination
198 
    if( ir[7:6] == 2'b01 ) BCHG
199 
    else if( ir[7:6] == 2'b10 ) BCLR
200 
    else if( ir[7:6] == 2'b11 ) BSET
201 
 
202 
    update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared
203 
 
204 
    save result to (ea) form ir[5:0]
205 
 
206 
    update PC
207 
 
208 
if( ir[15:12] == 4'b0000 &amp;&amp; ir[8] == 1'b1 &amp;&amp; ir[5:3] != 3'b001 &amp;&amp; ir[8:6] == 3'b100 )
209 
    BTST register
210 
+++
211 
    load (ea) from ir[11:9] to operand1[7:0]: Dn
212 
 
213 
    move operand1 to operand2
214 
 
215 
    load (ea) form ir[5:0] to operand1: data address
216 
        data address:            Dn 000,                    (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
217 
                                (xxx).W 111 000, (xxx).L 111 001,                (d16, PC) 111 010, (d8, PC, Xn) 111 011
218 
 
219 
    operation size:
220 
    if( ir[5:3] == 3'b000 ) long
221 
    else if( ir[5:3] != 3'b000 ) byte
222 
 
223 
    perform bit operation:
224 
    test( &lt;number&gt; of Destination ) -&gt; Z
225 
    if( ir[7:6] == 2'b00 ) BTST
226 
 
227 
    update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared
228 
 
229 
    update PC
230 
 
231 
if( ir[15:12] == 4'b0000 &amp;&amp; ir[8] == 1'b1 &amp;&amp; ir[5:3] == 3'b001 &amp;&amp; ( ir[7:6] == 2'b00 || ir[7:6] == 2'b01 ) )
232 
    MOVEP memory to register
233 
+++
234 
    operation size:
235 
    if( ir[7:6] == 2'b00 ) word
236 
    if( ir[7:6] == 2'b01 ) long
237 
 
238 
    load ea from ir[2:0] to address register: (d16, An)
239 
 
240 
    do
241 
        load from (address) to operand1 register, long
242 
        move two alternate bytes to result register
243 
        increment ea by 4
244 
    repeat for long
245 
 
246 
    save result to (ea) from ir[11:9]: Dn, word ( ir[7:6] == 2'b00 ), long ( ir[7:6] == 2'b01 )
247 
 
248 
    update CCR: no change
249 
    update PC
250 
 
251 
if( ir[15:12] == 4'b0000 &amp;&amp; ir[8] == 1'b1 &amp;&amp; ir[5:3] == 3'b001 &amp;&amp; ( ir[7:6] == 2'b10 || ir[7:6] == 2'b11 ) )
252 
    MOVEP register to memory
253 
+++
254 
    operation size:
255 
    if( ir[7:6] == 2'b10 ) word
256 
    if( ir[7:6] == 2'b11 ) long
257 
 
258 
    load (ea) from ir[11:9] to operand1: Dn, long
259 
 
260 
    load ea from ir[2:0] to address register: (d16, An)
261 
 
262 
    do
263 
        move two alternate bytes to result register
264 
        save result register to (addreess), long, only selected bytes
265 
        increment ea by 4
266 
    repeat for long
267 
 
268 
    update CCR: no change
269 
    update PC
270 
 
271 
if( ir[15:14] == 2'b00 &amp;&amp; ir[13:12] != 2'b00 &amp;&amp; ir[8:6] != 3'b001)
272 
    MOVE
273 
+++
274 
    size of operation: ir[13:12]: 01,11,10 byte,word,long
275 
 
276 
    load (ea) from ir[5:0] to operand1: all modes.
277 
        all modes:                Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
278 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
279 
 
280 
    copy operand1 to result register
281 
 
282 
    save result to (ea) from ir[11:6]: data alter.
283 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
284 
                                (xxx).W 111 000, (xxx).L 111 001,
285 
 
286 
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
287 
 
288 
    update PC
289 
 
290 
if( ir[15:14] == 2'b00 &amp;&amp; (ir[13:12] == 2'b11 || ir[13:12] == 2'b10) &amp;&amp; ir[8:6] == 3'b001)
291 
    MOVEA
292 
+++
293 
    size of operation: ir[13:12]: 11,10 word,long
294 
 
295 
    load (ea) from ir[5:0] to operand1: all modes.
296 
        all modes:                Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
297 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
298 
 
299 
    copy operand1 to result register
300 
 
301 
    save result to (ea) from ir[11:6]: An
302 
 
303 
    CC: not affected
304 
 
305 
    update PC
306 
 
307 
if( ir[15:12] == 4'b1100 &amp;&amp; (ir[8:4] == 5'b10100 || 5'b11000) )
308 
    EXG
309 
+++
310 
    load (ea) from ir[5:0] to operand1: Dn, An
311 
 
312 
    perform ALU operation: move operand1 to result register
313 
 
314 
    load (ea) from ir[11:9] with mode in ir[7:3] to operand1: Dn (5'b01000 or 5'b10001), An (5'b01001)
315 
 
316 
    save result to (ea) from ir[11:9] with mode in ir[7:3]: Dn (5'b01000 or 5'b10001), An (5'b01001),
317 
 
318 
    perform ALU operation: move operand1 to result register
319 
 
320 
    save result to (ea) from ir[5:0]: Dn, An
321 
 
322 
    CC: not affected
323 
 
324 
    update PC
325 
 
326 
if( ir[15:12] == 4'b1011 &amp;&amp; (ir[8:6] == 3'b100 || 3'b101 || 3'b110) &amp;&amp; ir[5:3] == 3'b001 )
327 
    CMPM
328 
+++
329 
    load (ea) from ir[2:0] to operand1: postincrement (An)+
330 
 
331 
    move operand1 to operand2
332 
 
333 
    load (ea) from ir[11:9] to operand1: postincrement (An)+
334 
 
335 
    ALU operation size:
336 
    if( ir[7:6] == 2'b00 ) byte
337 
    else if( ir[7:6] == 2'b01 ) word
338 
    else if( ir[7:6] == 2'b10 ) long
339 
 
340 
    perform ALU operation: CMPM == SUB
341 
 
342 
    CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared
343 
    Ax dest, Ay source: postincrement: +(An)
344 
 
345 
    update PC
346 
 
347 
if( ir[15:12] == 4'b1011 &amp;&amp; (ir[8:6] == 3'b100 || 3'b101 || 3'b110) &amp;&amp; ir[5:3] != 3'b001 )
348 
    EOR
349 
+++
350 
    load (ea) from ir[11:9] to operand1: Dn
351 
 
352 
    move operand1 to operand2
353 
 
354 
    load (ea) from ir[5:0] to operand1: data alter
355 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
356 
                                (xxx).W 111 000, (xxx).L 111 001,
357 
 
358 
    ALU operation size:
359 
    if( ir[7:6] == 2'b00 ) byte
360 
    else if( ir[7:6] == 2'b01 ) word
361 
    else if( ir[7:6] == 2'b10 ) long
362 
 
363 
    perform ALU operation: EOR
364 
 
365 
    CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
366 
 
367 
    save result to (ea) from ir[5:0]: data alter
368 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
369 
                                (xxx).W 111 000, (xxx).L 111 001,
370 
    update PC
371 
 
372 
if( (ir[15:12] == 4'b1101 || 4'b1001 || 4'b1100 || 4'b1000) &amp;&amp;
373 
    (ir[8:4] == 5'b10001 || 5'b10010 || 5'b10011 || 5'b10101 || 5'b10110 || 5'b10111 || 5'b11001 || 5'b11010 || 5'b11011) )
374 
 
375 
    ADD to mem,SUB to mem,AND to mem,OR to mem
376 
+++
377 
    load (ea) from ir[11:9] to operand1: Dn
378 
 
379 
    move operand1 to operand2
380 
 
381 
    load (ea) indexed by ir[5:0] to operand1: memory alter
382 
        memory alter:                                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
383 
                                (xxx).W 111 000, (xxx).L 111 001
384 
 
385 
    ALU operation size:
386 
    if( ir[7:6] == 2'b00 ) byte
387 
    else if( ir[7:6] == 2'b01 ) word
388 
    else if( ir[7:6] == 2'b10 ) long
389 
 
390 
    perform ALU operation:
391 
    if( ir[15:12] == 4'b1101 ) ADD
392 
    else if( ir[15:12] == 4'b1001 ) SUB
393 
    else if( ir[15:12] == 4'b1100 ) AND
394 
    else if( ir[15:12] == 4'b1000 ) OR
395 
 
396 
    if( ADD,SUB )
397 
        CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared;
398 
            N set if result negative else cleared
399 
    else if( AND,OR )
400 
        CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
401 
 
402 
    save result to (ea) from ir[5:0]: memory alter
403 
        memory alter:                                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
404 
                                (xxx).W 111 000, (xxx).L 111 001
405 
 
406 
    update PC
407 
 
408 
if( (ir[15:12] == 4'b1101 || 4'b1001 || 4'b1100 || 4'b1000) &amp;&amp; (ir[8:6] == 3'b000 || 3'b001 || 3'b010) )
409 
    ADD to Dn,SUB to Dn,AND to Dn,OR to Dn
410 
+++
411 
    load (ea) from ir[5:0] to operand1: all modes
412 
        all modes:                 Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
413 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
414 
 
415 
    move operand1 to operand2
416 
 
417 
    load (ea) from ir[11:9] to operand1: Dn
418 
 
419 
    ALU operation size:
420 
    if( ir[7:6] == 2'b00 ) byte
421 
    else if( ir[7:6] == 2'b01 ) word
422 
    else if( ir[7:6] == 2'b10 ) long
423 
 
424 
    perform ALU operation:
425 
    if( ir[15:12] == 4'b1101 ) ADD
426 
    else if( ir[15:12] == 4'b1001 ) SUB
427 
    else if( ir[15:12] == 4'b1100 ) AND
428 
    else if( ir[15:12] == 4'b1000 ) OR
429 
 
430 
    if( ADD,SUB )
431 
        CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared;
432 
            N set if result negative else cleared
433 
    else if( AND,OR )
434 
        CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
435 
 
436 
    save result to (ea) from ir[11:9]: Dn
437 
 
438 
    update PC
439 
 
440 
if( (ir[15:12] == 4'b1011) &amp;&amp; (ir[8:6] == 3'b000 || 3'b001 || 3'b010) )
441 
    CMP
442 
+++
443 
    load (ea) from ir[5:0] to operand1: all modes
444 
        all modes:                 Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
445 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
446 
 
447 
    move operand1 to operand2
448 
 
449 
    load (ea) from ir[11:9] to operand1: Dn
450 
 
451 
    ALU operation size:
452 
    if( ir[7:6] == 2'b00 ) byte
453 
    else if( ir[7:6] == 2'b01 ) word
454 
    else if( ir[7:6] == 2'b10 ) long
455 
 
456 
    perform ALU operation:
457 
    if( ir[15:12] == 4'b1011 ) CMP=SUB
458 
 
459 
    CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared
460 
 
461 
    update PC
462 
 
463 
if( (ir[15:12] == 4'b1100 || 4'b1000) &amp;&amp; ir[7:6] == 2'b11 )
464 
    MULS,MULU,DIVS,DIVU
465 
+++
466 
    load (ea) from ir[5:0] to operand1: data
467 
            data:        Dn 000,                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
468 
                        (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
469 
 
470 
    move operand1 to operand2
471 
 
472 
    load (ea) from ir[11:9] to operand1: Dn
473 
 
474 
    perform ALU operation:
475 
    if( ir[15:12] == 4'b1100 &amp;&amp; ir[8] == 1'b0 ) MULU
476 
    else if( ir[15:12] == 4'b1100 &amp;&amp; ir[8] == 1'b1 ) MULS
477 
    else if( ir[15:12] == 4'b1000 &amp;&amp; ir[8] == 1'b0 ) DIVU
478 
    else if( ir[15:12] == 4'b1000 &amp;&amp; ir[8] == 1'b1 ) DIVS
479 
 
480 
    if( MULU/MULS )
481 
        CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
482 
    else if( DIVU/DIVS )
483 
        CC: X not affected; C cleared; V set if overflow else if trap undefined else cleared;
484 
            Z set if quotient zero else if trap or overflow undefined else cleared;
485 
            N set if quotient negative else if trap or overflow undefined else cleared;
486 
 
487 
    save result to (ea) from ir[11:9]: Dn
488 
 
489 
    update PC
490 
 
491 
if( (ir[15:12] == 4'b1101 || 4'b1001) &amp;&amp; (ir[8:6] == 3'b011 || 3'b111) )
492 
    ADDA,SUBA
493 
+++
494 
    load (ea) from ir[5:0] to operand1: all modes
495 
        all modes:                Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
496 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
497 
 
498 
    move operand1 to operand2
499 
 
500 
    load (ea) from ir[11:9] to operand1: An
501 
 
502 
    ALU operation size, source is sign-extended:
503 
    if( ir[8] == 1'b0 ) word
504 
    else if( ir[8] == 1'b1 ) long
505 
 
506 
    perform ALU operation:
507 
    if( ir[14:12] == 3'b101 ) ADD
508 
    else if( ir[14:12] == 3'b001 ) SUB
509 
 
510 
    CC: not affected
511 
 
512 
    save result sign-extended to (ea) from ir[11:9]: An
513 
 
514 
    update PC
515 
 
516 
if( (ir[15:12] == 4'b1011) &amp;&amp; (ir[8:6] == 3'b011 || 3'b111) )
517 
    CMPA
518 
+++
519 
    load (ea) from ir[5:0] to operand1: all modes
520 
        all modes:                Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
521 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
522 
 
523 
    move operand1 to operand2
524 
 
525 
    load (ea) from ir[11:9] to operand1: An
526 
 
527 
    ALU operation size, source is sign-extended:
528 
    if( ir[8] == 1'b0 ) word
529 
    else if( ir[8] == 1'b1 ) long
530 
 
531 
    perform ALU operation:
532 
    if( ir[14:12] == 3'b011 ) CMP==SUB
533 
 
534 
    CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared
535 
 
536 
    update PC
537 
 
538 
if( ((ir[15:12] == 4'b1100 || 4'b1000) &amp;&amp; ir[8:4] == 5'b10000) || ((if[15:12] == 4'b1101 || 4'b1001) &amp;&amp; (ir[8:4] == 5'b10000 || 5'b10100 || 5'b11000) )
539 
    ABCD,SBCD,ADDX,SUBX
540 
+++
541 
    load (ea) from ir[2:0] to operand1: Dn (ir[3] == 1'b0), -(An) (ir[3] == 1'b1)
542 
 
543 
    move operand1 to operand2
544 
 
545 
    load (ea) from ir[11:9] to operand1: Dn (ir[3] == 1'b0), -(An) (ir[3] == 1'b1)
546 
 
547 
 
548 
    ALU operation size:
549 
    if( ir[7:6] == 2'b00 ) byte
550 
    else if( ir[7:6] == 2'b01 ) word
551 
    else if( ir[7:6] == 2'b10 ) long
552 
 
553 
    perform ALU operation:
554 
    if( ir[14:12] == 3'b100 ) ABCD
555 
    else if( ir[14:12] == 3'b000 ) SBCD
556 
    else if( ir[14:12] == 3'b101 ) ADDX
557 
    else if( ir[14:12] == 3'b001 ) SUBX
558 
 
559 
    if( ir[12] == 1'b0 /ABCD,SBCD/ )
560 
        CC: X=C set if decimal carry [borrow] else cleared; Z cleared if result nonzero else unchanged; N,V undefined
561 
    else
562 
        CC: X=C set if carry[borrow] else cleared; V set if overflow else cleared; Z cleared if nonzero else unchanged; N set if negative else cleared
563 
 
564 
    save result to (ea) from ir[11:9]: Dn (ir[3] == 1'b0), -(An) (ir[3] == 1'b1)
565 
 
566 
    update PC
567 
 
568 
if( ir[15:12] == 4'b1110 &amp;&amp; ir[7:6] == 2'b11 &amp;&amp; ir[11] == 1'b0 )
569 
    ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all memory
570 
+++
571 
    load (ea) from ir[5:0] to operand1: memory alter
572 
        memory alter:                                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
573 
                                (xxx).W 111 000, (xxx).L 111 001
574 
    load 1'b1 to operand2
575 
 
576 
    ALU operation size: word
577 
 
578 
    ALU shift/rotate direction:
579 
    if( ir[8] == 1'b0 ) right
580 
    else if( ir[8] == 1'b1 ) left
581 
 
582 
    perform ALU operation:
583 
    if( ir[10:9] == 2'b00 ) ASL/ASR
584 
    else if( ir[10:9] == 2'b01 ) LSL,LSR
585 
    else if( ir[10:9] == 2'b11 ) ROL,ROR
586 
    else if( ir[10:9] == 2'b10 ) ROXL,ROXR
587 
 
588 
    CC: X set to last bit, unchanged if zero shift[same][not affected][same set]; N set if MSB bit is set else cleared; Z set if zero else cleared;
589 
        V set if MSB bit changed during shift else cleared[cleared][cleared][cleared]; C set to last bit, cleared if zero shift[same][same][set to X]
590 
 
591 
    save result to (ea) from ir[5:0]: memory alter
592 
        memory alter:                                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
593 
                                (xxx).W 111 000, (xxx).L 111 001
594 
    update PC
595 
 
596 
if( ir[15:12] == 4'b1110 &amp;&amp; (ir[7:6] == 2'b00 || 2'b01 || 2'b10) )
597 
    ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all immediate/register
598 
+++
599 
    load (ea) from ir[11:9] to operand1: Dn
600 
 
601 
    move operand1 to operand2
602 
 
603 
    load (ea) from ir[2:0] to operand1: Dn
604 
 
605 
    if( ir[5] == 1'b0 )
606 
        if( ir[11:9] == 3'b000 ) load 4'b1000 to operand2
607 
        else load ir[11:9] to operand2
608 
    else if( ir[5] == 1'b1 )
609 
        perform operand2 modulo 64
610 
 
611 
    ALU operation size:
612 
    if( ir[7:6] == 2'b00 ) byte
613 
    else if( ir[7:6] == 2'b01 ) word
614 
    else if( ir[7:6] == 2'b10 ) long
615 
 
616 
    ALU shift/rotate direction:
617 
    if( ir[8] == 1'b0 ) right
618 
    else if( ir[8] == 1'b1 ) left
619 
 
620 
    perform ALU operation:
621 
    if( ir[4:3] == 2'b00 ) ASL/ASR
622 
    else if( ir[4:3] == 2'b01 ) LSL,LSR
623 
    else if( ir[4:3] == 2'b11 ) ROL,ROR
624 
    else if( ir[4:3] == 2'b10 ) ROXL,ROXR
625 
 
626 
    CC: X set to last bit, unchanged if zero shift[same][not affected][same set]; N set if MSB bit is set else cleared; Z set if zero else cleared;
627 
        V set if MSB bit changed during shift else cleared[cleared][cleared][cleared]; C set to last bit, cleared if zero shift[same][same][set to X]
628 
 
629 
    save result to (ea) from ir[2:0]: Dn
630 
 
631 
    update PC
632 
 
633 
if( ir[15:12] == 4'b0111 &amp;&amp; ir[8] == 1'b0 )
634 
    MOVEQ
635 
+++
636 
    load ir[7:0] sign-extended to result register
637 
 
638 
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
639 
 
640 
    save result to (ea) from ir[11:9]: Dn
641 
 
642 
    update PC
643 
 
644 
if( ir[15:12] == 4'b0110 &amp;&amp; ir[11:8] == 4'b0001 )
645 
    BSR
646 
+++
647 
    CC: not affected
648 
 
649 
    SP -= 4
650 
 
651 
    move PC to operand1
652 
    move operand1 to result
653 
 
654 
    save result to (ea): (SP)
655 
 
656 
    if( ir[7:0] == 8'b0 )
657 
        add to PC: ir1[15:0]
658 
    else
659 
        add to PC: ir[7:0]
660 
 
661 
    return
662 
 
663 
if( ir[15:12] == 4'b0110 &amp;&amp; ir[11:8] != 4'b0001 )
664 
    Bcc,BRA
665 
+++
666 
    condition:                               high(!C &amp; !Z) 0010, low or same(C | V) 0011,
667 
                carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111,
668 
                overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011,
669 
                greater or equal(N &amp; V | !N &amp; !V) 1100, less than(N &amp; !V | !N &amp; V) 1101,
670 
                greater than(N &amp; V &amp; !Z | !N &amp; !V &amp; !Z) 1110, less or equal(Z | N &amp; !V | !N &amp; V) 1111
671 
 
672 
    CC: not affected
673 
 
674 
    if( contidtion on ir[11:8] true )
675 
        if( ir[7:0] == 8'b0 )
676 
            add to PC: ir1[15:0]
677 
        else
678 
            add to PC: ir[7:0]
679 
 
680 
        return
681 
 
682 
    update PC
683 
 
684 
if( ir[15:12] == 4'b0101 &amp;&amp; ir[7:6] == 2'b11 &amp;&amp; ir[5:3] != 2'b001 )
685 
    Scc
686 
+++
687 
    condition:    true(1) 0000, false(0) 0001, high(!C &amp; !Z) 0010, low or same(C | V) 0011,
688 
                carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111,
689 
                overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011,
690 
                greater or equal(N &amp; V | !N &amp; !V) 1100, less than(N &amp; !V | !N &amp; V),
691 
                greater than(N &amp; V &amp; !Z | !N &amp; !V &amp; !Z), less or equal(Z | N &amp; !V | !N &amp; V) 1111
692 
 
693 
    if( contidtion on ir[11:8] false )
694 
        load 8'b00000000 to result
695 
    else
696 
        load 8'b11111111 to result
697 
 
698 
    operation size: byte
699 
 
700 
    save result to (ea) from ir[5:0]: data alter.
701 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
702 
                                (xxx).W 111 000, (xxx).L 111 001,
703 
    CC: not affected
704 
 
705 
    update PC
706 
 
707 
if( ir[15:12] == 4'b0101 &amp;&amp; ir[7:6] == 2'b11 &amp;&amp; ir[5:3] == 2'b001 )
708 
    DBcc
709 
+++
710 
    condition:    true(1) 0000, false(0) 0001, high(!C &amp; !Z) 0010, low or same(C | V) 0011,
711 
                carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111,
712 
                overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011,
713 
                greater or equal(N &amp; V | !N &amp; !V) 1100, less than(N &amp; !V | !N &amp; V),
714 
                greater than(N &amp; V &amp; !Z | !N &amp; !V &amp; !Z), less or equal(Z | N &amp; !V | !N &amp; V) 1111
715 
 
716 
    CC: not affected
717 
 
718 
    if( condition on ir[11:8] false )
719 
        load (ea) from ir[2:0] to operand1: Dn
720 
 
721 
        load 1'b1 to operand2
722 
 
723 
        ALU operation size: word
724 
 
725 
        perform ALU operation: SUB
726 
 
727 
        save result to (ea) from ir[2:0]: Dn
728 
 
729 
        if( result != -1 )
730 
            add to PC: ir1[15:0]
731 
            return
732 
 
733 
    update PC
734 
 
735 
if( ir[15:12] == 4'b0101 &amp;&amp; ir[7:6] != 2'b11 &amp;&amp; ir[5:3] != 3'b001 )
736 
    ADDQ,SUBQ not An
737 
+++
738 
    if( ir[11:9] == 3'b000 )
739 
        load 4'b1000 to operand2
740 
    else
741 
        load ir[11:9] to operand2
742 
 
743 
    load (ea) from by ir[5:0] to operand1: data alter
744 
        data alter:                Dn 000,         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
745 
                                (xxx).W 111 000, (xxx).L 111 001,
746 
 
747 
    ALU operation size:
748 
    if( ir[7:6] == 2'b10 ) long
749 
    else if( ir[7:6] == 2'b01 ) word
750 
    else if( ir[7:6] == 2'b00 ) byte
751 
 
752 
    perform ALU operation:
753 
    if( ir[8] == 1'b0 ) ADDQ
754 
    else if( ir[8] == 1'b1 ) SUBQ
755 
 
756 
    CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared;
757 
        N set if result negative else cleared
758 
 
759 
    save result to (ea) from ir[5:0]
760 
 
761 
    update PC
762 
 
763 
if( ir[15:12] == 4'b0101 &amp;&amp; ir[7:6] != 2'b11 &amp;&amp; ir[5:3] == 3'b001)
764 
    ADDQ,SUBQ An
765 
+++
766 
    if( ir[11:9] == 3'b000 )
767 
        load 4'b1000 to operand2
768 
    else
769 
        load ir[11:9] to operand2
770 
 
771 
    load (ea) from by ir[2:0] to operand1: An
772 
 
773 
    ALU operation size: long
774 
 
775 
    perform ALU operation:
776 
    if( ir[8] == 1'b0 ) ADD
777 
    else if( ir[8] == 1'b1 ) SUB
778 
 
779 
    CC: not affected
780 
 
781 
    save result to (ea) from ir[2:0]: An
782 
 
783 
    update PC
784 
 
785 
if( ir[15:0] == 16'b0100 1110 0111 0001 )
786 
    NOP
787 
+++
788 
    CC: not affected
789 
 
790 
    update PC
791 
 
792 
if( ir[15:0] == 16'b0100 1110 0111 0000 )
793 
    RESET
794 
+++
795 
    hold REST output for 124 clock cycles
796 
 
797 
    CC: not affected
798 
 
799 
    update PC
800 
 
801 
if( ir[15:0] == 16'b0100 1110 0111 0010 )
802 
    STOP
803 
+++
804 
    copy ir1[15:0] to SR
805 
 
806 
    Resume when trace, interrupt or rest.
807 
 
808 
if( ir[15:5] == 12'b0100 1110 0100 )
809 
    TRAP
810 
+++
811 
    TRAP with vector indexed by ir[3:0]
812 
 
813 
    CC: not affected
814 
 
815 
if( ir[15:0] == 16'b0100 1110 0111 0110 )
816 
    TRAPV
817 
+++
818 
    if( V ) TRAP
819 
 
820 
    CC: not affected
821 
 
822 
    update PC
823 
 
824 
if( ir[15:0] == 16'b0100 1110 0111 0011 || ir[15:0] == 16'b0100 1110 0111 0111 )
825 
    RTE,RTR
826 
+++
827 
    load (ea) to operand1: (SP)
828 
 
829 
    perform ALU operation:
830 
    if(ir[2] == 1'b0) move operand1 to SR
831 
    else if(ir[2] == 1'b1) move operand1 to CCR
832 
 
833 
    SP += 2
834 
 
835 
    load (ea) to operand1: (SP)
836 
    move operand1 to result
837 
    move result to PC
838 
 
839 
    SP += 4
840 
 
841 
if( ir[15:0] == 16'b0100 1110 0111 0101 )
842 
    RTS
843 
+++
844 
    load (ea) to operand1: (SP)
845 
    move operand1 to result
846 
    move result to PC
847 
 
848 
    SP += 4
849 
 
850 
if( ir[15:6] == 10'b0100 1110 11 )
851 
    JMP
852 
+++
853 
    load (ea) from ir[5:0] to operand1: control
854 
        control:                                         (An) 010,                       (d16, An) 101, (d8, An, Xn) 110,
855 
                                (xxx).W 111 000, (xxx).L 111 001,         (d16, PC) 111 010, (d8, PC, Xn) 111 011
856 
 
857 
    perform ALU operation: move operand1 to result
858 
 
859 
    copy result register to PC
860 
 
861 
    CC: not affected
862 
 
863 
if( ir[15:6] == 10'b0100 1110 10 )
864 
    JSR
865 
+++
866 
    SP -= 4
867 
 
868 
    move PC to operand1
869 
    move operand1 to result
870 
    save result to (ea): (SP)
871 
 
872 
    load (ea) from ir[5:0] to operand1: control
873 
        control:                                         (An) 010,                       (d16, An) 101, (d8, An, Xn) 110,
874 
                                (xxx).W 111 000, (xxx).L 111 001,         (d16, PC) 111 010, (d8, PC, Xn) 111 011
875 
 
876 
    perform ALU operation: move operand1 to result
877 
 
878 
    copy result register to PC
879 
 
880 
    CC: not affected
881 
 
882 
if( ir[15:3] == 13'b0100 1110 0101 0 )
883 
    LINK
884 
+++
885 
    SP -= 4
886 
 
887 
    load (ea) from ir[2:0] to operand1: An
888 
 
889 
    perform ALU operation: move operand1 to result
890 
 
891 
    save result to (ea): (SP)
892 
 
893 
    load (ea) to operand1: SP
894 
    move operand1 to result
895 
 
896 
    save result to (ea) from ir[2:0]: An
897 
 
898 
    add to SP: ir1[15:0]
899 
 
900 
    CC: not affected
901 
 
902 
    update PC
903 
 
904 
if( ir[15:3] == 13'b0100 1110 0101 1 )
905 
    ULNK
906 
+++
907 
    load (ea) from ir[2:0] to operand1: An
908 
 
909 
    perform ALU operation: move operand1 to result
910 
 
911 
    save result to (ea): SP
912 
 
913 
    load ea to operand1: (SP)
914 
    move operand1 to result
915 
 
916 
    save result to (ea) from ir[2:0]: An
917 
 
918 
    SP += 4
919 
 
920 
    CC: not affected
921 
 
922 
    update PC
923 
 
924 
if( ir[15:8] == 8'b0100 1010 &amp;&amp; ir[7:6] != 2'b11 )
925 
    TST
926 
+++
927 
    ea operation size:
928 
    if( ir[7:6] == 2'b00 ) byte
929 
    else if( ir[7:6] == 2'b01 ) word
930 
    else if( ir[7:6] == 2'b10 ) long
931 
 
932 
    load (ea) from ir[5:0] to operand1: data alter
933 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
934 
                                (xxx).W 111 000, (xxx).L 111 001,
935 
 
936 
    perform ALU TST operation: set CC
937 
 
938 
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared
939 
 
940 
    update PC
941 
 
942 
if( ir[15:6] == 10'b0100 1010 11 &amp;&amp; ir[5:0] != 6'b111000 )
943 
    TAS
944 
+++
945 
    ea operation size: byte
946 
 
947 
    enable READ-MODIFY-WRITE bus cycle
948 
 
949 
    load (ea) from ir[5:0] to operand1: data alter
950 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
951 
                                (xxx).W 111 000, (xxx).L 111 001,
952 
 
953 
    perform ALU TAS operation: set bit 7 in result register
954 
 
955 
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared
956 
 
957 
    save result to (ea) from ir[5:0]: data alter
958 
 
959 
    disable READ-MODIFY-WRITE bus cycle
960 
 
961 
    update PC
962 
 
963 
if( ir[15:12] == 4'b0100 &amp;&amp; ir[8:6] == 3'b110 )
964 
    CHK
965 
+++
966 
    load (ea) from ir[5:0] to operand1: data
967 
        data:                     Dn 000,                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
968 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
969 
 
970 
    move operand1 to operand2
971 
 
972 
    load (ea) from ir[11:9] to operand1: Dn
973 
 
974 
 
975 
    ALU operation size: word
976 
 
977 
    perform ALU CHK operation: operand1 &lt; 0 or operand1 - operand2 &gt; 0
978 
 
979 
    CC: X not affected; N set if operand1 &lt; 0; cleared if operand1 - operand2 &gt; 0 else undefined; C,V,Z udefined
980 
 
981 
    if( ALU check ) trap CHK
982 
 
983 
    update PC
984 
 
985 
if( ir[15:12] == 4'b0100 &amp;&amp; ir[8:6] == 3'b111 )
986 
    LEA
987 
+++
988 
    load ea from ir[5:0] to address register: control
989 
        control:                                     (An) 010,                       (d16, An) 101, (d8, An, Xn) 110,
990 
                                (xxx).W 111 000, (xxx).L 111 001,         (d16, PC) 111 010, (d8, PC, Xn) 111 011
991 
 
992 
    move address register to operand1
993 
    perform ALU operation: move operand1 to result register
994 
 
995 
    save result to (ea) from ir[11:9]: An
996 
 
997 
    CC: not affected
998 
 
999 
    update PC
1000 
 
1001 
if( ir[15:6] == 10'b0100 1000 01 &amp;&amp; ir[5:3] != 3'b000 )
1002 
    PEA
1003 
+++
1004 
    load ea from ir[5:0] to address register: control
1005 
        control:                                     (An) 010,                       (d16, An) 101, (d8, An, Xn) 110,
1006 
                                (xxx).W 111 000, (xxx).L 111 001,         (d16, PC) 111 010, (d8, PC, Xn) 111 011
1007 
 
1008 
    SP -= 4
1009 
 
1010 
    move address register to operand1
1011 
    move operand1 to result
1012 
 
1013 
    save result to (ea): (SP)
1014 
 
1015 
    CC: not affected
1016 
 
1017 
    update PC
1018 
 
1019 
if( ir[15:6] == 10'b0100 0100 11 || ir[15:6] == 10'b0100 0110 11 )
1020 
    MOVE TO CCR, MOVE TO SR
1021 
+++
1022 
    ea operation size: word
1023 
 
1024 
    load (ea) from ir[5:0] to operand1: data
1025 
        data:                    Dn 000,                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1026 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
1027 
 
1028 
    if( ir[11:8] == 4'b0110 /MOVE TO SR/ )
1029 
        copy word form operand1 register to SR
1030 
    else
1031 
        copy lower byte form operand1 register to CCR
1032 
 
1033 
    update PC
1034 
 
1035 
if( ir[15:6] == 10'b0100 0000 11 )
1036 
    MOVE FROM SR
1037 
+++
1038 
    copy SR register to result register
1039 
 
1040 
    ea operation size: word
1041 
 
1042 
    save result to (ea) from ir[5:0]: data alter
1043 
        data alter:            Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1044 
                            (xxx).W 111 000, (xxx).L 111 001,
1045 
 
1046 
    CC: not affected
1047 
 
1048 
    update PC
1049 
 
1050 
if( ir[15:3] == 12'b0100 1110 0110 0 )
1051 
    MOVE USP to USP
1052 
+++
1053 
    load (ea) from ir[2:0] to operand1: An
1054 
 
1055 
    perform ALU operation: move operand1 to result
1056 
 
1057 
    move result to USP
1058 
 
1059 
    CC: not affected
1060 
 
1061 
    update PC
1062 
 
1063 
if( ir[15:3] == 13'b0100 1110 0110 1 )
1064 
    MOVE USP to An
1065 
+++
1066 
    move USP to operand1
1067 
 
1068 
    perform ALU operation: move operand1 to result
1069 
 
1070 
    save result to (ea) from ir[2:0]: An
1071 
 
1072 
    CC: not affected
1073 
 
1074 
    update PC
1075 
 
1076 
if( ir[15:12] == 4'b0100 &amp;&amp; ( (ir[11:8] == 4'b0000 &amp;&amp; ir[7:6] != 2'b11) || (ir[11:8] == 4'b0010) || (ir[11:8] == 4'b0100 &amp;&amp; ir[7:6] != 2'b11) ||
1077 
    (ir[11:8] == 4'b0110 &amp;&amp; ir[7:6] != 2'b11) || (ir[11:6] == 6'b1000 00) ) )
1078 
+++
1079 
    NEGX,CLR,NEG,NOT,NBCD
1080 
 
1081 
    load (ea) from ir[5:0] to operand1: data alter
1082 
    data alter:                    Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1083 
                                (xxx).W 111 000, (xxx).L 111 001
1084 
 
1085 
    ALU operation size:
1086 
    NEGX:    ir[7:6]: 00,01,10 byte,word,long
1087 
    CLR:    ir[7:6]: 00,01,10 byte,word,long
1088 
    NEG:    ir[7:6]: 00,01,10 byte,word,long
1089 
    NOT:    ir[7:6]: 00,01,10 byte,word,long
1090 
    NBCD:    ir[7:6]: 00 byte
1091 
 
1092 
    perform ALU operation:
1093 
    NEGX:    ir[11:8] == 4'b0000
1094 
    CLR:    ir[11:8] == 4'b0010
1095 
    NEG:    ir[11:8] == 4'b0100
1096 
    NOT:    ir[11:8] == 4'b0110
1097 
    NBCD:    ir[11:6] == 6'b1000 00
1098 
 
1099 
    CC:
1100 
    NEGX:    X=C set if borrow else clear; V set if overflow else clear; Z cleared if nonzero else unchanged; N set if negative else clear
1101 
    CLR:    X not affected; C cleared; V cleared; Z set; N cleared
1102 
    NEG:    X=C clear if zero else set; V set if overflow else clear; Z set if zero else clear; N set if negative else clear
1103 
    NOT:    X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
1104 
    NBCD:    X=C set if decimal borrow else cleared; Z cleared if nonzero else unchanged; N,V undefined
1105 
 
1106 
    save result to (ea) from ir[5:0]: data alter
1107 
 
1108 
    update PC
1109 
 
1110 
if( ir[15:12] == 4'b0100 &amp;&amp; (ir[11:3] == 9'b1000 01 000 || (ir[11:7] == 5'b1000 1 &amp;&amp; ir[5:3] == 3'b000) )
1111 
    SWAP,EXT
1112 
+++
1113 
    load (ea) from ir[5:0] to operand1: Dn
1114 
 
1115 
    ALU operation size: word
1116 
    SWAP:     ir[7:6]: 01 long
1117 
    EXT:    ir[7:6]: 10,11 byte to word, word to long
1118 
 
1119 
    perform ALU operation:
1120 
    SWAP:     ir[11:6] == 6'b1000 01
1121 
    EXT:    ir[11:7] == 5'b1000 1
1122 
 
1123 
    CC:
1124 
    SWAP:    X not affected; C cleared; V cleared; Z set if 32 bits are zero else cleared; N set if result MSB set else cleared
1125 
    EXT:    X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
1126 
 
1127 
    save result to (ea) from ir[5:0]: Dn
1128 
 
1129 
    update PC
1130 
 
1131 
if( ir[15:7] == 9'b0100 1100 1 &amp;&amp; ir[5:3] != 3'b000 )
1132 
    MOVEM memory to register
1133 
+++
1134 
    operation size:
1135 
    if( ir[6] == 1'b0 ) word
1136 
    else if ir[6] == 1'b1 ) long
1137 
 
1138 
    load ea from ir[5:0] to address register: control or postincrement
1139 
                                                (An) 010, (An)+ 011,            (d16, An) 101, (d8, An, Xn) 110,
1140 
                                (xxx).W 111 000, (xxx).L 111 001,                (d16, PC) 111 010, (d8, PC, Xn) 111 011
1141 
 
1142 
    register selection order: D0,D1,...D7,A0,A1,...,A7
1143 
 
1144 
    do
1145 
        if( ir1[0] == 1'b1 )
1146 
            read from (ea) to operand1
1147 
 
1148 
            perform ALU operation: move operand1 with sign-extension to result
1149 
 
1150 
            save result to selected register
1151 
 
1152 
            update address register
1153 
 
1154 
        shift ir1
1155 
    loop 16 times
1156 
 
1157 
    if( ir[5:3] == 3'b011 ) save address register back to An indexed by ir[2:0]
1158 
 
1159 
    CC: not affected
1160 
 
1161 
    update PC
1162 
 
1163 
if( ir[15:7] == 9'b0100 1000 1 &amp;&amp; ir[5:3] == 3'b100 )
1164 
    MOVEM register to memory, predecrement
1165 
+++
1166 
    operation size:
1167 
    if( ir[6] == 1'b0 ) word
1168 
    else if ir[6] == 1'b1 ) long
1169 
 
1170 
    load ea from ir[5:0] to address register: control alter or predecrement
1171 
                                        (An) 010,            -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1172 
                                (xxx).W 111 000, (xxx).L 111 001,
1173 
 
1174 
    register selection order: A7,A6,..A0,D7,D6,....D0
1175 
 
1176 
    do
1177 
        if( ir1[0] == 1'b1 )
1178 
            save selected register to operand1
1179 
 
1180 
            perform ALU operation: move operand1 to result
1181 
 
1182 
            save result to (ea)
1183 
 
1184 
            update address register
1185 
 
1186 
        shift ir1
1187 
    loop 16 times
1188 
 
1189 
    if( ir[5:3] == 3'b100 ) save address register back to An indexed by ir[2:0]
1190 
 
1191 
    CC: not affected
1192 
 
1193 
    update PC
1194 
 
1195 
if( ir[15:7] == 9'b0100 1000 1 &amp;&amp; ir[5:3] != 3'b000 &amp;&amp; ir[5:3] != 3b100 )
1196 
    MOVEM register to memory, control
1197 
+++
1198 
    operation size:
1199 
    if( ir[6] == 1'b0 ) word
1200 
    else if ir[6] == 1'b1 ) long
1201 
 
1202 
    load ea from ir[5:0] to address register: control alter or predecrement
1203 
                                        (An) 010,            -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1204 
                                (xxx).W 111 000, (xxx).L 111 001,
1205 
 
1206 
    register selection order: D0,D1,...D7,A0,A1,...,A7
1207 
 
1208 
    do
1209 
        if( ir1[0] == 1'b1 )
1210 
            save selected register to operand1
1211 
 
1212 
            perform ALU operation: move operand1 to result
1213 
 
1214 
            save result to (ea)
1215 
 
1216 
            update address register
1217 
 
1218 
        shift ir1
1219 
    loop 16 times
1220 
 
1221 
    CC: not affected
1222 
 
1223 
    update PC
1224 
 
1225 
*/
1226 
 
1227 
/*
1228 
 
1229 
&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;
1230 
microinstructions
1231 
 
1232 
MOVE_ea_reg_TO_An_address
1233 
MOVE_ea_reg_TO_Dn_address
1234 
MOVE_ir1_brief_ext_TO_An_Dn_addresses        // ir_valid
1235 
MOVE_An_output_TO_address
1236 
MOVE_Dn_output_TO_OP1
1237 
MOVE_An_output_TO_OP1
1238 
MOVE_zeros_TO_index
1239 
MOVE_ir1_brief_ext_TO_index                    // ir_valid
1240 
MOVE_ir1_byte_TO_offset                        // ir_valid
1241 
MOVE_ir1_word_TO_offset                        // ir_valid
1242 
MOVE_base_index_offset_TO_address
1243 
MOVE_ir1_absolute_word_TO_address            // ir_valid
1244 
MOVE_ir1_ir2_absolute_long_TO_address        // ir_valid
1245 
MOVE_pc_index_offset_TO_address
1246 
MOVE_trap_TO_address
1247 
MOVE_result_TO_An_input
1248 
MOVE_result_TO_Dn_input(size=)
1249 
MOVE_address_TO_An_input
1250 
MOVE_result_TO_data
1251 
 
1252 
MOVE_OP1_TO_OP2
1253 
MOVE_OP2_TO_OP1
1254 
MOVE_ADDR_TO_OP1
1255 
MOVE_data_TO_OP1
1256 
MOVE_immediate_TO_OP1(size=)
1257 
MOVE_result_TO_OP1
1258 
MOVE_moveq_TO_OP1
1259 
MOVE_PC_NEXT_TO_OP1
1260 
MOVE_zeros_TO_OP1
1261 
MOVE_ones_TO_OP1
1262 
MOVE_SR_TO_OP1
1263 
MOVE_USP_TO_OP1
1264 
MOVE_ir_TO_OP1
1265 
MOVE_address_bus_info_TO_OP2
1266 
MOVE_1_TO_OP2
1267 
MOVE_offset_TO_OP2
1268 
MOVE_count_TO_OP2
1269 
MOVE_addq_subq_TO_OP2
1270 
MOVE_result_TO_PC
1271 
MOVE_result_TO_USP
1272 
MOVE_zeros_TO_movem_mod_reg
1273 
MOVE_001111_TO_movem_mod_reg
1274 
MOVE_OP1_TO_movem_reg
1275 
MOVE_zeros_TO_movem_loop
1276 
MOVE_prefetch_ir_TO_ir
1277 
MOVE_interrupt_mask_TO_sr
1278 
MOVE_1_0_supervisor_trace_TO_sr
1279 
MOVE_reset_mask_TO_sr
1280 
MOVE_prefetch_ir_TO_PC
1281 
MOVE_prefetch_ir_TO_SSP
1282 
 
1283 
MOVE_illegal_instr_TO_TRAP
1284 
MOVE_divide_by_zero_TO_TRAP
1285 
MOVE_chk_TO_TRAP
1286 
MOVE_trapv_TO_TRAP
1287 
MOVE_priv_viol_TO_TRAP
1288 
MOVE_trap_TO_TRAP
1289 
MOVE_decoder_trap_TO_TRAP
1290 
MOVE_trace_TO_TRAP
1291 
MOVE_interrupt_trap_TO_TRAP
1292 
 
1293 
MOVE_0_TO_stop_flag
1294 
MOVE_1_TO_stop_flag
1295 
MOVE_sr15_TO_trace_flag
1296 
MOVE_0_TO_group_0_flag
1297 
MOVE_1_TO_group_0_flag
1298 
MOVE_0_TO_read_modify_write_flag
1299 
MOVE_1_TO_read_modify_write_flag
1300 
MOVE_0_TO_instruction_flag
1301 
MOVE_1_TO_instruction_flag
1302 
MOVE_1_TO_blocked_flag
1303 
MOVE_0_TO_read_flag
1304 
MOVE_1_To_read_flag
1305 
MOVE_0_TO_write_flag
1306 
MOVE_1_TO_write_flag
1307 
MOVE_0_TO_interrupt_flag
1308 
MOVE_1_TO_interrupt_flag
1309 
MOVE_1_TO_reset_flag
1310 
MOVE_0_TO_reset_flag
1311 
 
1312 
INCR_ADDR_BY_SIZE(size=)
1313 
DECR_ADDR_BY_SIZE(size=)
1314 
DECR_OP2_BY_1
1315 
CALL procedure
1316 
RETURN
1317 
INCR_movem_loop_BY_1
1318 
INCR_movem_mod_reg_BY_1
1319 
DECR_movem_mod_reg_BY_1
1320 
JMP: local label, trap, instr_fin, instr_fin_pc_loaded,
1321 
SHIFT_RIGHT_movem_reg
1322 
INCR_PC_BY_2
1323 
INCR_PC_BY_4
1324 
INCR_PC_BY_size(size=)
1325 
 
1326 
BRANCH(movem_loop == 4'b1000)
1327 
BRANCH(movem_reg[0] == 0)
1328 
BRANCH(operand2[5:0] == 6'b0)
1329 
BRANCH(special == 2'b01)
1330 
BRANCH(special == 2'b10)
1331 
BRANCH(condition == 1'b0)
1332 
BRANCH(condition == 1'b1)
1333 
BRANCH(result[15:0] == 16'hFFFF)
1334 
BRANCH(V == 1'b0)
1335 
BRANCH(stop_flag == 1'b1)
1336 
BRANCH(ir[7:0] != 8'b0)
1337 
BRANCH(decoder_trap == 8'b0)
1338 
BRANCH(trace_flag == 1'b0)
1339 
BRANCH(group_0_flag == 0)
1340 
 
1341 
WAIT_RESET, WAIT_MEMORY_READ(size, address), WAIT_MEMORY_WRITE(size, address, select), WAIT_interrupt, WAIT_blocked
1342 
WAIT_prefetch_ir_valid
1343 
 
1344 
subprocedures:
1345 
ea(size=, reg=, mod=, type=, select=)
1346 
 
1347 
LOAD_EA:             to address register
1348 
PERFORM_EA_READ:     to operand1
1349 
PERFORM_EA_WRITE:     from result
1350 
SAVE_EA
1351 
 
1352 
&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;&gt;
1353 
 
1354 
TYPE.ALL: all
1355 
                                Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1356 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
1357 
TYPE.CONTROL_POSTINC: control or postincrement
1358 
                                                             (An) 010, (An)+ 011,            (d16, An) 101, (d8, An, Xn) 110,
1359 
                                (xxx).W 111 000, (xxx).L 111 001,                (d16, PC) 111 010, (d8, PC, Xn) 111 011
1360 
TYPE.CONTROLALTER_PREDEC: control alter or predecrement
1361 
                                                              (An) 010,            -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1362 
                                (xxx).W 111 000, (xxx).L 111 001,
1363 
TYPE.CONTROL: control
1364 
                                                              (An) 010,                       (d16, An) 101, (d8, An, Xn) 110,
1365 
                                (xxx).W 111 000, (xxx).L 111 001,                  (d16, PC) 111 010, (d8, PC, Xn) 111 011
1366 
TYPE.DATAALTER: data alter
1367 
                                Dn 000,                      (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1368 
                                (xxx).W 111 000, (xxx).L 111 001,
1369 
TYPE.DN_AN: Dn, An
1370 
                                Dn 000, An 001
1371 
TYPE.MEMORYALTER: memory alter
1372 
                                                              (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1373 
                                (xxx).W 111 000, (xxx).L 111 001
1374 
TYPE.DATA: data
1375 
                                Dn 000,                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1376 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
1377 
 
1378 
 
1379 
</pre></div> </div>
1380 
<hr class="footer"/><address class="footer"><small>Generated on Sat Dec 11 2010 13:21:12 for ao68000 by&#160;
1381 
<a href="http://www.doxygen.org/index.html">
1382 
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
1383 
</body>
1384 
</html>

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.