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[/] [ao68000/] [trunk/] [doc/] [src/] [old_notes.txt] - Blame information for rev 12

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1 12 alfik 
*******************************************************************************************************************************************
2 
NOTE: The information bellow is not current. It is here only for historical reasons.
3 
*******************************************************************************************************************************************
4 
 
5 
if( ir[15:12] == 4'b0000 && ir[8] == 1'b0 && ir[11:9] != 3'b100 && ir[11:9] != 3'b110 &&
6 
    ir[15:0] != 16'b0000_000_0_00_111100 && ir[15:0] != 16'b0000_000_0_01_111100 &&
7 
    ir[15:0] != 16'b0000_001_0_00_111100 && ir[15:0] != 16'b0000_001_0_01_111100 &&
8 
    ir[15:0] != 16'b0000_101_0_00_111100 && ir[15:0] != 16'b0000_101_0_01_111100
9 
)
10 
    ANDI,EORI,ORI,ADDI,SUBI
11 
+++
12 
    if( ir[7:6] == 2'b00 ) load ir1[7:0] to operand1[7:0]
13 
    else if( ir[7:6] == 2'b01 ) load ir1[15:0] to operand1[15:0]
14 
    else if( ir[7:6] == 2'b10 ) load { ir1, ir2 } to operand1[31:0]
15 
 
16 
    move operand1 to operand2
17 
 
18 
    operation size:
19 
    if( ir[7:6] == 2'b00 ) byte
20 
    else if( ir[7:6] == 2'b01 ) word
21 
    else if( ir[7:6] == 2'b10 ) long
22 
 
23 
    load (ea) from ir[5:0] to operand1: data alter
24 
                                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
25 
                                (xxx).W 111 000, (xxx).L 111 001
26 
 
27 
    perform ALU operation:
28 
        if( ir[11:9] == 3'b000 ) OR
29 
        else if( ir[11:9] == 3'b001 ) AND
30 
        else if( ir[11:9] == 3'b010 ) SUB
31 
        else if( ir[11:9] == 3'b011 ) ADD
32 
        else if( ir[11:9] == 3'b101 ) EOR
33 
 
34 
    update CCR:
35 
        ANDI,EORI,ORI:    X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
36 
        ADDI,SUBI: same as ADD: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared;
37 
            N set if result negative else cleared
38 
 
39 
    save result to (ea) from ir[5:0]
40 
 
41 
    update PC
42 
 
43 
if( ir[15:0] == 16'b0000_000_0_00_111100 || ir[15:0] == 16'b0000_000_0_01_111100 ||
44 
    ir[15:0] == 16'b0000_001_0_00_111100 || ir[15:0] == 16'b0000_001_0_01_111100 ||
45 
    ir[15:0] == 16'b0000_101_0_00_111100 || ir[15:0] == 16'b0000_101_0_01_111100
46 
)
47 
    ORI to CCR,ORI to SR,ANDI to CCR,ANDI to SR,EORI to CCR,EORI to SR
48 
+++
49 
    if( ir[7:6] == 2'b00 ) load ir1[7:0] to operand1[7:0]
50 
    else if( ir[7:6] == 2'b01 ) load ir1[15:0] to operand1[15:0]
51 
    else if( ir[7:6] == 2'b10 ) load { ir1, ir2 } to operand1[31:0]
52 
 
53 
    move operand1 to operand2
54 
 
55 
    operation size:
56 
    if( ir[7:6] == 2'b00 ) byte
57 
    else if( ir[7:6] == 2'b01 ) word
58 
    else if( ir[7:6] == 2'b10 ) long
59 
 
60 
    move SR to operand1
61 
 
62 
    perform ALU operation:
63 
        if( ir[11:9] == 3'b000 ) OR
64 
        else if( ir[11:9] == 3'b001 ) AND
65 
        else if( ir[11:9] == 3'b101 ) EOR
66 
 
67 
    move result to operand1
68 
 
69 
    save operand1 to CCR/SR
70 
 
71 
    update CCR:
72 
        result
73 
 
74 
    update PC
75 
 
76 
if( ir[15:12] == 4'b0000 && ir[8] == 1'b0 && ir[11:9] = 3'b110 )
77 
    CMPI
78 
+++
79 
    if( ir[7:6] == 2'b00 ) load ir1[7:0] to operand2[7:0]
80 
    else if( ir[7:6] == 2'b01 ) load ir1[15:0] to operand2[15:0]
81 
    else if( ir[7:6] == 2'b10 ) load { ir1, ir2 } to operand2[31:0]
82 
 
83 
    operation size:
84 
    if( ir[7:6] == 2'b00 ) byte
85 
    else if( ir[7:6] == 2'b01 ) word
86 
    else if( ir[7:6] == 2'b10 ) long
87 
 
88 
    load (ea) from ir[5:0] to operand1: data alter
89 
                                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
90 
                                (xxx).W 111 000, (xxx).L 111 001
91 
 
92 
    perform ALU operation:
93 
        if( ir[11:9] == 3'b110 ) CMP=SUB
94 
 
95 
    update CCR:
96 
        CMPI: same as CMP: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared;
97 
            N set if negative else cleared
98 
 
99 
    update PC
100 
 
101 
if( ir[15:12] == 4'b0000 && ir[11:8] == 4'b1000 && ir[7:6] != 2'b00 )
102 
    BCHG,BCLR,BSET immediate
103 
+++
104 
    load ir1[7:0] to operand1[7:0]
105 
 
106 
    move operand1 to operand2
107 
 
108 
    load (ea) form ir[5:0] to operand1: data alter
109 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
110 
                                (xxx).W 111 000, (xxx).L 111 001
111 
 
112 
    operation size:
113 
    if( ir[5:3] == 3'b000 ) long
114 
    else if( ir[5:3] != 3'b000 ) byte
115 
 
116 
    perform bit operation:
117 
    test(  of Destination ) -> Z; test(  of Destination )[0][1] ->  of Destination
118 
    if( ir[7:6] == 2'b01 ) BCHG
119 
    else if( ir[7:6] == 2'b10 ) BCLR
120 
    else if( ir[7:6] == 2'b11 ) BSET
121 
 
122 
    update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared
123 
 
124 
    save result to (ea) form ir[5:0]
125 
 
126 
    update PC
127 
 
128 
if( ir[15:12] == 4'b0000 && ir[11:8] == 4'b1000 && ir[7:6] == 2'b00 )
129 
    BTST immediate
130 
+++
131 
    load ir1[7:0] to operand1[7:0]
132 
 
133 
    move operand1 to operand2
134 
 
135 
    load (ea) form ir[5:0] to operand1: data address
136 
        data address:            Dn 000,                    (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
137 
                                (xxx).W 111 000, (xxx).L 111 001,                (d16, PC) 111 010, (d8, PC, Xn) 111 011
138 
 
139 
    operation size:
140 
    if( ir[5:3] == 3'b000 ) long
141 
    else if( ir[5:3] != 3'b000 ) byte
142 
 
143 
    perform bit operation:
144 
    test(  of Destination ) -> Z
145 
    if( ir[7:6] == 2'b00 ) BTST
146 
 
147 
    update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared
148 
 
149 
    update PC
150 
 
151 
if( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] != 3'b001 && ir[8:6] != 3'b100 )
152 
    BCHG,BCLR,BSET register
153 
+++
154 
    load (ea) from ir[11:9] to operand1[7:0]: Dn
155 
 
156 
    move operand1 to operand2
157 
 
158 
    load (ea) form ir[5:0] to operand1: data alter
159 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
160 
                                (xxx).W 111 000, (xxx).L 111 001
161 
 
162 
    operation size:
163 
    if( ir[5:3] == 3'b000 ) long
164 
    else if( ir[5:3] != 3'b000 ) byte
165 
 
166 
    perform bit operation:
167 
    test(  of Destination ) -> Z; test(  of Destination )[0][1] ->  of Destination
168 
    if( ir[7:6] == 2'b01 ) BCHG
169 
    else if( ir[7:6] == 2'b10 ) BCLR
170 
    else if( ir[7:6] == 2'b11 ) BSET
171 
 
172 
    update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared
173 
 
174 
    save result to (ea) form ir[5:0]
175 
 
176 
    update PC
177 
 
178 
if( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] != 3'b001 && ir[8:6] == 3'b100 )
179 
    BTST register
180 
+++
181 
    load (ea) from ir[11:9] to operand1[7:0]: Dn
182 
 
183 
    move operand1 to operand2
184 
 
185 
    load (ea) form ir[5:0] to operand1: data address
186 
        data address:            Dn 000,                    (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
187 
                                (xxx).W 111 000, (xxx).L 111 001,                (d16, PC) 111 010, (d8, PC, Xn) 111 011
188 
 
189 
    operation size:
190 
    if( ir[5:3] == 3'b000 ) long
191 
    else if( ir[5:3] != 3'b000 ) byte
192 
 
193 
    perform bit operation:
194 
    test(  of Destination ) -> Z
195 
    if( ir[7:6] == 2'b00 ) BTST
196 
 
197 
    update CCR: X,N,V,C not affected; Z set if bit tested is zero else cleared
198 
 
199 
    update PC
200 
 
201 
if( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] == 3'b001 && ( ir[7:6] == 2'b00 || ir[7:6] == 2'b01 ) )
202 
    MOVEP memory to register
203 
+++
204 
    operation size:
205 
    if( ir[7:6] == 2'b00 ) word
206 
    if( ir[7:6] == 2'b01 ) long
207 
 
208 
    load ea from ir[2:0] to address register: (d16, An)
209 
 
210 
    do
211 
        load from (address) to operand1 register, long
212 
        move two alternate bytes to result register
213 
        increment ea by 4
214 
    repeat for long
215 
 
216 
    save result to (ea) from ir[11:9]: Dn, word ( ir[7:6] == 2'b00 ), long ( ir[7:6] == 2'b01 )
217 
 
218 
    update CCR: no change
219 
    update PC
220 
 
221 
if( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] == 3'b001 && ( ir[7:6] == 2'b10 || ir[7:6] == 2'b11 ) )
222 
    MOVEP register to memory
223 
+++
224 
    operation size:
225 
    if( ir[7:6] == 2'b10 ) word
226 
    if( ir[7:6] == 2'b11 ) long
227 
 
228 
    load (ea) from ir[11:9] to operand1: Dn, long
229 
 
230 
    load ea from ir[2:0] to address register: (d16, An)
231 
 
232 
    do
233 
        move two alternate bytes to result register
234 
        save result register to (addreess), long, only selected bytes
235 
        increment ea by 4
236 
    repeat for long
237 
 
238 
    update CCR: no change
239 
    update PC
240 
 
241 
if( ir[15:14] == 2'b00 && ir[13:12] != 2'b00 && ir[8:6] != 3'b001)
242 
    MOVE
243 
+++
244 
    size of operation: ir[13:12]: 01,11,10 byte,word,long
245 
 
246 
    load (ea) from ir[5:0] to operand1: all modes.
247 
        all modes:                Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
248 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
249 
 
250 
    copy operand1 to result register
251 
 
252 
    save result to (ea) from ir[11:6]: data alter.
253 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
254 
                                (xxx).W 111 000, (xxx).L 111 001,
255 
 
256 
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
257 
 
258 
    update PC
259 
 
260 
if( ir[15:14] == 2'b00 && (ir[13:12] == 2'b11 || ir[13:12] == 2'b10) && ir[8:6] == 3'b001)
261 
    MOVEA
262 
+++
263 
    size of operation: ir[13:12]: 11,10 word,long
264 
 
265 
    load (ea) from ir[5:0] to operand1: all modes.
266 
        all modes:                Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
267 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
268 
 
269 
    copy operand1 to result register
270 
 
271 
    save result to (ea) from ir[11:6]: An
272 
 
273 
    CC: not affected
274 
 
275 
    update PC
276 
 
277 
if( ir[15:12] == 4'b1100 && (ir[8:4] == 5'b10100 || 5'b11000) )
278 
    EXG
279 
+++
280 
    load (ea) from ir[5:0] to operand1: Dn, An
281 
 
282 
    perform ALU operation: move operand1 to result register
283 
 
284 
    load (ea) from ir[11:9] with mode in ir[7:3] to operand1: Dn (5'b01000 or 5'b10001), An (5'b01001)
285 
 
286 
    save result to (ea) from ir[11:9] with mode in ir[7:3]: Dn (5'b01000 or 5'b10001), An (5'b01001),
287 
 
288 
    perform ALU operation: move operand1 to result register
289 
 
290 
    save result to (ea) from ir[5:0]: Dn, An
291 
 
292 
    CC: not affected
293 
 
294 
    update PC
295 
 
296 
if( ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || 3'b101 || 3'b110) && ir[5:3] == 3'b001 )
297 
    CMPM
298 
+++
299 
    load (ea) from ir[2:0] to operand1: postincrement (An)+
300 
 
301 
    move operand1 to operand2
302 
 
303 
    load (ea) from ir[11:9] to operand1: postincrement (An)+
304 
 
305 
    ALU operation size:
306 
    if( ir[7:6] == 2'b00 ) byte
307 
    else if( ir[7:6] == 2'b01 ) word
308 
    else if( ir[7:6] == 2'b10 ) long
309 
 
310 
    perform ALU operation: CMPM == SUB
311 
 
312 
    CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared
313 
    Ax dest, Ay source: postincrement: +(An)
314 
 
315 
    update PC
316 
 
317 
if( ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || 3'b101 || 3'b110) && ir[5:3] != 3'b001 )
318 
    EOR
319 
+++
320 
    load (ea) from ir[11:9] to operand1: Dn
321 
 
322 
    move operand1 to operand2
323 
 
324 
    load (ea) from ir[5:0] to operand1: data alter
325 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
326 
                                (xxx).W 111 000, (xxx).L 111 001,
327 
 
328 
    ALU operation size:
329 
    if( ir[7:6] == 2'b00 ) byte
330 
    else if( ir[7:6] == 2'b01 ) word
331 
    else if( ir[7:6] == 2'b10 ) long
332 
 
333 
    perform ALU operation: EOR
334 
 
335 
    CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
336 
 
337 
    save result to (ea) from ir[5:0]: data alter
338 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
339 
                                (xxx).W 111 000, (xxx).L 111 001,
340 
    update PC
341 
 
342 
if( (ir[15:12] == 4'b1101 || 4'b1001 || 4'b1100 || 4'b1000) &&
343 
    (ir[8:4] == 5'b10001 || 5'b10010 || 5'b10011 || 5'b10101 || 5'b10110 || 5'b10111 || 5'b11001 || 5'b11010 || 5'b11011) )
344 
 
345 
    ADD to mem,SUB to mem,AND to mem,OR to mem
346 
+++
347 
    load (ea) from ir[11:9] to operand1: Dn
348 
 
349 
    move operand1 to operand2
350 
 
351 
    load (ea) indexed by ir[5:0] to operand1: memory alter
352 
        memory alter:                                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
353 
                                (xxx).W 111 000, (xxx).L 111 001
354 
 
355 
    ALU operation size:
356 
    if( ir[7:6] == 2'b00 ) byte
357 
    else if( ir[7:6] == 2'b01 ) word
358 
    else if( ir[7:6] == 2'b10 ) long
359 
 
360 
    perform ALU operation:
361 
    if( ir[15:12] == 4'b1101 ) ADD
362 
    else if( ir[15:12] == 4'b1001 ) SUB
363 
    else if( ir[15:12] == 4'b1100 ) AND
364 
    else if( ir[15:12] == 4'b1000 ) OR
365 
 
366 
    if( ADD,SUB )
367 
        CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared;
368 
            N set if result negative else cleared
369 
    else if( AND,OR )
370 
        CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
371 
 
372 
    save result to (ea) from ir[5:0]: memory alter
373 
        memory alter:                                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
374 
                                (xxx).W 111 000, (xxx).L 111 001
375 
 
376 
    update PC
377 
 
378 
if( (ir[15:12] == 4'b1101 || 4'b1001 || 4'b1100 || 4'b1000) && (ir[8:6] == 3'b000 || 3'b001 || 3'b010) )
379 
    ADD to Dn,SUB to Dn,AND to Dn,OR to Dn
380 
+++
381 
    load (ea) from ir[5:0] to operand1: all modes
382 
        all modes:                 Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
383 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
384 
 
385 
    move operand1 to operand2
386 
 
387 
    load (ea) from ir[11:9] to operand1: Dn
388 
 
389 
    ALU operation size:
390 
    if( ir[7:6] == 2'b00 ) byte
391 
    else if( ir[7:6] == 2'b01 ) word
392 
    else if( ir[7:6] == 2'b10 ) long
393 
 
394 
    perform ALU operation:
395 
    if( ir[15:12] == 4'b1101 ) ADD
396 
    else if( ir[15:12] == 4'b1001 ) SUB
397 
    else if( ir[15:12] == 4'b1100 ) AND
398 
    else if( ir[15:12] == 4'b1000 ) OR
399 
 
400 
    if( ADD,SUB )
401 
        CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared;
402 
            N set if result negative else cleared
403 
    else if( AND,OR )
404 
        CC: X not affected; C cleared; V cleared; Z set if zero else clear; N set if MSB set else cleared
405 
 
406 
    save result to (ea) from ir[11:9]: Dn
407 
 
408 
    update PC
409 
 
410 
if( (ir[15:12] == 4'b1011) && (ir[8:6] == 3'b000 || 3'b001 || 3'b010) )
411 
    CMP
412 
+++
413 
    load (ea) from ir[5:0] to operand1: all modes
414 
        all modes:                 Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
415 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
416 
 
417 
    move operand1 to operand2
418 
 
419 
    load (ea) from ir[11:9] to operand1: Dn
420 
 
421 
    ALU operation size:
422 
    if( ir[7:6] == 2'b00 ) byte
423 
    else if( ir[7:6] == 2'b01 ) word
424 
    else if( ir[7:6] == 2'b10 ) long
425 
 
426 
    perform ALU operation:
427 
    if( ir[15:12] == 4'b1011 ) CMP=SUB
428 
 
429 
    CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared
430 
 
431 
    update PC
432 
 
433 
if( (ir[15:12] == 4'b1100 || 4'b1000) && ir[7:6] == 2'b11 )
434 
    MULS,MULU,DIVS,DIVU
435 
+++
436 
    load (ea) from ir[5:0] to operand1: data
437 
            data:        Dn 000,                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
438 
                        (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
439 
 
440 
    move operand1 to operand2
441 
 
442 
    load (ea) from ir[11:9] to operand1: Dn
443 
 
444 
    perform ALU operation:
445 
    if( ir[15:12] == 4'b1100 && ir[8] == 1'b0 ) MULU
446 
    else if( ir[15:12] == 4'b1100 && ir[8] == 1'b1 ) MULS
447 
    else if( ir[15:12] == 4'b1000 && ir[8] == 1'b0 ) DIVU
448 
    else if( ir[15:12] == 4'b1000 && ir[8] == 1'b1 ) DIVS
449 
 
450 
    if( MULU/MULS )
451 
        CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
452 
    else if( DIVU/DIVS )
453 
        CC: X not affected; C cleared; V set if overflow else if trap undefined else cleared;
454 
            Z set if quotient zero else if trap or overflow undefined else cleared;
455 
            N set if quotient negative else if trap or overflow undefined else cleared;
456 
 
457 
    save result to (ea) from ir[11:9]: Dn
458 
 
459 
    update PC
460 
 
461 
if( (ir[15:12] == 4'b1101 || 4'b1001) && (ir[8:6] == 3'b011 || 3'b111) )
462 
    ADDA,SUBA
463 
+++
464 
    load (ea) from ir[5:0] to operand1: all modes
465 
        all modes:                Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
466 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
467 
 
468 
    move operand1 to operand2
469 
 
470 
    load (ea) from ir[11:9] to operand1: An
471 
 
472 
    ALU operation size, source is sign-extended:
473 
    if( ir[8] == 1'b0 ) word
474 
    else if( ir[8] == 1'b1 ) long
475 
 
476 
    perform ALU operation:
477 
    if( ir[14:12] == 3'b101 ) ADD
478 
    else if( ir[14:12] == 3'b001 ) SUB
479 
 
480 
    CC: not affected
481 
 
482 
    save result sign-extended to (ea) from ir[11:9]: An
483 
 
484 
    update PC
485 
 
486 
if( (ir[15:12] == 4'b1011) && (ir[8:6] == 3'b011 || 3'b111) )
487 
    CMPA
488 
+++
489 
    load (ea) from ir[5:0] to operand1: all modes
490 
        all modes:                Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
491 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
492 
 
493 
    move operand1 to operand2
494 
 
495 
    load (ea) from ir[11:9] to operand1: An
496 
 
497 
    ALU operation size, source is sign-extended:
498 
    if( ir[8] == 1'b0 ) word
499 
    else if( ir[8] == 1'b1 ) long
500 
 
501 
    perform ALU operation:
502 
    if( ir[14:12] == 3'b011 ) CMP==SUB
503 
 
504 
    CC: X not affected; C set if borrow else cleared; V set if overflow else cleared; Z set if zero else cleared; N set if negative else cleared
505 
 
506 
    update PC
507 
 
508 
if( ((ir[15:12] == 4'b1100 || 4'b1000) && ir[8:4] == 5'b10000) || ((if[15:12] == 4'b1101 || 4'b1001) && (ir[8:4] == 5'b10000 || 5'b10100 || 5'b11000) )
509 
    ABCD,SBCD,ADDX,SUBX
510 
+++
511 
    load (ea) from ir[2:0] to operand1: Dn (ir[3] == 1'b0), -(An) (ir[3] == 1'b1)
512 
 
513 
    move operand1 to operand2
514 
 
515 
    load (ea) from ir[11:9] to operand1: Dn (ir[3] == 1'b0), -(An) (ir[3] == 1'b1)
516 
 
517 
 
518 
    ALU operation size:
519 
    if( ir[7:6] == 2'b00 ) byte
520 
    else if( ir[7:6] == 2'b01 ) word
521 
    else if( ir[7:6] == 2'b10 ) long
522 
 
523 
    perform ALU operation:
524 
    if( ir[14:12] == 3'b100 ) ABCD
525 
    else if( ir[14:12] == 3'b000 ) SBCD
526 
    else if( ir[14:12] == 3'b101 ) ADDX
527 
    else if( ir[14:12] == 3'b001 ) SUBX
528 
 
529 
    if( ir[12] == 1'b0 /ABCD,SBCD/ )
530 
        CC: X=C set if decimal carry [borrow] else cleared; Z cleared if result nonzero else unchanged; N,V undefined
531 
    else
532 
        CC: X=C set if carry[borrow] else cleared; V set if overflow else cleared; Z cleared if nonzero else unchanged; N set if negative else cleared
533 
 
534 
    save result to (ea) from ir[11:9]: Dn (ir[3] == 1'b0), -(An) (ir[3] == 1'b1)
535 
 
536 
    update PC
537 
 
538 
if( ir[15:12] == 4'b1110 && ir[7:6] == 2'b11 && ir[11] == 1'b0 )
539 
    ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all memory
540 
+++
541 
    load (ea) from ir[5:0] to operand1: memory alter
542 
        memory alter:                                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
543 
                                (xxx).W 111 000, (xxx).L 111 001
544 
    load 1'b1 to operand2
545 
 
546 
    ALU operation size: word
547 
 
548 
    ALU shift/rotate direction:
549 
    if( ir[8] == 1'b0 ) right
550 
    else if( ir[8] == 1'b1 ) left
551 
 
552 
    perform ALU operation:
553 
    if( ir[10:9] == 2'b00 ) ASL/ASR
554 
    else if( ir[10:9] == 2'b01 ) LSL,LSR
555 
    else if( ir[10:9] == 2'b11 ) ROL,ROR
556 
    else if( ir[10:9] == 2'b10 ) ROXL,ROXR
557 
 
558 
    CC: X set to last bit, unchanged if zero shift[same][not affected][same set]; N set if MSB bit is set else cleared; Z set if zero else cleared;
559 
        V set if MSB bit changed during shift else cleared[cleared][cleared][cleared]; C set to last bit, cleared if zero shift[same][same][set to X]
560 
 
561 
    save result to (ea) from ir[5:0]: memory alter
562 
        memory alter:                                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
563 
                                (xxx).W 111 000, (xxx).L 111 001
564 
    update PC
565 
 
566 
if( ir[15:12] == 4'b1110 && (ir[7:6] == 2'b00 || 2'b01 || 2'b10) )
567 
    ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all immediate/register
568 
+++
569 
    load (ea) from ir[11:9] to operand1: Dn
570 
 
571 
    move operand1 to operand2
572 
 
573 
    load (ea) from ir[2:0] to operand1: Dn
574 
 
575 
    if( ir[5] == 1'b0 )
576 
        if( ir[11:9] == 3'b000 ) load 4'b1000 to operand2
577 
        else load ir[11:9] to operand2
578 
    else if( ir[5] == 1'b1 )
579 
        perform operand2 modulo 64
580 
 
581 
    ALU operation size:
582 
    if( ir[7:6] == 2'b00 ) byte
583 
    else if( ir[7:6] == 2'b01 ) word
584 
    else if( ir[7:6] == 2'b10 ) long
585 
 
586 
    ALU shift/rotate direction:
587 
    if( ir[8] == 1'b0 ) right
588 
    else if( ir[8] == 1'b1 ) left
589 
 
590 
    perform ALU operation:
591 
    if( ir[4:3] == 2'b00 ) ASL/ASR
592 
    else if( ir[4:3] == 2'b01 ) LSL,LSR
593 
    else if( ir[4:3] == 2'b11 ) ROL,ROR
594 
    else if( ir[4:3] == 2'b10 ) ROXL,ROXR
595 
 
596 
    CC: X set to last bit, unchanged if zero shift[same][not affected][same set]; N set if MSB bit is set else cleared; Z set if zero else cleared;
597 
        V set if MSB bit changed during shift else cleared[cleared][cleared][cleared]; C set to last bit, cleared if zero shift[same][same][set to X]
598 
 
599 
    save result to (ea) from ir[2:0]: Dn
600 
 
601 
    update PC
602 
 
603 
if( ir[15:12] == 4'b0111 && ir[8] == 1'b0 )
604 
    MOVEQ
605 
+++
606 
    load ir[7:0] sign-extended to result register
607 
 
608 
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
609 
 
610 
    save result to (ea) from ir[11:9]: Dn
611 
 
612 
    update PC
613 
 
614 
if( ir[15:12] == 4'b0110 && ir[11:8] == 4'b0001 )
615 
    BSR
616 
+++
617 
    CC: not affected
618 
 
619 
    SP -= 4
620 
 
621 
    move PC to operand1
622 
    move operand1 to result
623 
 
624 
    save result to (ea): (SP)
625 
 
626 
    if( ir[7:0] == 8'b0 )
627 
        add to PC: ir1[15:0]
628 
    else
629 
        add to PC: ir[7:0]
630 
 
631 
    return
632 
 
633 
if( ir[15:12] == 4'b0110 && ir[11:8] != 4'b0001 )
634 
    Bcc,BRA
635 
+++
636 
    condition:                               high(!C & !Z) 0010, low or same(C | V) 0011,
637 
                carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111,
638 
                overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011,
639 
                greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V) 1101,
640 
                greater than(N & V & !Z | !N & !V & !Z) 1110, less or equal(Z | N & !V | !N & V) 1111
641 
 
642 
    CC: not affected
643 
 
644 
    if( contidtion on ir[11:8] true )
645 
        if( ir[7:0] == 8'b0 )
646 
            add to PC: ir1[15:0]
647 
        else
648 
            add to PC: ir[7:0]
649 
 
650 
        return
651 
 
652 
    update PC
653 
 
654 
if( ir[15:12] == 4'b0101 && ir[7:6] == 2'b11 && ir[5:3] != 2'b001 )
655 
    Scc
656 
+++
657 
    condition:    true(1) 0000, false(0) 0001, high(!C & !Z) 0010, low or same(C | V) 0011,
658 
                carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111,
659 
                overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011,
660 
                greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V),
661 
                greater than(N & V & !Z | !N & !V & !Z), less or equal(Z | N & !V | !N & V) 1111
662 
 
663 
    if( contidtion on ir[11:8] false )
664 
        load 8'b00000000 to result
665 
    else
666 
        load 8'b11111111 to result
667 
 
668 
    operation size: byte
669 
 
670 
    save result to (ea) from ir[5:0]: data alter.
671 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
672 
                                (xxx).W 111 000, (xxx).L 111 001,
673 
    CC: not affected
674 
 
675 
    update PC
676 
 
677 
if( ir[15:12] == 4'b0101 && ir[7:6] == 2'b11 && ir[5:3] == 2'b001 )
678 
    DBcc
679 
+++
680 
    condition:    true(1) 0000, false(0) 0001, high(!C & !Z) 0010, low or same(C | V) 0011,
681 
                carry clear(!C) 0100, carry set(C) 0101, not equal(Z) 0110, equal(!Z) 0111,
682 
                overflow clear(!V) 1000, overflow set(V) 1001, plus(!N) 1010, minus(N) 1011,
683 
                greater or equal(N & V | !N & !V) 1100, less than(N & !V | !N & V),
684 
                greater than(N & V & !Z | !N & !V & !Z), less or equal(Z | N & !V | !N & V) 1111
685 
 
686 
    CC: not affected
687 
 
688 
    if( condition on ir[11:8] false )
689 
        load (ea) from ir[2:0] to operand1: Dn
690 
 
691 
        load 1'b1 to operand2
692 
 
693 
        ALU operation size: word
694 
 
695 
        perform ALU operation: SUB
696 
 
697 
        save result to (ea) from ir[2:0]: Dn
698 
 
699 
        if( result != -1 )
700 
            add to PC: ir1[15:0]
701 
            return
702 
 
703 
    update PC
704 
 
705 
if( ir[15:12] == 4'b0101 && ir[7:6] != 2'b11 && ir[5:3] != 3'b001 )
706 
    ADDQ,SUBQ not An
707 
+++
708 
    if( ir[11:9] == 3'b000 )
709 
        load 4'b1000 to operand2
710 
    else
711 
        load ir[11:9] to operand2
712 
 
713 
    load (ea) from by ir[5:0] to operand1: data alter
714 
        data alter:                Dn 000,         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
715 
                                (xxx).W 111 000, (xxx).L 111 001,
716 
 
717 
    ALU operation size:
718 
    if( ir[7:6] == 2'b10 ) long
719 
    else if( ir[7:6] == 2'b01 ) word
720 
    else if( ir[7:6] == 2'b00 ) byte
721 
 
722 
    perform ALU operation:
723 
    if( ir[8] == 1'b0 ) ADDQ
724 
    else if( ir[8] == 1'b1 ) SUBQ
725 
 
726 
    CC: X=C set if carry[borrow] generated else cleared; V set if overflow else cleared; Z set if result zero else cleared;
727 
        N set if result negative else cleared
728 
 
729 
    save result to (ea) from ir[5:0]
730 
 
731 
    update PC
732 
 
733 
if( ir[15:12] == 4'b0101 && ir[7:6] != 2'b11 && ir[5:3] == 3'b001)
734 
    ADDQ,SUBQ An
735 
+++
736 
    if( ir[11:9] == 3'b000 )
737 
        load 4'b1000 to operand2
738 
    else
739 
        load ir[11:9] to operand2
740 
 
741 
    load (ea) from by ir[2:0] to operand1: An
742 
 
743 
    ALU operation size: long
744 
 
745 
    perform ALU operation:
746 
    if( ir[8] == 1'b0 ) ADD
747 
    else if( ir[8] == 1'b1 ) SUB
748 
 
749 
    CC: not affected
750 
 
751 
    save result to (ea) from ir[2:0]: An
752 
 
753 
    update PC
754 
 
755 
if( ir[15:0] == 16'b0100 1110 0111 0001 )
756 
    NOP
757 
+++
758 
    CC: not affected
759 
 
760 
    update PC
761 
 
762 
if( ir[15:0] == 16'b0100 1110 0111 0000 )
763 
    RESET
764 
+++
765 
    hold REST output for 124 clock cycles
766 
 
767 
    CC: not affected
768 
 
769 
    update PC
770 
 
771 
if( ir[15:0] == 16'b0100 1110 0111 0010 )
772 
    STOP
773 
+++
774 
    copy ir1[15:0] to SR
775 
 
776 
    Resume when trace, interrupt or rest.
777 
 
778 
if( ir[15:5] == 12'b0100 1110 0100 )
779 
    TRAP
780 
+++
781 
    TRAP with vector indexed by ir[3:0]
782 
 
783 
    CC: not affected
784 
 
785 
if( ir[15:0] == 16'b0100 1110 0111 0110 )
786 
    TRAPV
787 
+++
788 
    if( V ) TRAP
789 
 
790 
    CC: not affected
791 
 
792 
    update PC
793 
 
794 
if( ir[15:0] == 16'b0100 1110 0111 0011 || ir[15:0] == 16'b0100 1110 0111 0111 )
795 
    RTE,RTR
796 
+++
797 
    load (ea) to operand1: (SP)
798 
 
799 
    perform ALU operation:
800 
    if(ir[2] == 1'b0) move operand1 to SR
801 
    else if(ir[2] == 1'b1) move operand1 to CCR
802 
 
803 
    SP += 2
804 
 
805 
    load (ea) to operand1: (SP)
806 
    move operand1 to result
807 
    move result to PC
808 
 
809 
    SP += 4
810 
 
811 
if( ir[15:0] == 16'b0100 1110 0111 0101 )
812 
    RTS
813 
+++
814 
    load (ea) to operand1: (SP)
815 
    move operand1 to result
816 
    move result to PC
817 
 
818 
    SP += 4
819 
 
820 
if( ir[15:6] == 10'b0100 1110 11 )
821 
    JMP
822 
+++
823 
    load (ea) from ir[5:0] to operand1: control
824 
        control:                                         (An) 010,                       (d16, An) 101, (d8, An, Xn) 110,
825 
                                (xxx).W 111 000, (xxx).L 111 001,         (d16, PC) 111 010, (d8, PC, Xn) 111 011
826 
 
827 
    perform ALU operation: move operand1 to result
828 
 
829 
    copy result register to PC
830 
 
831 
    CC: not affected
832 
 
833 
if( ir[15:6] == 10'b0100 1110 10 )
834 
    JSR
835 
+++
836 
    SP -= 4
837 
 
838 
    move PC to operand1
839 
    move operand1 to result
840 
    save result to (ea): (SP)
841 
 
842 
    load (ea) from ir[5:0] to operand1: control
843 
        control:                                         (An) 010,                       (d16, An) 101, (d8, An, Xn) 110,
844 
                                (xxx).W 111 000, (xxx).L 111 001,         (d16, PC) 111 010, (d8, PC, Xn) 111 011
845 
 
846 
    perform ALU operation: move operand1 to result
847 
 
848 
    copy result register to PC
849 
 
850 
    CC: not affected
851 
 
852 
if( ir[15:3] == 13'b0100 1110 0101 0 )
853 
    LINK
854 
+++
855 
    SP -= 4
856 
 
857 
    load (ea) from ir[2:0] to operand1: An
858 
 
859 
    perform ALU operation: move operand1 to result
860 
 
861 
    save result to (ea): (SP)
862 
 
863 
    load (ea) to operand1: SP
864 
    move operand1 to result
865 
 
866 
    save result to (ea) from ir[2:0]: An
867 
 
868 
    add to SP: ir1[15:0]
869 
 
870 
    CC: not affected
871 
 
872 
    update PC
873 
 
874 
if( ir[15:3] == 13'b0100 1110 0101 1 )
875 
    ULNK
876 
+++
877 
    load (ea) from ir[2:0] to operand1: An
878 
 
879 
    perform ALU operation: move operand1 to result
880 
 
881 
    save result to (ea): SP
882 
 
883 
    load ea to operand1: (SP)
884 
    move operand1 to result
885 
 
886 
    save result to (ea) from ir[2:0]: An
887 
 
888 
    SP += 4
889 
 
890 
    CC: not affected
891 
 
892 
    update PC
893 
 
894 
if( ir[15:8] == 8'b0100 1010 && ir[7:6] != 2'b11 )
895 
    TST
896 
+++
897 
    ea operation size:
898 
    if( ir[7:6] == 2'b00 ) byte
899 
    else if( ir[7:6] == 2'b01 ) word
900 
    else if( ir[7:6] == 2'b10 ) long
901 
 
902 
    load (ea) from ir[5:0] to operand1: data alter
903 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
904 
                                (xxx).W 111 000, (xxx).L 111 001,
905 
 
906 
    perform ALU TST operation: set CC
907 
 
908 
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared
909 
 
910 
    update PC
911 
 
912 
if( ir[15:6] == 10'b0100 1010 11 && ir[5:0] != 6'b111000 )
913 
    TAS
914 
+++
915 
    ea operation size: byte
916 
 
917 
    enable READ-MODIFY-WRITE bus cycle
918 
 
919 
    load (ea) from ir[5:0] to operand1: data alter
920 
        data alter:                Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
921 
                                (xxx).W 111 000, (xxx).L 111 001,
922 
 
923 
    perform ALU TAS operation: set bit 7 in result register
924 
 
925 
    CC: X not affected; C cleared; V cleared; Z set if zero else cleared; N set if MSB bit set else cleared
926 
 
927 
    save result to (ea) from ir[5:0]: data alter
928 
 
929 
    disable READ-MODIFY-WRITE bus cycle
930 
 
931 
    update PC
932 
 
933 
if( ir[15:12] == 4'b0100 && ir[8:6] == 3'b110 )
934 
    CHK
935 
+++
936 
    load (ea) from ir[5:0] to operand1: data
937 
        data:                     Dn 000,                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
938 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
939 
 
940 
    move operand1 to operand2
941 
 
942 
    load (ea) from ir[11:9] to operand1: Dn
943 
 
944 
 
945 
    ALU operation size: word
946 
 
947 
    perform ALU CHK operation: operand1 < 0 or operand1 - operand2 > 0
948 
 
949 
    CC: X not affected; N set if operand1 < 0; cleared if operand1 - operand2 > 0 else undefined; C,V,Z udefined
950 
 
951 
    if( ALU check ) trap CHK
952 
 
953 
    update PC
954 
 
955 
if( ir[15:12] == 4'b0100 && ir[8:6] == 3'b111 )
956 
    LEA
957 
+++
958 
    load ea from ir[5:0] to address register: control
959 
        control:                                     (An) 010,                       (d16, An) 101, (d8, An, Xn) 110,
960 
                                (xxx).W 111 000, (xxx).L 111 001,         (d16, PC) 111 010, (d8, PC, Xn) 111 011
961 
 
962 
    move address register to operand1
963 
    perform ALU operation: move operand1 to result register
964 
 
965 
    save result to (ea) from ir[11:9]: An
966 
 
967 
    CC: not affected
968 
 
969 
    update PC
970 
 
971 
if( ir[15:6] == 10'b0100 1000 01 && ir[5:3] != 3'b000 )
972 
    PEA
973 
+++
974 
    load ea from ir[5:0] to address register: control
975 
        control:                                     (An) 010,                       (d16, An) 101, (d8, An, Xn) 110,
976 
                                (xxx).W 111 000, (xxx).L 111 001,         (d16, PC) 111 010, (d8, PC, Xn) 111 011
977 
 
978 
    SP -= 4
979 
 
980 
    move address register to operand1
981 
    move operand1 to result
982 
 
983 
    save result to (ea): (SP)
984 
 
985 
    CC: not affected
986 
 
987 
    update PC
988 
 
989 
if( ir[15:6] == 10'b0100 0100 11 || ir[15:6] == 10'b0100 0110 11 )
990 
    MOVE TO CCR, MOVE TO SR
991 
+++
992 
    ea operation size: word
993 
 
994 
    load (ea) from ir[5:0] to operand1: data
995 
        data:                    Dn 000,                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
996 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
997 
 
998 
    if( ir[11:8] == 4'b0110 /MOVE TO SR/ )
999 
        copy word form operand1 register to SR
1000 
    else
1001 
        copy lower byte form operand1 register to CCR
1002 
 
1003 
    update PC
1004 
 
1005 
if( ir[15:6] == 10'b0100 0000 11 )
1006 
    MOVE FROM SR
1007 
+++
1008 
    copy SR register to result register
1009 
 
1010 
    ea operation size: word
1011 
 
1012 
    save result to (ea) from ir[5:0]: data alter
1013 
        data alter:            Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1014 
                            (xxx).W 111 000, (xxx).L 111 001,
1015 
 
1016 
    CC: not affected
1017 
 
1018 
    update PC
1019 
 
1020 
if( ir[15:3] == 12'b0100 1110 0110 0 )
1021 
    MOVE USP to USP
1022 
+++
1023 
    load (ea) from ir[2:0] to operand1: An
1024 
 
1025 
    perform ALU operation: move operand1 to result
1026 
 
1027 
    move result to USP
1028 
 
1029 
    CC: not affected
1030 
 
1031 
    update PC
1032 
 
1033 
if( ir[15:3] == 13'b0100 1110 0110 1 )
1034 
    MOVE USP to An
1035 
+++
1036 
    move USP to operand1
1037 
 
1038 
    perform ALU operation: move operand1 to result
1039 
 
1040 
    save result to (ea) from ir[2:0]: An
1041 
 
1042 
    CC: not affected
1043 
 
1044 
    update PC
1045 
 
1046 
if( ir[15:12] == 4'b0100 && ( (ir[11:8] == 4'b0000 && ir[7:6] != 2'b11) || (ir[11:8] == 4'b0010) || (ir[11:8] == 4'b0100 && ir[7:6] != 2'b11) ||
1047 
    (ir[11:8] == 4'b0110 && ir[7:6] != 2'b11) || (ir[11:6] == 6'b1000 00) ) )
1048 
+++
1049 
    NEGX,CLR,NEG,NOT,NBCD
1050 
 
1051 
    load (ea) from ir[5:0] to operand1: data alter
1052 
    data alter:                    Dn 000,                 (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1053 
                                (xxx).W 111 000, (xxx).L 111 001
1054 
 
1055 
    ALU operation size:
1056 
    NEGX:    ir[7:6]: 00,01,10 byte,word,long
1057 
    CLR:    ir[7:6]: 00,01,10 byte,word,long
1058 
    NEG:    ir[7:6]: 00,01,10 byte,word,long
1059 
    NOT:    ir[7:6]: 00,01,10 byte,word,long
1060 
    NBCD:    ir[7:6]: 00 byte
1061 
 
1062 
    perform ALU operation:
1063 
    NEGX:    ir[11:8] == 4'b0000
1064 
    CLR:    ir[11:8] == 4'b0010
1065 
    NEG:    ir[11:8] == 4'b0100
1066 
    NOT:    ir[11:8] == 4'b0110
1067 
    NBCD:    ir[11:6] == 6'b1000 00
1068 
 
1069 
    CC:
1070 
    NEGX:    X=C set if borrow else clear; V set if overflow else clear; Z cleared if nonzero else unchanged; N set if negative else clear
1071 
    CLR:    X not affected; C cleared; V cleared; Z set; N cleared
1072 
    NEG:    X=C clear if zero else set; V set if overflow else clear; Z set if zero else clear; N set if negative else clear
1073 
    NOT:    X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
1074 
    NBCD:    X=C set if decimal borrow else cleared; Z cleared if nonzero else unchanged; N,V undefined
1075 
 
1076 
    save result to (ea) from ir[5:0]: data alter
1077 
 
1078 
    update PC
1079 
 
1080 
if( ir[15:12] == 4'b0100 && (ir[11:3] == 9'b1000 01 000 || (ir[11:7] == 5'b1000 1 && ir[5:3] == 3'b000) )
1081 
    SWAP,EXT
1082 
+++
1083 
    load (ea) from ir[5:0] to operand1: Dn
1084 
 
1085 
    ALU operation size: word
1086 
    SWAP:     ir[7:6]: 01 long
1087 
    EXT:    ir[7:6]: 10,11 byte to word, word to long
1088 
 
1089 
    perform ALU operation:
1090 
    SWAP:     ir[11:6] == 6'b1000 01
1091 
    EXT:    ir[11:7] == 5'b1000 1
1092 
 
1093 
    CC:
1094 
    SWAP:    X not affected; C cleared; V cleared; Z set if 32 bits are zero else cleared; N set if result MSB set else cleared
1095 
    EXT:    X not affected; C cleared; V cleared; Z set if zero else cleared; N set if negative else cleared
1096 
 
1097 
    save result to (ea) from ir[5:0]: Dn
1098 
 
1099 
    update PC
1100 
 
1101 
if( ir[15:7] == 9'b0100 1100 1 && ir[5:3] != 3'b000 )
1102 
    MOVEM memory to register
1103 
+++
1104 
    operation size:
1105 
    if( ir[6] == 1'b0 ) word
1106 
    else if ir[6] == 1'b1 ) long
1107 
 
1108 
    load ea from ir[5:0] to address register: control or postincrement
1109 
                                                (An) 010, (An)+ 011,            (d16, An) 101, (d8, An, Xn) 110,
1110 
                                (xxx).W 111 000, (xxx).L 111 001,                (d16, PC) 111 010, (d8, PC, Xn) 111 011
1111 
 
1112 
    register selection order: D0,D1,...D7,A0,A1,...,A7
1113 
 
1114 
    do
1115 
        if( ir1[0] == 1'b1 )
1116 
            read from (ea) to operand1
1117 
 
1118 
            perform ALU operation: move operand1 with sign-extension to result
1119 
 
1120 
            save result to selected register
1121 
 
1122 
            update address register
1123 
 
1124 
        shift ir1
1125 
    loop 16 times
1126 
 
1127 
    if( ir[5:3] == 3'b011 ) save address register back to An indexed by ir[2:0]
1128 
 
1129 
    CC: not affected
1130 
 
1131 
    update PC
1132 
 
1133 
if( ir[15:7] == 9'b0100 1000 1 && ir[5:3] == 3'b100 )
1134 
    MOVEM register to memory, predecrement
1135 
+++
1136 
    operation size:
1137 
    if( ir[6] == 1'b0 ) word
1138 
    else if ir[6] == 1'b1 ) long
1139 
 
1140 
    load ea from ir[5:0] to address register: control alter or predecrement
1141 
                                        (An) 010,            -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1142 
                                (xxx).W 111 000, (xxx).L 111 001,
1143 
 
1144 
    register selection order: A7,A6,..A0,D7,D6,....D0
1145 
 
1146 
    do
1147 
        if( ir1[0] == 1'b1 )
1148 
            save selected register to operand1
1149 
 
1150 
            perform ALU operation: move operand1 to result
1151 
 
1152 
            save result to (ea)
1153 
 
1154 
            update address register
1155 
 
1156 
        shift ir1
1157 
    loop 16 times
1158 
 
1159 
    if( ir[5:3] == 3'b100 ) save address register back to An indexed by ir[2:0]
1160 
 
1161 
    CC: not affected
1162 
 
1163 
    update PC
1164 
 
1165 
if( ir[15:7] == 9'b0100 1000 1 && ir[5:3] != 3'b000 && ir[5:3] != 3b100 )
1166 
    MOVEM register to memory, control
1167 
+++
1168 
    operation size:
1169 
    if( ir[6] == 1'b0 ) word
1170 
    else if ir[6] == 1'b1 ) long
1171 
 
1172 
    load ea from ir[5:0] to address register: control alter or predecrement
1173 
                                        (An) 010,            -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1174 
                                (xxx).W 111 000, (xxx).L 111 001,
1175 
 
1176 
    register selection order: D0,D1,...D7,A0,A1,...,A7
1177 
 
1178 
    do
1179 
        if( ir1[0] == 1'b1 )
1180 
            save selected register to operand1
1181 
 
1182 
            perform ALU operation: move operand1 to result
1183 
 
1184 
            save result to (ea)
1185 
 
1186 
            update address register
1187 
 
1188 
        shift ir1
1189 
    loop 16 times
1190 
 
1191 
    CC: not affected
1192 
 
1193 
    update PC
1194 
 
1195 
*/
1196 
 
1197 
/*
1198 
 
1199 
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
1200 
microinstructions
1201 
 
1202 
MOVE_ea_reg_TO_An_address
1203 
MOVE_ea_reg_TO_Dn_address
1204 
MOVE_ir1_brief_ext_TO_An_Dn_addresses        // ir_valid
1205 
MOVE_An_output_TO_address
1206 
MOVE_Dn_output_TO_OP1
1207 
MOVE_An_output_TO_OP1
1208 
MOVE_zeros_TO_index
1209 
MOVE_ir1_brief_ext_TO_index                    // ir_valid
1210 
MOVE_ir1_byte_TO_offset                        // ir_valid
1211 
MOVE_ir1_word_TO_offset                        // ir_valid
1212 
MOVE_base_index_offset_TO_address
1213 
MOVE_ir1_absolute_word_TO_address            // ir_valid
1214 
MOVE_ir1_ir2_absolute_long_TO_address        // ir_valid
1215 
MOVE_pc_index_offset_TO_address
1216 
MOVE_trap_TO_address
1217 
MOVE_result_TO_An_input
1218 
MOVE_result_TO_Dn_input(size=)
1219 
MOVE_address_TO_An_input
1220 
MOVE_result_TO_data
1221 
 
1222 
MOVE_OP1_TO_OP2
1223 
MOVE_OP2_TO_OP1
1224 
MOVE_ADDR_TO_OP1
1225 
MOVE_data_TO_OP1
1226 
MOVE_immediate_TO_OP1(size=)
1227 
MOVE_result_TO_OP1
1228 
MOVE_moveq_TO_OP1
1229 
MOVE_PC_NEXT_TO_OP1
1230 
MOVE_zeros_TO_OP1
1231 
MOVE_ones_TO_OP1
1232 
MOVE_SR_TO_OP1
1233 
MOVE_USP_TO_OP1
1234 
MOVE_ir_TO_OP1
1235 
MOVE_address_bus_info_TO_OP2
1236 
MOVE_1_TO_OP2
1237 
MOVE_offset_TO_OP2
1238 
MOVE_count_TO_OP2
1239 
MOVE_addq_subq_TO_OP2
1240 
MOVE_result_TO_PC
1241 
MOVE_result_TO_USP
1242 
MOVE_zeros_TO_movem_mod_reg
1243 
MOVE_001111_TO_movem_mod_reg
1244 
MOVE_OP1_TO_movem_reg
1245 
MOVE_zeros_TO_movem_loop
1246 
MOVE_prefetch_ir_TO_ir
1247 
MOVE_interrupt_mask_TO_sr
1248 
MOVE_1_0_supervisor_trace_TO_sr
1249 
MOVE_reset_mask_TO_sr
1250 
MOVE_prefetch_ir_TO_PC
1251 
MOVE_prefetch_ir_TO_SSP
1252 
 
1253 
MOVE_illegal_instr_TO_TRAP
1254 
MOVE_divide_by_zero_TO_TRAP
1255 
MOVE_chk_TO_TRAP
1256 
MOVE_trapv_TO_TRAP
1257 
MOVE_priv_viol_TO_TRAP
1258 
MOVE_trap_TO_TRAP
1259 
MOVE_decoder_trap_TO_TRAP
1260 
MOVE_trace_TO_TRAP
1261 
MOVE_interrupt_trap_TO_TRAP
1262 
 
1263 
MOVE_0_TO_stop_flag
1264 
MOVE_1_TO_stop_flag
1265 
MOVE_sr15_TO_trace_flag
1266 
MOVE_0_TO_group_0_flag
1267 
MOVE_1_TO_group_0_flag
1268 
MOVE_0_TO_read_modify_write_flag
1269 
MOVE_1_TO_read_modify_write_flag
1270 
MOVE_0_TO_instruction_flag
1271 
MOVE_1_TO_instruction_flag
1272 
MOVE_1_TO_blocked_flag
1273 
MOVE_0_TO_read_flag
1274 
MOVE_1_To_read_flag
1275 
MOVE_0_TO_write_flag
1276 
MOVE_1_TO_write_flag
1277 
MOVE_0_TO_interrupt_flag
1278 
MOVE_1_TO_interrupt_flag
1279 
MOVE_1_TO_reset_flag
1280 
MOVE_0_TO_reset_flag
1281 
 
1282 
INCR_ADDR_BY_SIZE(size=)
1283 
DECR_ADDR_BY_SIZE(size=)
1284 
DECR_OP2_BY_1
1285 
CALL procedure
1286 
RETURN
1287 
INCR_movem_loop_BY_1
1288 
INCR_movem_mod_reg_BY_1
1289 
DECR_movem_mod_reg_BY_1
1290 
JMP: local label, trap, instr_fin, instr_fin_pc_loaded,
1291 
SHIFT_RIGHT_movem_reg
1292 
INCR_PC_BY_2
1293 
INCR_PC_BY_4
1294 
INCR_PC_BY_size(size=)
1295 
 
1296 
BRANCH(movem_loop == 4'b1000)
1297 
BRANCH(movem_reg[0] == 0)
1298 
BRANCH(operand2[5:0] == 6'b0)
1299 
BRANCH(special == 2'b01)
1300 
BRANCH(special == 2'b10)
1301 
BRANCH(condition == 1'b0)
1302 
BRANCH(condition == 1'b1)
1303 
BRANCH(result[15:0] == 16'hFFFF)
1304 
BRANCH(V == 1'b0)
1305 
BRANCH(stop_flag == 1'b1)
1306 
BRANCH(ir[7:0] != 8'b0)
1307 
BRANCH(decoder_trap == 8'b0)
1308 
BRANCH(trace_flag == 1'b0)
1309 
BRANCH(group_0_flag == 0)
1310 
 
1311 
WAIT_RESET, WAIT_MEMORY_READ(size, address), WAIT_MEMORY_WRITE(size, address, select), WAIT_interrupt, WAIT_blocked
1312 
WAIT_prefetch_ir_valid
1313 
 
1314 
subprocedures:
1315 
ea(size=, reg=, mod=, type=, select=)
1316 
 
1317 
LOAD_EA:             to address register
1318 
PERFORM_EA_READ:     to operand1
1319 
PERFORM_EA_WRITE:     from result
1320 
SAVE_EA
1321 
 
1322 
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
1323 
 
1324 
TYPE.ALL: all
1325 
                                Dn 000,    An (word, long) 001, (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1326 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
1327 
TYPE.CONTROL_POSTINC: control or postincrement
1328 
                                                             (An) 010, (An)+ 011,            (d16, An) 101, (d8, An, Xn) 110,
1329 
                                (xxx).W 111 000, (xxx).L 111 001,                (d16, PC) 111 010, (d8, PC, Xn) 111 011
1330 
TYPE.CONTROLALTER_PREDEC: control alter or predecrement
1331 
                                                              (An) 010,            -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1332 
                                (xxx).W 111 000, (xxx).L 111 001,
1333 
TYPE.CONTROL: control
1334 
                                                              (An) 010,                       (d16, An) 101, (d8, An, Xn) 110,
1335 
                                (xxx).W 111 000, (xxx).L 111 001,                  (d16, PC) 111 010, (d8, PC, Xn) 111 011
1336 
TYPE.DATAALTER: data alter
1337 
                                Dn 000,                      (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1338 
                                (xxx).W 111 000, (xxx).L 111 001,
1339 
TYPE.DN_AN: Dn, An
1340 
                                Dn 000, An 001
1341 
TYPE.MEMORYALTER: memory alter
1342 
                                                              (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1343 
                                (xxx).W 111 000, (xxx).L 111 001
1344 
TYPE.DATA: data
1345 
                                Dn 000,                         (An) 010, (An)+ 011, -(An) 100, (d16, An) 101, (d8, An, Xn) 110,
1346 
                                (xxx).W 111 000, (xxx).L 111 001, #data 111 100, (d16, PC) 111 010, (d8, PC, Xn) 111 011
1347 
 
1348 
 

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