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alfik |
/*
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* Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are
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* permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice, this list
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* of conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*! \file ao68000.v
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* \brief Main ao68000 IP Core source file.
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*/
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/***********************************************************************************************************************
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* Definitions of microcode operations - parsed by ao68000_tool to generate the defines in the section below
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**********************************************************************************************************************/
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// OPERATIONS START
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`define EA_REG_IDLE 3'd0
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`define EA_REG_IR_2_0 3'd1
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`define EA_REG_IR_11_9 3'd2
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`define EA_REG_MOVEM_REG_2_0 3'd3
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`define EA_REG_3b111 3'd4
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`define EA_REG_3b100 3'd5
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`define EA_MOD_IDLE 4'd0
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`define EA_MOD_IR_5_3 4'd1
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`define EA_MOD_MOVEM_MOD_5_3 4'd2
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`define EA_MOD_IR_8_6 4'd3
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`define EA_MOD_PREDEC 4'd4 // predecrement: -(An)
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`define EA_MOD_3b111 4'd5 // extended mod
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`define EA_MOD_DN_PREDEC 4'd6 // MOD.DN_PREDEC: Dn 3'b000 (ir[3] == 1'b0), -(An) 3'b100 (ir[3] == 1'b1)
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`define EA_MOD_DN_AN_EXG 4'd7 // MOD.DN_AN_EXG: Dn 3'b000 (ir[7:3] == 5'b01000 or 5'b10001), An 3'b001 (ir[7:3] == 5'b01001)
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`define EA_MOD_POSTINC 4'd8 // MOD.POSTINC: postincrement (An)+ 3'b011
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`define EA_MOD_AN 4'd9 // MOD.AN: An 3'b001, saved result is sign-extended
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`define EA_MOD_DN 4'd10 // MOD.DN: Dn 3'b000
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`define EA_MOD_INDIRECTOFFSET 4'd11 // MOD.INDIRECTOFFSET: (d16, An) 3'b101
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`define EA_TYPE_IDLE 4'd0
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`define EA_TYPE_ALL 4'd1 // TYPE.ALL: all
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`define EA_TYPE_CONTROL_POSTINC 4'd2 // TYPE.CONTROL_POSTINC: control or postincrement
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`define EA_TYPE_CONTROLALTER_PREDEC 4'd3 // TYPE.CONTROLALTER_PREDEC: control alter or predecrement
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`define EA_TYPE_CONTROL 4'd4 // TYPE.CONTROL: control
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`define EA_TYPE_DATAALTER 4'd5 // TYPE.DATAALTER: data alter
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`define EA_TYPE_DN_AN 4'd6 // TYPE.DN_AN: Dn, An
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`define EA_TYPE_MEMORYALTER 4'd7 // TYPE.MEMORYALTER: memory alter
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`define EA_TYPE_DATA 4'd8 // TYPE.DATA: data
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`define OP1_IDLE 4'd0
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`define OP1_FROM_OP2 4'd1 // move from operand2
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`define OP1_FROM_ADDRESS 4'd2 // move from address
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`define OP1_FROM_DATA 4'd3 // move from data, sign extend
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`define OP1_FROM_IMMEDIATE 4'd4 // move immediate, sign extend
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`define OP1_FROM_RESULT 4'd5 // move from result
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`define OP1_MOVEQ 4'd6 // move moveq: { 24{ir[7]}, ir[7:0] }
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`define OP1_FROM_PC 4'd7 // move from PC
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`define OP1_LOAD_ZEROS 4'd8 // load zeros: 32'b0
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`define OP1_LOAD_ONES 4'd9 // load ones: 32'hFFFFFFFF
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`define OP1_FROM_SR 4'd10 // move from SR
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`define OP1_FROM_USP 4'd11 // move from USP
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`define OP1_FROM_AN 4'd12 // move from An, 32 bits
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`define OP1_FROM_DN 4'd13 // move from Dn, sign extend
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`define OP1_FROM_IR 4'd14 // move from ir[15:0]
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`define OP1_FROM_FAULT_ADDRESS 4'd15 // move from fault_address
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`define OP2_IDLE 3'd0
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`define OP2_FROM_OP1 3'd1 // move from operand1
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`define OP2_LOAD_1 3'd2 // load: 32'b1
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`define OP2_LOAD_COUNT 3'd3 // load count
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`define OP2_ADDQ_SUBQ 3'd4 // load addq_subq
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`define OP2_MOVE_OFFSET 3'd5 // move offset
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`define OP2_MOVE_ADDRESS_BUS_INFO 3'd6 // move address_bus_info
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`define OP2_DECR_BY_1 3'd7 // decrement by 1
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`define ADDRESS_IDLE 4'd0
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`define ADDRESS_INCR_BY_SIZE 4'd1 // increment by size
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`define ADDRESS_DECR_BY_SIZE 4'd2 // decrement by size
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`define ADDRESS_INCR_BY_2 4'd3 // increment by 2
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`define ADDRESS_FROM_AN_OUTPUT 4'd4 // move from An output
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`define ADDRESS_FROM_BASE_INDEX_OFFSET 4'd5 // move from base+index+offset
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`define ADDRESS_FROM_IMM_16 4'd6 // move from {16{ir1[15]}, ir1[15:0]}
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`define ADDRESS_FROM_IMM_32 4'd7 // move from {ir1[15:0], ir2[15:0]}
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`define ADDRESS_FROM_PC_INDEX_OFFSET 4'd8 // move from pc+index+offset
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`define ADDRESS_FROM_TRAP 4'd9 // move trap {22'b0, trap[7:0], 2'b0}
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`define SIZE_IDLE 4'd0
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`define SIZE_BYTE 4'd1 // load byte: 2'b00
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`define SIZE_WORD 4'd2 // load word: 2'b01
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`define SIZE_LONG 4'd3 // load long: 2'b10
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`define SIZE_1 4'd4 // SIZE.1: word ( ir[7:6] == 2'b00 ), long ( ir[7:6] == 2'b01 )
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`define SIZE_1_PLUS 4'd5 // SIZE.1+: word ( ir[7:6] == 2'b10 ), long ( ir[7:6] == 2'b11 )
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`define SIZE_2 4'd6 // SIZE.2: word ( ir[6] == 1'b0 ), long ( ir[6] == 1'b1 )
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`define SIZE_3 4'd7 // SIZE.3: byte ( ir[7:6] == 2'b00 ), word ( ir[7:6] == 2'b01 ), long ( ir[7:6] == 2'b10 )
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`define SIZE_4 4'd8 // SIZE.4: byte ( ir[13:12] == 2'b01 ), word( ir[13:12] == 2'b11 ), long ( ir[13:12] == 2'b10 )
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`define SIZE_5 4'd9 // SIZE.5: word ( ir[8] == 1'b0 ), long ( ir[8] == 1'b1 )
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`define SIZE_6 4'd10 // SIZE.6: byte ( ir[5:3] != 3'b000 ), long ( ir[5:3] == 3'b000 )
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`define MOVEM_MODREG_IDLE 3'd0
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`define MOVEM_MODREG_LOAD_0 3'd1 // load 6'b0
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`define MOVEM_MODREG_LOAD_6b001111 3'd2 // load 6'b001111
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`define MOVEM_MODREG_INCR_BY_1 3'd3 // increment by 1
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`define MOVEM_MODREG_DECR_BY_1 3'd4 // decrement by 1
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`define MOVEM_LOOP_IDLE 2'd0
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`define MOVEM_LOOP_LOAD_0 2'd1 // load 4'b0
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`define MOVEM_LOOP_INCR_BY_1 2'd2 // increment by 1
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`define MOVEM_REG_IDLE 2'd0
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`define MOVEM_REG_FROM_OP1 2'd1 // load from operand1[15:0]
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`define MOVEM_REG_SHIFT_RIGHT 2'd2 // shift right
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`define IR_IDLE 2'd0
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`define IR_LOAD_WHEN_PREFETCH_VALID 2'd1 // load from prefetch_ir[79:64]
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`define PC_IDLE 3'd0
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`define PC_FROM_RESULT 3'd1 // move from result
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`define PC_INCR_BY_2 3'd2 // increment by 2
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`define PC_INCR_BY_4 3'd3 // increment by 4
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`define PC_INCR_BY_SIZE 3'd4 // increment by size: 2 (size == 2'b00 || size == 2'b01), 4 (size == 2'b10)
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`define PC_FROM_PREFETCH_IR 3'd5 // move from prefetch_ir
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`define PC_INCR_BY_2_IN_MAIN_LOOP 3'd6 // increment by 2, in main loop, when valid prefetch and valid instruction
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`define TRAP_IDLE 4'd0
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`define TRAP_ILLEGAL_INSTR 4'd1 // move illegal_instr: 8'd4
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`define TRAP_DIV_BY_ZERO 4'd2 // move divide_by_zero: 8'd5
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`define TRAP_CHK 4'd3 // move chk: 8'd6
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`define TRAP_TRAPV 4'd4 // move trapv: 8'd7
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`define TRAP_PRIVIL_VIOLAT 4'd5 // move priv_viol: 8'd8
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`define TRAP_TRACE 4'd6 // move trace: 8'd9
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`define TRAP_TRAP 4'd7 // move trap: { 3'b0, 1'b1, ir[3:0] }
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`define TRAP_FROM_DECODER 4'd8 // move from decoder_trap
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`define TRAP_FROM_INTERRUPT 4'd9 // move from interrupt_trap
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`define OFFSET_IDLE 2'd0
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`define OFFSET_IMM_8 2'd1 // { 24{ir1[7]}, ir1[7:0] }
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`define OFFSET_IMM_16 2'd2 // { 16{ir1[15]}, ir1[15:0] }
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`define INDEX_IDLE 2'd0
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`define INDEX_0 2'd1 // 32'b0
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`define INDEX_LOAD_EXTENDED 2'd2 // load from extended instruction word
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`define STOP_FLAG_IDLE 2'd0
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`define STOP_FLAG_SET 2'd1 // set, continue when: trace,interrupt or reset
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`define STOP_FLAG_CLEAR 2'd2 // clear
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`define TRACE_FLAG_IDLE 2'd0
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`define TRACE_FLAG_COPY_WHEN_NO_STOP 2'd1 // remember trace bit, move from sr[15]
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`define GROUP_0_FLAG_IDLE 2'd0
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`define GROUP_0_FLAG_SET 2'd1 // set, processing group zero exception
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`define GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH 2'd2 // clear
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`define INSTRUCTION_FLAG_IDLE 2'd0
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`define INSTRUCTION_FLAG_SET 2'd1 // set, processing instruction
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`define INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP 2'd2 // clear, in main loop, when valid prefetch and valid instruction
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`define READ_MODIFY_WRITE_FLAG_IDLE 2'd0
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`define READ_MODIFY_WRITE_FLAG_SET 2'd1 // set, execute a RMW cycle
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`define READ_MODIFY_WRITE_FLAG_CLEAR 2'd2 // clear
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`define DO_RESET_FLAG_IDLE 2'd0
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`define DO_RESET_FLAG_SET 2'd1 // set, signal reset
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`define DO_RESET_FLAG_CLEAR 2'd2 // clear
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`define DO_INTERRUPT_FLAG_IDLE 2'd0
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`define DO_INTERRUPT_FLAG_SET_IF_ACTIVE 2'd1 // set if interrupt active
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`define DO_INTERRUPT_FLAG_CLEAR 2'd2 // clear
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`define DO_READ_FLAG_IDLE 2'd0
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`define DO_READ_FLAG_SET 2'd1 // set, perform read operation
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`define DO_READ_FLAG_CLEAR 2'd2 // clear
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`define DO_WRITE_FLAG_IDLE 2'd0
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`define DO_WRITE_FLAG_SET 2'd1 // set, perform write operation
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`define DO_WRITE_FLAG_CLEAR 2'd2 // clear
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`define DO_BLOCKED_FLAG_IDLE 2'd0
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`define DO_BLOCKED_FLAG_SET 2'd1 // set, block processor
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`define DATA_WRITE_IDLE 2'd0
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`define DATA_WRITE_FROM_RESULT 2'd1 // load data write register from result register
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`define AN_ADDRESS_IDLE 2'd0 // load from ea_reg, user or supervisor
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`define AN_ADDRESS_FROM_EXTENDED 2'd1 // load from extended instruction word: ir1[14:12], user or supervisor
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`define AN_ADDRESS_USP 2'd2 // load USP address
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`define AN_ADDRESS_SSP 2'd3 // load SSP address
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`define AN_WRITE_ENABLE_IDLE 1'd0
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`define AN_WRITE_ENABLE_SET 1'd1 // set write enable on An register
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`define AN_INPUT_IDLE 2'd0 // load from result
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`define AN_INPUT_FROM_ADDRESS 2'd1 // load from address
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`define AN_INPUT_FROM_PREFETCH_IR 2'd2 // load from prefetch_ir, for reset, for SSP
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`define DN_ADDRESS_IDLE 1'd0 // load from ea_reg
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`define DN_ADDRESS_FROM_EXTENDED 1'd1 // load from extended instruction word: ir1[14:12]
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`define DN_WRITE_ENABLE_IDLE 1'd0
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`define DN_WRITE_ENABLE_SET 1'd1 // set write enable on Dn register
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`define ALU_IDLE 5'd0
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`define ALU_SR_SET_INTERRUPT 5'd1
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`define ALU_SR_SET_TRAP 5'd2
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`define ALU_MOVEP_M2R_1 5'd3
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`define ALU_MOVEP_M2R_2 5'd4
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`define ALU_MOVEP_M2R_3 5'd5
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`define ALU_MOVEP_M2R_4 5'd6
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`define ALU_MOVEP_R2M_1 5'd7
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`define ALU_MOVEP_R2M_2 5'd8
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`define ALU_MOVEP_R2M_3 5'd9
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`define ALU_MOVEP_R2M_4 5'd10
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`define ALU_SIGN_EXTEND 5'd11
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`define ALU_ARITHMETIC_LOGIC 5'd12
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`define ALU_ABCD_SBCD_ADDX_SUBX 5'd13
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`define ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare 5'd14
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`define ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR 5'd15
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`define ALU_MOVE 5'd16
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`define ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ 5'd17
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`define ALU_CHK 5'd18
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`define ALU_MULS_MULU_DIVS_DIVU 5'd19
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`define ALU_BCHG_BCLR_BSET_BTST 5'd20
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`define ALU_TAS 5'd21
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`define ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT 5'd22
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`define ALU_SIMPLE_LONG_ADD 5'd23
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`define ALU_SIMPLE_LONG_SUB 5'd24
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`define ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR 5'd25
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`define ALU_SIMPLE_MOVE 5'd26
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`define ALU_LINK_MOVE 5'd27
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`define BRANCH_IDLE 4'd0
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`define BRANCH_movem_loop 4'd1 // BRANCH(movem_loop == 4'b1000)
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`define BRANCH_movem_reg 4'd2 // BRANCH(movem_reg[0] == 0)
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`define BRANCH_operand2 4'd3 // BRANCH(operand2[5:0] == 6'b0)
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`define BRANCH_special_01 4'd4 // BRANCH(special != 2'b01)
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`define BRANCH_special_10 4'd5 // BRANCH(special == 2'b10)
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`define BRANCH_condition_0 4'd6 // BRANCH(condition == 1'b0)
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`define BRANCH_condition_1 4'd7 // BRANCH(condition == 1'b1)
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`define BRANCH_result 4'd8 // BRANCH(result[15:0] == 16'hFFFF)
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`define BRANCH_V 4'd9 // BRANCH(V == 1'b0)
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| 254 |
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|
`define BRANCH_movep_16 4'd10 // BRANCH(ir[6] == 0)
|
| 255 |
|
|
`define BRANCH_stop_flag_wait_ir_decode 4'd11 // BRANCH(stop_flag == 1'b1) if no branch: wait for prefetch ir valid and decode instruction
|
| 256 |
|
|
`define BRANCH_ir 4'd12 // BRANCH(ir[7:0] != 8'b0)
|
| 257 |
|
|
`define BRANCH_trace_flag_and_interrupt 4'd13 // BRANCH(trace_flag == 1'b0 && interrupt_mask != 3'b000) if no branch: jump to main loop
|
| 258 |
|
|
`define BRANCH_group_0_flag 4'd14 // BRANCH(group_0_flag == 0)
|
| 259 |
|
|
`define BRANCH_procedure 4'd15 // call procedure, return from procedure
|
| 260 |
|
|
|
| 261 |
|
|
`define PROCEDURE_IDLE 4'd0
|
| 262 |
|
|
`define PROCEDURE_call_load_ea 4'd1 // load ea
|
| 263 |
|
|
`define PROCEDURE_call_perform_ea_read 4'd2 // perform_ea_read
|
| 264 |
|
|
`define PROCEDURE_call_perform_ea_write 4'd3 // perform_ea_write
|
| 265 |
|
|
`define PROCEDURE_call_save_ea 4'd4 // save ea
|
| 266 |
|
|
`define PROCEDURE_return 4'd5 // return from procedure
|
| 267 |
|
|
`define PROCEDURE_wait_finished 4'd6 // wait for finished signal from bus controler
|
| 268 |
|
|
`define PROCEDURE_wait_prefetch_valid 4'd7 // wait for prefetch ir valid, 64 bits
|
| 269 |
|
|
`define PROCEDURE_wait_prefetch_valid_32 4'd8 // wait for prefetch ir valid, 32 bits
|
| 270 |
|
|
`define PROCEDURE_jump_to_main_loop 4'd9 // jump to main loop
|
| 271 |
|
|
`define PROCEDURE_push_micropc 4'd10 // save current micro_pc
|
| 272 |
|
|
`define PROCEDURE_call_trap 4'd11 // call trap service procedure
|
| 273 |
|
|
`define PROCEDURE_pop_micropc 4'd12 // pop most recent micro_pc and forget
|
| 274 |
|
|
`define PROCEDURE_interrupt_mask 4'd13 // if interrupt active continue, else jump to main loop
|
| 275 |
|
|
`define PROCEDURE_call_read 4'd14 // load_ea + perform_ea_read
|
| 276 |
|
|
`define PROCEDURE_call_write 4'd15 // perform_ea_write + save_ea + return
|
| 277 |
|
|
// OPERATIONS END
|
| 278 |
|
|
|
| 279 |
|
|
/***********************************************************************************************************************
|
| 280 |
|
|
* Automatically generated by ao68000_tool microcode word bit assignments and addresses
|
| 281 |
|
|
**********************************************************************************************************************/
|
| 282 |
|
|
// MICROCODE - DO NOT EDIT BELOW
|
| 283 |
|
|
`define MICRO_DATA_ea_reg micro_data[2:0]
|
| 284 |
|
|
`define MICRO_DATA_ea_mod micro_data[6:3]
|
| 285 |
|
|
`define MICRO_DATA_ea_type micro_data[10:7]
|
| 286 |
|
|
`define MICRO_DATA_op1 micro_data[14:11]
|
| 287 |
|
|
`define MICRO_DATA_op2 micro_data[17:15]
|
| 288 |
|
|
`define MICRO_DATA_address micro_data[21:18]
|
| 289 |
|
|
`define MICRO_DATA_size micro_data[25:22]
|
| 290 |
|
|
`define MICRO_DATA_movem_modreg micro_data[28:26]
|
| 291 |
|
|
`define MICRO_DATA_movem_loop micro_data[30:29]
|
| 292 |
|
|
`define MICRO_DATA_movem_reg micro_data[32:31]
|
| 293 |
|
|
`define MICRO_DATA_ir micro_data[34:33]
|
| 294 |
|
|
`define MICRO_DATA_pc micro_data[37:35]
|
| 295 |
|
|
`define MICRO_DATA_trap micro_data[41:38]
|
| 296 |
|
|
`define MICRO_DATA_offset micro_data[43:42]
|
| 297 |
|
|
`define MICRO_DATA_index micro_data[45:44]
|
| 298 |
|
|
`define MICRO_DATA_stop_flag micro_data[47:46]
|
| 299 |
|
|
`define MICRO_DATA_trace_flag micro_data[49:48]
|
| 300 |
|
|
`define MICRO_DATA_group_0_flag micro_data[51:50]
|
| 301 |
|
|
`define MICRO_DATA_instruction_flag micro_data[53:52]
|
| 302 |
|
|
`define MICRO_DATA_read_modify_write_flag micro_data[55:54]
|
| 303 |
|
|
`define MICRO_DATA_do_reset_flag micro_data[57:56]
|
| 304 |
|
|
`define MICRO_DATA_do_interrupt_flag micro_data[59:58]
|
| 305 |
|
|
`define MICRO_DATA_do_read_flag micro_data[61:60]
|
| 306 |
|
|
`define MICRO_DATA_do_write_flag micro_data[63:62]
|
| 307 |
|
|
`define MICRO_DATA_do_blocked_flag micro_data[65:64]
|
| 308 |
|
|
`define MICRO_DATA_data_write micro_data[67:66]
|
| 309 |
|
|
`define MICRO_DATA_an_address micro_data[69:68]
|
| 310 |
|
|
`define MICRO_DATA_an_write_enable micro_data[70:70]
|
| 311 |
|
|
`define MICRO_DATA_an_input micro_data[72:71]
|
| 312 |
|
|
`define MICRO_DATA_dn_address micro_data[73:73]
|
| 313 |
|
|
`define MICRO_DATA_dn_write_enable micro_data[74:74]
|
| 314 |
|
|
`define MICRO_DATA_alu micro_data[79:75]
|
| 315 |
|
|
`define MICRO_DATA_branch micro_data[83:80]
|
| 316 |
|
|
`define MICRO_DATA_procedure micro_data[87:84]
|
| 317 |
|
|
|
| 318 |
|
|
`define MICROPC_MOVE 9'd231
|
| 319 |
|
|
`define MICROPC_MOVE_USP_to_An 9'd403
|
| 320 |
|
|
`define MICROPC_TAS 9'd335
|
| 321 |
|
|
`define MICROPC_BSR 9'd433
|
| 322 |
|
|
`define MICROPC_ADDRESS_BUS_TRAP 9'd3
|
| 323 |
|
|
`define MICROPC_MOVEP_register_to_memory 9'd106
|
| 324 |
|
|
`define MICROPC_NEGX_CLR_NEG_NOT_NBCD 9'd340
|
| 325 |
|
|
`define MICROPC_RTS 9'd474
|
| 326 |
|
|
`define MICROPC_MAIN_LOOP 9'd53
|
| 327 |
|
|
`define MICROPC_ADDA_SUBA 9'd268
|
| 328 |
|
|
`define MICROPC_MOVE_TO_CCR_MOVE_TO_SR 9'd394
|
| 329 |
|
|
`define MICROPC_MOVE_FROM_SR 9'd391
|
| 330 |
|
|
`define MICROPC_LOAD_EA_d8_PC_Xn 9'd79
|
| 331 |
|
|
`define MICROPC_TRAP_ENTRY 9'd35
|
| 332 |
|
|
`define MICROPC_PERFORM_EA_READ_memory 9'd89
|
| 333 |
|
|
`define MICROPC_RESET 9'd488
|
| 334 |
|
|
`define MICROPC_PERFORM_EA_WRITE_Dn 9'd91
|
| 335 |
|
|
`define MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_memory 9'd225
|
| 336 |
|
|
`define MICROPC_MOVEA 9'd239
|
| 337 |
|
|
`define MICROPC_TST 9'd347
|
| 338 |
|
|
`define MICROPC_BTST_register 9'd329
|
| 339 |
|
|
`define MICROPC_LOAD_EA_d8_An_Xn 9'd68
|
| 340 |
|
|
`define MICROPC_MULS_MULU_DIVS_DIVU 9'd290
|
| 341 |
|
|
`define MICROPC_MOVEQ 9'd310
|
| 342 |
|
|
`define MICROPC_CMPA 9'd275
|
| 343 |
|
|
`define MICROPC_EOR 9'd245
|
| 344 |
|
|
`define MICROPC_LOAD_EA_xxx_W 9'd72
|
| 345 |
|
|
`define MICROPC_DBcc 9'd377
|
| 346 |
|
|
`define MICROPC_CMPI 9'd184
|
| 347 |
|
|
`define MICROPC_LOAD_EA_xxx_L 9'd74
|
| 348 |
|
|
`define MICROPC_CMPM 9'd205
|
| 349 |
|
|
`define MICROPC_MOVE_USP_to_USP 9'd398
|
| 350 |
|
|
`define MICROPC_ADDQ_SUBQ_not_An 9'd351
|
| 351 |
|
|
`define MICROPC_ULNK 9'd422
|
| 352 |
|
|
`define MICROPC_EXG 9'd197
|
| 353 |
|
|
`define MICROPC_ADD_to_mem_SUB_to_mem_AND_to_mem_OR_to_mem 9'd250
|
| 354 |
|
|
`define MICROPC_Bcc_BRA 9'd365
|
| 355 |
|
|
`define MICROPC_PERFORM_EA_READ_An 9'd86
|
| 356 |
|
|
`define MICROPC_LOAD_EA_d16_PC 9'd76
|
| 357 |
|
|
`define MICROPC_NOP 9'd482
|
| 358 |
|
|
`define MICROPC_MOVEM_register_to_memory_predecrement 9'd131
|
| 359 |
|
|
`define MICROPC_RTE_RTR 9'd462
|
| 360 |
|
|
`define MICROPC_TRAP 9'd483
|
| 361 |
|
|
`define MICROPC_ADDQ_SUBQ_An 9'd354
|
| 362 |
|
|
`define MICROPC_MOVEM_register_to_memory_control 9'd147
|
| 363 |
|
|
`define MICROPC_BTST_immediate 9'd318
|
| 364 |
|
|
`define MICROPC_MOVEP_memory_to_register 9'd98
|
| 365 |
|
|
`define MICROPC_PERFORM_EA_WRITE_An 9'd92
|
| 366 |
|
|
`define MICROPC_CHK 9'd281
|
| 367 |
|
|
`define MICROPC_Scc 9'd358
|
| 368 |
|
|
`define MICROPC_JMP 9'd445
|
| 369 |
|
|
`define MICROPC_PEA 9'd168
|
| 370 |
|
|
`define MICROPC_SAVE_EA_minus_An 9'd97
|
| 371 |
|
|
`define MICROPC_ANDI_EORI_ORI_ADDI_SUBI 9'd174
|
| 372 |
|
|
`define MICROPC_BCHG_BCLR_BSET_immediate 9'd313
|
| 373 |
|
|
`define MICROPC_LOAD_EA_An 9'd62
|
| 374 |
|
|
`define MICROPC_PERFORM_EA_READ_imm 9'd87
|
| 375 |
|
|
`define MICROPC_ADD_to_Dn_SUB_to_Dn_AND_to_Dn_OR_to_Dn 9'd255
|
| 376 |
|
|
`define MICROPC_LEA 9'd162
|
| 377 |
|
|
`define MICROPC_TRAPV 9'd485
|
| 378 |
|
|
`define MICROPC_LINK 9'd406
|
| 379 |
|
|
`define MICROPC_ABCD_SBCD_ADDX_SUBX 9'd189
|
| 380 |
|
|
`define MICROPC_BCHG_BCLR_BSET_register 9'd324
|
| 381 |
|
|
`define MICROPC_PERFORM_EA_READ_Dn 9'd85
|
| 382 |
|
|
`define MICROPC_LOAD_EA_illegal_command 9'd83
|
| 383 |
|
|
`define MICROPC_ORI_to_CCR_ORI_to_SR_ANDI_to_CCR_ANDI_to_SR_EORI_to_CCR_EORI_to_SR 9'd178
|
| 384 |
|
|
`define MICROPC_CMP 9'd262
|
| 385 |
|
|
`define MICROPC_SWAP_EXT 9'd343
|
| 386 |
|
|
`define MICROPC_STOP 9'd491
|
| 387 |
|
|
`define MICROPC_PERFORM_EA_WRITE_memory 9'd93
|
| 388 |
|
|
`define MICROPC_JSR 9'd453
|
| 389 |
|
|
`define MICROPC_LOAD_EA_minus_An 9'd63
|
| 390 |
|
|
`define MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_immediate_register 9'd212
|
| 391 |
|
|
`define MICROPC_SAVE_EA_An_plus 9'd95
|
| 392 |
|
|
`define MICROPC_LOAD_EA_d16_An 9'd65
|
| 393 |
|
|
`define MICROPC_LOAD_EA_An_plus 9'd62
|
| 394 |
|
|
`define MICROPC_MOVEM_memory_to_register 9'd116
|
| 395 |
|
|
// MICROCODE - DO NOT EDIT ABOVE
|
| 396 |
|
|
|
| 397 |
|
|
/***********************************************************************************************************************
|
| 398 |
|
|
* ao68000 top level module
|
| 399 |
|
|
**********************************************************************************************************************/
|
| 400 |
|
|
|
| 401 |
|
|
/*! \brief ao68000 top level module.
|
| 402 |
|
|
*
|
| 403 |
|
|
* This module contains only instantiations of sub-modules and wire declarations.
|
| 404 |
|
|
*/
|
| 405 |
|
|
module ao68000 (
|
| 406 |
|
|
//****************** WISHBONE
|
| 407 |
|
|
input CLK_I, //% \copydoc CLK_I
|
| 408 |
|
|
input reset_n, //% \copydoc reset_n
|
| 409 |
|
|
|
| 410 |
|
|
output CYC_O, //% \copydoc CYC_O
|
| 411 |
|
|
output [31:2] ADR_O, //% \copydoc ADR_O
|
| 412 |
|
|
output [31:0] DAT_O, //% \copydoc DAT_O
|
| 413 |
|
|
input [31:0] DAT_I, //% \copydoc DAT_I
|
| 414 |
|
|
output [3:0] SEL_O, //% \copydoc SEL_O
|
| 415 |
|
|
output STB_O, //% \copydoc STB_O
|
| 416 |
|
|
output WE_O, //% \copydoc WE_O
|
| 417 |
|
|
|
| 418 |
|
|
input ACK_I, //% \copydoc ACK_I
|
| 419 |
|
|
input ERR_I, //% \copydoc ERR_I
|
| 420 |
|
|
input RTY_I, //% \copydoc RTY_I
|
| 421 |
|
|
|
| 422 |
|
|
// TAG_TYPE: TGC_O
|
| 423 |
|
|
output SGL_O, //% \copydoc SGL_O
|
| 424 |
|
|
output BLK_O, //% \copydoc BLK_O
|
| 425 |
|
|
output RMW_O, //% \copydoc RMW_O
|
| 426 |
|
|
|
| 427 |
|
|
// TAG_TYPE: TGA_O
|
| 428 |
|
|
output [2:0] CTI_O, //% \copydoc CTI_O
|
| 429 |
|
|
output [1:0] BTE_O, //% \copydoc BTE_O
|
| 430 |
|
|
|
| 431 |
|
|
// TAG_TYPE: TGC_O
|
| 432 |
|
|
output [2:0] fc_o, //% \copydoc fc_o
|
| 433 |
|
|
|
| 434 |
|
|
//****************** OTHER
|
| 435 |
|
|
/* interrupt acknowlege:
|
| 436 |
|
|
* ACK_I: interrupt vector on DAT_I[7:0]
|
| 437 |
|
|
* ERR_I: spurious interrupt
|
| 438 |
|
|
* RTY_I: autovector
|
| 439 |
|
|
*/
|
| 440 |
|
|
input [2:0] ipl_i, //% \copydoc ipl_i
|
| 441 |
|
|
output reset_o, //% \copydoc reset_o
|
| 442 |
|
|
output blocked_o //% \copydoc blocked_o
|
| 443 |
|
|
);
|
| 444 |
|
|
|
| 445 |
|
|
wire [15:0] sr;
|
| 446 |
|
|
wire [1:0] size;
|
| 447 |
|
|
wire [31:0] address;
|
| 448 |
|
|
wire address_type;
|
| 449 |
|
|
wire read_modify_write_flag;
|
| 450 |
|
|
wire [31:0] data_read;
|
| 451 |
|
|
wire [31:0] data_write;
|
| 452 |
|
|
wire [31:0] pc;
|
| 453 |
|
|
wire prefetch_ir_valid;
|
| 454 |
|
|
wire [79:0] prefetch_ir;
|
| 455 |
|
|
wire do_reset;
|
| 456 |
|
|
wire do_read;
|
| 457 |
|
|
wire do_write;
|
| 458 |
|
|
wire do_interrupt;
|
| 459 |
|
|
wire do_blocked;
|
| 460 |
|
|
wire jmp_address_trap;
|
| 461 |
|
|
wire jmp_bus_trap;
|
| 462 |
|
|
wire finished;
|
| 463 |
|
|
wire [7:0] interrupt_trap;
|
| 464 |
|
|
wire [2:0] interrupt_mask;
|
| 465 |
|
|
wire rw_state;
|
| 466 |
|
|
wire [2:0] fc_state;
|
| 467 |
|
|
wire [7:0] decoder_trap;
|
| 468 |
|
|
wire [31:0] usp;
|
| 469 |
|
|
wire [31:0] Dn_output;
|
| 470 |
|
|
wire [31:0] An_output;
|
| 471 |
|
|
wire [31:0] result;
|
| 472 |
|
|
wire [3:0] An_address;
|
| 473 |
|
|
wire [31:0] An_input;
|
| 474 |
|
|
wire [2:0] Dn_address;
|
| 475 |
|
|
wire [15:0] ir;
|
| 476 |
|
|
wire [8:0] decoder_micropc;
|
| 477 |
|
|
wire [1:0] special;
|
| 478 |
|
|
wire [8:0] load_ea;
|
| 479 |
|
|
wire [8:0] perform_ea_read;
|
| 480 |
|
|
wire [8:0] perform_ea_write;
|
| 481 |
|
|
wire [8:0] save_ea;
|
| 482 |
|
|
wire trace_flag;
|
| 483 |
|
|
wire group_0_flag;
|
| 484 |
|
|
wire stop_flag;
|
| 485 |
|
|
wire [8:0] micro_pc;
|
| 486 |
|
|
wire [31:0] operand1;
|
| 487 |
|
|
wire [31:0] operand2;
|
| 488 |
|
|
wire [4:0] movem_loop;
|
| 489 |
|
|
wire [15:0] movem_reg;
|
| 490 |
|
|
wire condition;
|
| 491 |
|
|
wire [87:0] micro_data;
|
| 492 |
|
|
wire [31:0] fault_address_state;
|
| 493 |
|
|
wire [1:0] pc_change;
|
| 494 |
|
|
wire prefetch_ir_valid_32;
|
| 495 |
|
|
wire [3:0] ea_type;
|
| 496 |
|
|
wire [2:0] ea_mod;
|
| 497 |
|
|
wire [2:0] ea_reg;
|
| 498 |
|
|
|
| 499 |
|
|
bus_control bus_control_m(
|
| 500 |
|
|
.CLK_I (CLK_I),
|
| 501 |
|
|
.reset_n (reset_n),
|
| 502 |
|
|
.CYC_O (CYC_O),
|
| 503 |
|
|
.ADR_O (ADR_O),
|
| 504 |
|
|
.DAT_O (DAT_O),
|
| 505 |
|
|
.DAT_I (DAT_I),
|
| 506 |
|
|
.SEL_O (SEL_O),
|
| 507 |
|
|
.STB_O (STB_O),
|
| 508 |
|
|
.WE_O (WE_O),
|
| 509 |
|
|
.ACK_I (ACK_I),
|
| 510 |
|
|
.ERR_I (ERR_I),
|
| 511 |
|
|
.RTY_I (RTY_I),
|
| 512 |
|
|
.SGL_O (SGL_O),
|
| 513 |
|
|
.BLK_O (BLK_O),
|
| 514 |
|
|
.RMW_O (RMW_O),
|
| 515 |
|
|
.CTI_O (CTI_O),
|
| 516 |
|
|
.BTE_O (BTE_O),
|
| 517 |
|
|
.fc_o (fc_o),
|
| 518 |
|
|
.ipl_i (ipl_i),
|
| 519 |
|
|
.reset_o (reset_o),
|
| 520 |
|
|
.blocked_o (blocked_o),
|
| 521 |
|
|
|
| 522 |
|
|
.supervisor_i (sr[13]),
|
| 523 |
|
|
.ipm_i (sr[10:8]),
|
| 524 |
|
|
.size_i (size),
|
| 525 |
|
|
.address_i (address),
|
| 526 |
|
|
.address_type_i (address_type),
|
| 527 |
|
|
.read_modify_write_i (read_modify_write_flag),
|
| 528 |
|
|
.data_write_i (data_write),
|
| 529 |
|
|
.data_read_o (data_read),
|
| 530 |
|
|
.pc_i (pc),
|
| 531 |
|
|
.pc_change_i (pc_change),
|
| 532 |
|
|
.prefetch_ir_o (prefetch_ir),
|
| 533 |
|
|
.prefetch_ir_valid_32_o (prefetch_ir_valid_32),
|
| 534 |
|
|
.prefetch_ir_valid_o (prefetch_ir_valid),
|
| 535 |
|
|
.prefetch_ir_valid_80_o (),
|
| 536 |
|
|
.do_reset_i (do_reset),
|
| 537 |
|
|
.do_blocked_i (do_blocked),
|
| 538 |
|
|
.do_read_i (do_read),
|
| 539 |
|
|
.do_write_i (do_write),
|
| 540 |
|
|
.do_interrupt_i (do_interrupt),
|
| 541 |
|
|
.jmp_address_trap_o (jmp_address_trap),
|
| 542 |
|
|
.jmp_bus_trap_o (jmp_bus_trap),
|
| 543 |
|
|
.finished_o (finished),
|
| 544 |
|
|
.interrupt_trap_o (interrupt_trap),
|
| 545 |
|
|
.interrupt_mask_o (interrupt_mask),
|
| 546 |
|
|
.rw_state_o (rw_state),
|
| 547 |
|
|
.fc_state_o (fc_state),
|
| 548 |
|
|
.fault_address_state_o (fault_address_state)
|
| 549 |
|
|
);
|
| 550 |
|
|
|
| 551 |
|
|
registers registers_m(
|
| 552 |
|
|
.clock (CLK_I),
|
| 553 |
|
|
.reset_n (reset_n),
|
| 554 |
|
|
.data_read (data_read),
|
| 555 |
|
|
.prefetch_ir (prefetch_ir),
|
| 556 |
|
|
.prefetch_ir_valid (prefetch_ir_valid),
|
| 557 |
|
|
.result (result),
|
| 558 |
|
|
.sr (sr),
|
| 559 |
|
|
.rw_state (rw_state),
|
| 560 |
|
|
.fc_state (fc_state),
|
| 561 |
|
|
.fault_address_state (fault_address_state),
|
| 562 |
|
|
.interrupt_trap (interrupt_trap),
|
| 563 |
|
|
.interrupt_mask (interrupt_mask),
|
| 564 |
|
|
.decoder_trap (decoder_trap),
|
| 565 |
|
|
.usp (usp),
|
| 566 |
|
|
.Dn_output (Dn_output),
|
| 567 |
|
|
.An_output (An_output),
|
| 568 |
|
|
|
| 569 |
|
|
.pc_change (pc_change),
|
| 570 |
|
|
|
| 571 |
|
|
.ea_reg (ea_reg),
|
| 572 |
|
|
.ea_reg_control (`MICRO_DATA_ea_reg),
|
| 573 |
|
|
.ea_mod (ea_mod),
|
| 574 |
|
|
.ea_mod_control (`MICRO_DATA_ea_mod),
|
| 575 |
|
|
.ea_type (ea_type),
|
| 576 |
|
|
.ea_type_control (`MICRO_DATA_ea_type),
|
| 577 |
|
|
.operand1 (operand1),
|
| 578 |
|
|
.operand1_control (`MICRO_DATA_op1),
|
| 579 |
|
|
.operand2 (operand2),
|
| 580 |
|
|
.operand2_control (`MICRO_DATA_op2),
|
| 581 |
|
|
.address (address),
|
| 582 |
|
|
.address_type (address_type),
|
| 583 |
|
|
.address_control (`MICRO_DATA_address),
|
| 584 |
|
|
.size (size),
|
| 585 |
|
|
.size_control (`MICRO_DATA_size),
|
| 586 |
|
|
.movem_modreg (),
|
| 587 |
|
|
.movem_modreg_control (`MICRO_DATA_movem_modreg),
|
| 588 |
|
|
.movem_loop (movem_loop),
|
| 589 |
|
|
.movem_loop_control (`MICRO_DATA_movem_loop),
|
| 590 |
|
|
.movem_reg (movem_reg),
|
| 591 |
|
|
.movem_reg_control (`MICRO_DATA_movem_reg),
|
| 592 |
|
|
.ir (ir),
|
| 593 |
|
|
.ir_control (`MICRO_DATA_ir),
|
| 594 |
|
|
.pc (pc),
|
| 595 |
|
|
.pc_control (`MICRO_DATA_pc),
|
| 596 |
|
|
.trap (),
|
| 597 |
|
|
.trap_control (`MICRO_DATA_trap),
|
| 598 |
|
|
.offset (),
|
| 599 |
|
|
.offset_control (`MICRO_DATA_offset),
|
| 600 |
|
|
.index (),
|
| 601 |
|
|
.index_control (`MICRO_DATA_index),
|
| 602 |
|
|
.stop_flag (stop_flag),
|
| 603 |
|
|
.stop_flag_control (`MICRO_DATA_stop_flag),
|
| 604 |
|
|
.trace_flag (trace_flag),
|
| 605 |
|
|
.trace_flag_control (`MICRO_DATA_trace_flag),
|
| 606 |
|
|
.group_0_flag (group_0_flag),
|
| 607 |
|
|
.group_0_flag_control (`MICRO_DATA_group_0_flag),
|
| 608 |
|
|
.instruction_flag (),
|
| 609 |
|
|
.instruction_flag_control (`MICRO_DATA_instruction_flag),
|
| 610 |
|
|
.read_modify_write_flag (read_modify_write_flag),
|
| 611 |
|
|
.read_modify_write_flag_control (`MICRO_DATA_read_modify_write_flag),
|
| 612 |
|
|
.do_reset_flag (do_reset),
|
| 613 |
|
|
.do_reset_flag_control (`MICRO_DATA_do_reset_flag),
|
| 614 |
|
|
.do_interrupt_flag (do_interrupt),
|
| 615 |
|
|
.do_interrupt_flag_control (`MICRO_DATA_do_interrupt_flag),
|
| 616 |
|
|
.do_read_flag (do_read),
|
| 617 |
|
|
.do_read_flag_control (`MICRO_DATA_do_read_flag),
|
| 618 |
|
|
.do_write_flag (do_write),
|
| 619 |
|
|
.do_write_flag_control (`MICRO_DATA_do_write_flag),
|
| 620 |
|
|
.do_blocked_flag (do_blocked),
|
| 621 |
|
|
.do_blocked_flag_control (`MICRO_DATA_do_blocked_flag),
|
| 622 |
|
|
.data_write (data_write),
|
| 623 |
|
|
.data_write_control (`MICRO_DATA_data_write),
|
| 624 |
|
|
.An_address (An_address),
|
| 625 |
|
|
.An_address_control (`MICRO_DATA_an_address),
|
| 626 |
|
|
.An_input (An_input),
|
| 627 |
|
|
.An_input_control (`MICRO_DATA_an_input),
|
| 628 |
|
|
.Dn_address (Dn_address),
|
| 629 |
|
|
.Dn_address_control (`MICRO_DATA_dn_address)
|
| 630 |
|
|
);
|
| 631 |
|
|
|
| 632 |
|
|
memory_registers memory_registers_m(
|
| 633 |
|
|
.clock (CLK_I),
|
| 634 |
|
|
.reset_n (reset_n),
|
| 635 |
|
|
.An_address (An_address),
|
| 636 |
|
|
.An_input (An_input),
|
| 637 |
|
|
.An_write_enable (`MICRO_DATA_an_write_enable),
|
| 638 |
|
|
.An_output (An_output),
|
| 639 |
|
|
.usp (usp),
|
| 640 |
|
|
.Dn_address (Dn_address),
|
| 641 |
|
|
.Dn_input (result),
|
| 642 |
|
|
.Dn_write_enable (`MICRO_DATA_dn_write_enable),
|
| 643 |
|
|
.Dn_size (size),
|
| 644 |
|
|
.Dn_output (Dn_output),
|
| 645 |
|
|
.micro_pc (micro_pc),
|
| 646 |
|
|
.micro_data (micro_data)
|
| 647 |
|
|
);
|
| 648 |
|
|
|
| 649 |
|
|
decoder decoder_m(
|
| 650 |
|
|
.clock (CLK_I),
|
| 651 |
|
|
.reset_n (reset_n),
|
| 652 |
|
|
.supervisor (sr[13]),
|
| 653 |
|
|
.ir (prefetch_ir[79:64]),
|
| 654 |
|
|
.decoder_trap (decoder_trap),
|
| 655 |
|
|
.decoder_micropc (decoder_micropc),
|
| 656 |
|
|
|
| 657 |
|
|
.load_ea (load_ea),
|
| 658 |
|
|
.perform_ea_read (perform_ea_read),
|
| 659 |
|
|
.perform_ea_write (perform_ea_write),
|
| 660 |
|
|
.save_ea (save_ea),
|
| 661 |
|
|
|
| 662 |
|
|
.ea_type (ea_type),
|
| 663 |
|
|
.ea_mod (ea_mod),
|
| 664 |
|
|
.ea_reg (ea_reg)
|
| 665 |
|
|
);
|
| 666 |
|
|
|
| 667 |
|
|
condition condition_m(
|
| 668 |
|
|
.cond (ir[11:8]),
|
| 669 |
|
|
.ccr (sr[7:0]),
|
| 670 |
|
|
.condition (condition)
|
| 671 |
|
|
);
|
| 672 |
|
|
|
| 673 |
|
|
alu alu_m(
|
| 674 |
|
|
.clock (CLK_I),
|
| 675 |
|
|
.reset_n (reset_n),
|
| 676 |
|
|
.address (address),
|
| 677 |
|
|
.ir (ir),
|
| 678 |
|
|
.size (size),
|
| 679 |
|
|
.operand1 (operand1),
|
| 680 |
|
|
.operand2 (operand2),
|
| 681 |
|
|
.interrupt_mask (interrupt_mask),
|
| 682 |
|
|
.alu_control (`MICRO_DATA_alu),
|
| 683 |
|
|
.sr (sr),
|
| 684 |
|
|
.result (result),
|
| 685 |
|
|
.special (special)
|
| 686 |
|
|
);
|
| 687 |
|
|
|
| 688 |
|
|
microcode_branch microcode_branch_m(
|
| 689 |
|
|
.clock (CLK_I),
|
| 690 |
|
|
.reset_n (reset_n),
|
| 691 |
|
|
.movem_loop (movem_loop),
|
| 692 |
|
|
.movem_reg (movem_reg),
|
| 693 |
|
|
.operand2 (operand2),
|
| 694 |
|
|
.special (special),
|
| 695 |
|
|
.condition (condition),
|
| 696 |
|
|
.result (result),
|
| 697 |
|
|
.overflow (sr[1]),
|
| 698 |
|
|
.stop_flag (stop_flag),
|
| 699 |
|
|
.ir (ir),
|
| 700 |
|
|
.decoder_trap (decoder_trap),
|
| 701 |
|
|
.trace_flag (trace_flag),
|
| 702 |
|
|
.group_0_flag (group_0_flag),
|
| 703 |
|
|
.interrupt_mask (interrupt_mask),
|
| 704 |
|
|
.load_ea (load_ea),
|
| 705 |
|
|
.perform_ea_read (perform_ea_read),
|
| 706 |
|
|
.perform_ea_write (perform_ea_write),
|
| 707 |
|
|
.save_ea (save_ea),
|
| 708 |
|
|
.decoder_micropc (decoder_micropc),
|
| 709 |
|
|
.prefetch_ir_valid_32 (prefetch_ir_valid_32),
|
| 710 |
|
|
.prefetch_ir_valid (prefetch_ir_valid),
|
| 711 |
|
|
.jmp_address_trap (jmp_address_trap),
|
| 712 |
|
|
.jmp_bus_trap (jmp_bus_trap),
|
| 713 |
|
|
.finished (finished),
|
| 714 |
|
|
.branch_control (`MICRO_DATA_branch),
|
| 715 |
|
|
.branch_offset (`MICRO_DATA_procedure),
|
| 716 |
|
|
.micro_pc (micro_pc)
|
| 717 |
|
|
);
|
| 718 |
|
|
|
| 719 |
|
|
endmodule
|
| 720 |
|
|
|
| 721 |
|
|
/***********************************************************************************************************************
|
| 722 |
|
|
* Bus control
|
| 723 |
|
|
**********************************************************************************************************************/
|
| 724 |
|
|
|
| 725 |
|
|
/*! \brief Initiate WISHBONE MASTER bus cycles.
|
| 726 |
|
|
*
|
| 727 |
|
|
* The bus_control module is the only module that has contact with signals from outside of the IP core.
|
| 728 |
|
|
* It is responsible for initiating WISHBONE MASTER bus cycles. The cycles can be divided into:
|
| 729 |
|
|
* - memory read cycles (supervisor data, supervisor program, user data, user program)
|
| 730 |
|
|
* - memory write cycles (supervisor data, user data),
|
| 731 |
|
|
* - interrupt acknowledge.
|
| 732 |
|
|
*
|
| 733 |
|
|
* Every cycle is supplemented with the following tags:
|
| 734 |
|
|
* - standard WISHBONE cycle tags: SGL_O, BLK_O, RMW_O,
|
| 735 |
|
|
* - register feedback WISHBONE address tags: CTI_O and BTE_O,
|
| 736 |
|
|
* - ao68000 specific cycle tag: fc_o which is equivalent to MC68000 function codes.
|
| 737 |
|
|
*
|
| 738 |
|
|
* The bus_control module is also responsible for registering interrupt inputs and initiating the interrupt acknowledge
|
| 739 |
|
|
* cycle in response to a microcode request. Microcode requests a interrupt acknowledge at the end of instruction
|
| 740 |
|
|
* processing, when the interrupt privilege level is higher than the current interrupt privilege mask, as specified
|
| 741 |
|
|
* in the MC68000 User's Manual.
|
| 742 |
|
|
*
|
| 743 |
|
|
* Finally, bus_control controls also two ao68000 specific core outputs:
|
| 744 |
|
|
* - blocked output, high when that the processor is blocked after encountering a double bus error. The only way
|
| 745 |
|
|
* to leave this block state is by reseting the ao68000 by the asynchronous reset input signal.
|
| 746 |
|
|
* - reset output, high when processing the RESET instruction. Can be used to reset external devices.
|
| 747 |
|
|
*/
|
| 748 |
|
|
module bus_control(
|
| 749 |
|
|
//******************************************* external
|
| 750 |
|
|
//****************** WISHBONE
|
| 751 |
|
|
input CLK_I,
|
| 752 |
|
|
input reset_n,
|
| 753 |
|
|
|
| 754 |
|
|
output reg CYC_O,
|
| 755 |
|
|
output reg [31:2] ADR_O,
|
| 756 |
|
|
output reg [31:0] DAT_O,
|
| 757 |
|
|
input [31:0] DAT_I,
|
| 758 |
|
|
output reg [3:0] SEL_O,
|
| 759 |
|
|
output reg STB_O,
|
| 760 |
|
|
output reg WE_O,
|
| 761 |
|
|
|
| 762 |
|
|
input ACK_I,
|
| 763 |
|
|
input ERR_I,
|
| 764 |
|
|
input RTY_I,
|
| 765 |
|
|
|
| 766 |
|
|
// TAG_TYPE: TGC_O
|
| 767 |
|
|
output reg SGL_O,
|
| 768 |
|
|
output reg BLK_O,
|
| 769 |
|
|
output reg RMW_O,
|
| 770 |
|
|
|
| 771 |
|
|
// TAG_TYPE: TGA_O
|
| 772 |
|
|
output reg [2:0] CTI_O,
|
| 773 |
|
|
output [1:0] BTE_O,
|
| 774 |
|
|
|
| 775 |
|
|
// TAG_TYPE: TGC_O
|
| 776 |
|
|
output reg [2:0] fc_o,
|
| 777 |
|
|
|
| 778 |
|
|
//****************** OTHER
|
| 779 |
|
|
input [2:0] ipl_i,
|
| 780 |
|
|
output reg reset_o = 1'b0,
|
| 781 |
|
|
output reg blocked_o = 1'b0,
|
| 782 |
|
|
|
| 783 |
|
|
//******************************************* internal
|
| 784 |
|
|
input supervisor_i,
|
| 785 |
|
|
input [2:0] ipm_i,
|
| 786 |
|
|
input [1:0] size_i,
|
| 787 |
|
|
input [31:0] address_i,
|
| 788 |
|
|
input address_type_i,
|
| 789 |
|
|
input read_modify_write_i,
|
| 790 |
|
|
input [31:0] data_write_i,
|
| 791 |
|
|
output reg [31:0] data_read_o,
|
| 792 |
|
|
|
| 793 |
|
|
input [31:0] pc_i,
|
| 794 |
|
|
input [1:0] pc_change_i,
|
| 795 |
|
|
output reg [79:0] prefetch_ir_o,
|
| 796 |
|
|
output reg prefetch_ir_valid_32_o = 1'b0,
|
| 797 |
|
|
output reg prefetch_ir_valid_o = 1'b0,
|
| 798 |
|
|
output reg prefetch_ir_valid_80_o = 1'b0,
|
| 799 |
|
|
|
| 800 |
|
|
input do_reset_i,
|
| 801 |
|
|
input do_blocked_i,
|
| 802 |
|
|
input do_read_i,
|
| 803 |
|
|
input do_write_i,
|
| 804 |
|
|
input do_interrupt_i,
|
| 805 |
|
|
|
| 806 |
|
|
output reg jmp_address_trap_o = 1'b0,
|
| 807 |
|
|
output reg jmp_bus_trap_o = 1'b0,
|
| 808 |
|
|
// read/write/interrupt
|
| 809 |
|
|
output reg finished_o,
|
| 810 |
|
|
|
| 811 |
|
|
output reg [7:0] interrupt_trap_o = 8'b0,
|
| 812 |
|
|
output reg [2:0] interrupt_mask_o = 3'b0,
|
| 813 |
|
|
|
| 814 |
|
|
/* mask==0 && trap==0 nothing
|
| 815 |
|
|
* mask!=0 interrupt with spurious interrupt
|
| 816 |
|
|
*/
|
| 817 |
|
|
|
| 818 |
|
|
// write = 0/read = 1
|
| 819 |
|
|
output reg rw_state_o,
|
| 820 |
|
|
output reg [2:0] fc_state_o,
|
| 821 |
|
|
output reg [31:0] fault_address_state_o
|
| 822 |
|
|
);
|
| 823 |
|
|
|
| 824 |
|
|
assign BTE_O = 2'b00;
|
| 825 |
|
|
|
| 826 |
|
|
wire [31:0] pc_i_plus_6;
|
| 827 |
|
|
assign pc_i_plus_6 = pc_i + 32'd6;
|
| 828 |
|
|
wire [31:0] pc_i_plus_4;
|
| 829 |
|
|
assign pc_i_plus_4 = pc_i + 32'd4;
|
| 830 |
|
|
|
| 831 |
|
|
wire [31:0] address_i_plus_4;
|
| 832 |
|
|
assign address_i_plus_4 = address_i + 32'd4;
|
| 833 |
|
|
|
| 834 |
|
|
reg [1:0] saved_pc_change = 2'b00;
|
| 835 |
|
|
|
| 836 |
|
|
parameter [4:0]
|
| 837 |
|
|
S_INIT = 5'd0,
|
| 838 |
|
|
S_RESET = 5'd1,
|
| 839 |
|
|
S_BLOCKED = 5'd2,
|
| 840 |
|
|
S_INT_1 = 5'd3,
|
| 841 |
|
|
S_READ_1 = 5'd4,
|
| 842 |
|
|
S_READ_2 = 5'd5,
|
| 843 |
|
|
S_READ_3 = 5'd6,
|
| 844 |
|
|
S_WAIT = 5'd7,
|
| 845 |
|
|
S_WRITE_1 = 5'd8,
|
| 846 |
|
|
S_WRITE_2 = 5'd9,
|
| 847 |
|
|
S_WRITE_3 = 5'd10,
|
| 848 |
|
|
S_PC_0 = 5'd11,
|
| 849 |
|
|
S_PC_1 = 5'd12,
|
| 850 |
|
|
S_PC_2 = 5'd13,
|
| 851 |
|
|
S_PC_3 = 5'd14,
|
| 852 |
|
|
S_PC_4 = 5'd15,
|
| 853 |
|
|
S_PC_5 = 5'd16,
|
| 854 |
|
|
S_PC_6 = 5'd17;
|
| 855 |
|
|
|
| 856 |
|
|
parameter [2:0]
|
| 857 |
|
|
FC_USER_DATA = 3'd1,
|
| 858 |
|
|
FC_USER_PROGRAM = 3'd2,
|
| 859 |
|
|
FC_SUPERVISOR_DATA = 3'd5, // all exception vector entries except reset
|
| 860 |
|
|
FC_SUPERVISOR_PROGRAM = 3'd6, // exception vector for reset
|
| 861 |
|
|
FC_CPU_SPACE = 3'd7; // interrupt acknowlege bus cycle
|
| 862 |
|
|
|
| 863 |
|
|
parameter [2:0]
|
| 864 |
|
|
CTI_CLASSIC_CYCLE = 3'd0,
|
| 865 |
|
|
CTI_CONST_CYCLE = 3'd1,
|
| 866 |
|
|
CTI_INCR_CYCLE = 3'd2,
|
| 867 |
|
|
CTI_END_OF_BURST = 3'd7;
|
| 868 |
|
|
|
| 869 |
|
|
parameter [7:0]
|
| 870 |
|
|
VECTOR_BUS_TRAP = 8'd2,
|
| 871 |
|
|
VECTOR_ADDRESS_TRAP = 8'd3;
|
| 872 |
|
|
|
| 873 |
|
|
reg [4:0] current_state;
|
| 874 |
|
|
reg [7:0] reset_counter;
|
| 875 |
|
|
|
| 876 |
|
|
reg [2:0] last_interrupt_mask;
|
| 877 |
|
|
always @(posedge CLK_I or negedge reset_n) begin
|
| 878 |
|
|
if(reset_n == 1'b0) begin
|
| 879 |
|
|
interrupt_mask_o <= 3'b000;
|
| 880 |
|
|
last_interrupt_mask <= 3'b000;
|
| 881 |
|
|
end
|
| 882 |
|
|
else if(ipl_i > ipm_i && do_interrupt_i == 1'b0) begin
|
| 883 |
|
|
interrupt_mask_o <= ipl_i;
|
| 884 |
|
|
last_interrupt_mask <= interrupt_mask_o;
|
| 885 |
|
|
end
|
| 886 |
|
|
else if(do_interrupt_i == 1'b1) begin
|
| 887 |
|
|
interrupt_mask_o <= last_interrupt_mask;
|
| 888 |
|
|
end
|
| 889 |
|
|
else begin
|
| 890 |
|
|
interrupt_mask_o <= 3'b000;
|
| 891 |
|
|
last_interrupt_mask <= 3'b000;
|
| 892 |
|
|
end
|
| 893 |
|
|
end
|
| 894 |
|
|
|
| 895 |
|
|
// change pc_i in middle of prefetch operation: undefined
|
| 896 |
|
|
|
| 897 |
|
|
always @(posedge CLK_I or negedge reset_n) begin
|
| 898 |
|
|
if(reset_n == 1'b0) begin
|
| 899 |
|
|
current_state <= S_INIT;
|
| 900 |
|
|
interrupt_trap_o <= 8'd0;
|
| 901 |
|
|
prefetch_ir_valid_o <= 1'b0;
|
| 902 |
|
|
prefetch_ir_valid_32_o <= 1'b0;
|
| 903 |
|
|
prefetch_ir_valid_80_o <= 1'b0;
|
| 904 |
|
|
|
| 905 |
|
|
jmp_address_trap_o <= 1'b0;
|
| 906 |
|
|
jmp_bus_trap_o <= 1'b0;
|
| 907 |
|
|
|
| 908 |
|
|
CYC_O <= 1'b0;
|
| 909 |
|
|
ADR_O <= 30'd0;
|
| 910 |
|
|
DAT_O <= 32'd0;
|
| 911 |
|
|
SEL_O <= 4'b0;
|
| 912 |
|
|
STB_O <= 1'b0;
|
| 913 |
|
|
WE_O <= 1'b0;
|
| 914 |
|
|
SGL_O <= 1'b0;
|
| 915 |
|
|
BLK_O <= 1'b0;
|
| 916 |
|
|
RMW_O <= 1'b0;
|
| 917 |
|
|
CTI_O <= 3'd0;
|
| 918 |
|
|
fc_o <= 3'd0;
|
| 919 |
|
|
reset_o <= 1'b0;
|
| 920 |
|
|
blocked_o <= 1'b0;
|
| 921 |
|
|
data_read_o <= 32'd0;
|
| 922 |
|
|
finished_o <= 1'b0;
|
| 923 |
|
|
rw_state_o <= 1'b0;
|
| 924 |
|
|
fc_state_o <= 3'd0;
|
| 925 |
|
|
fault_address_state_o <= 32'd0;
|
| 926 |
|
|
saved_pc_change <= 2'b0;
|
| 927 |
|
|
reset_counter <= 8'd0;
|
| 928 |
|
|
end
|
| 929 |
|
|
else begin
|
| 930 |
|
|
case(current_state)
|
| 931 |
|
|
S_INIT: begin
|
| 932 |
|
|
finished_o <= 1'b0;
|
| 933 |
|
|
jmp_address_trap_o <= 1'b0;
|
| 934 |
|
|
jmp_bus_trap_o <= 1'b0;
|
| 935 |
|
|
reset_o <= 1'b0;
|
| 936 |
|
|
blocked_o <= 1'b0;
|
| 937 |
|
|
|
| 938 |
|
|
// block
|
| 939 |
|
|
if(do_blocked_i == 1'b1) begin
|
| 940 |
|
|
blocked_o <= 1'b1;
|
| 941 |
|
|
current_state <= S_BLOCKED;
|
| 942 |
|
|
end
|
| 943 |
|
|
// reset
|
| 944 |
|
|
else if(do_reset_i == 1'b1) begin
|
| 945 |
|
|
reset_o <= 1'b1;
|
| 946 |
|
|
reset_counter <= 8'd124;
|
| 947 |
|
|
current_state <= S_RESET;
|
| 948 |
|
|
end
|
| 949 |
|
|
// read
|
| 950 |
|
|
else if(do_read_i == 1'b1) begin
|
| 951 |
|
|
WE_O <= 1'b0;
|
| 952 |
|
|
if(supervisor_i == 1'b1) fc_o <= (address_type_i == 1'b0) ? FC_SUPERVISOR_DATA : FC_SUPERVISOR_PROGRAM;
|
| 953 |
|
|
else fc_o <= (address_type_i == 1'b0) ? FC_USER_DATA : FC_USER_PROGRAM;
|
| 954 |
|
|
|
| 955 |
|
|
if(address_i[0] == 1'b1 && (size_i == 2'b01 || size_i == 2'b10)) begin
|
| 956 |
|
|
fault_address_state_o <= address_i;
|
| 957 |
|
|
rw_state_o <= 1'b1;
|
| 958 |
|
|
fc_state_o <= (supervisor_i == 1'b1) ? ((address_type_i == 1'b0) ? FC_SUPERVISOR_DATA : FC_SUPERVISOR_PROGRAM) :
|
| 959 |
|
|
((address_type_i == 1'b0) ? FC_USER_DATA : FC_USER_PROGRAM);
|
| 960 |
|
|
interrupt_trap_o <= VECTOR_ADDRESS_TRAP;
|
| 961 |
|
|
|
| 962 |
|
|
jmp_address_trap_o <= 1'b1;
|
| 963 |
|
|
current_state <= S_WAIT;
|
| 964 |
|
|
end
|
| 965 |
|
|
else begin
|
| 966 |
|
|
CYC_O <= 1'b1;
|
| 967 |
|
|
ADR_O <= address_i[31:2];
|
| 968 |
|
|
SEL_O <= (size_i == 2'b00 && address_i[1:0] == 2'b00)? 4'b1000 :
|
| 969 |
|
|
(size_i == 2'b00 && address_i[1:0] == 2'b01)? 4'b0100 :
|
| 970 |
|
|
(size_i == 2'b00 && address_i[1:0] == 2'b10)? 4'b0010 :
|
| 971 |
|
|
(size_i == 2'b00 && address_i[1:0] == 2'b11)? 4'b0001 :
|
| 972 |
|
|
(size_i == 2'b01 && address_i[1] == 2'b0)? 4'b1100 :
|
| 973 |
|
|
((size_i == 2'b01 || size_i == 2'b10) && address_i[1] == 2'b1)? 4'b0011 :
|
| 974 |
|
|
4'b1111;
|
| 975 |
|
|
STB_O <= 1'b1;
|
| 976 |
|
|
|
| 977 |
|
|
if(read_modify_write_i == 1'b1) begin
|
| 978 |
|
|
SGL_O <= 1'b0;
|
| 979 |
|
|
BLK_O <= 1'b0;
|
| 980 |
|
|
RMW_O <= 1'b1;
|
| 981 |
|
|
CTI_O <= CTI_END_OF_BURST;
|
| 982 |
|
|
end
|
| 983 |
|
|
else if(address_i[1:0] == 2'b10 && size_i == 2'b10) begin
|
| 984 |
|
|
SGL_O <= 1'b0;
|
| 985 |
|
|
BLK_O <= 1'b1;
|
| 986 |
|
|
RMW_O <= 1'b0;
|
| 987 |
|
|
CTI_O <= CTI_INCR_CYCLE;
|
| 988 |
|
|
end
|
| 989 |
|
|
else begin
|
| 990 |
|
|
SGL_O <= 1'b1;
|
| 991 |
|
|
BLK_O <= 1'b0;
|
| 992 |
|
|
RMW_O <= 1'b0;
|
| 993 |
|
|
CTI_O <= CTI_END_OF_BURST;
|
| 994 |
|
|
end
|
| 995 |
|
|
|
| 996 |
|
|
current_state <= S_READ_1;
|
| 997 |
|
|
end
|
| 998 |
|
|
end
|
| 999 |
|
|
// write
|
| 1000 |
|
|
else if(do_write_i == 1'b1) begin
|
| 1001 |
|
|
WE_O <= 1'b1;
|
| 1002 |
|
|
if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_DATA;
|
| 1003 |
|
|
else fc_o <= FC_USER_DATA;
|
| 1004 |
|
|
|
| 1005 |
|
|
if(address_i[0] == 1'b1 && (size_i == 2'b01 || size_i == 2'b10)) begin
|
| 1006 |
|
|
fault_address_state_o <= address_i;
|
| 1007 |
|
|
rw_state_o <= 1'b0;
|
| 1008 |
|
|
fc_state_o <= (supervisor_i == 1'b1) ? FC_SUPERVISOR_DATA : FC_USER_DATA;
|
| 1009 |
|
|
interrupt_trap_o <= VECTOR_ADDRESS_TRAP;
|
| 1010 |
|
|
|
| 1011 |
|
|
jmp_address_trap_o <= 1'b1;
|
| 1012 |
|
|
current_state <= S_WAIT;
|
| 1013 |
|
|
end
|
| 1014 |
|
|
else begin
|
| 1015 |
|
|
CYC_O <= 1'b1;
|
| 1016 |
|
|
ADR_O <= address_i[31:2];
|
| 1017 |
|
|
STB_O <= 1'b1;
|
| 1018 |
|
|
|
| 1019 |
|
|
if(address_i[1:0] == 2'b10 && size_i == 2'b10) begin
|
| 1020 |
|
|
DAT_O <= { 16'b0, data_write_i[31:16] };
|
| 1021 |
|
|
SEL_O <= 4'b0011;
|
| 1022 |
|
|
end
|
| 1023 |
|
|
else if(address_i[1:0] == 2'b00 && size_i == 2'b10) begin
|
| 1024 |
|
|
DAT_O <= data_write_i[31:0];
|
| 1025 |
|
|
SEL_O <= 4'b1111;
|
| 1026 |
|
|
end
|
| 1027 |
|
|
else if(address_i[1:0] == 2'b10 && size_i == 2'b01) begin
|
| 1028 |
|
|
DAT_O <= { 16'b0, data_write_i[15:0] };
|
| 1029 |
|
|
SEL_O <= 4'b0011;
|
| 1030 |
|
|
end
|
| 1031 |
|
|
else if(address_i[1:0] == 2'b00 && size_i == 2'b01) begin
|
| 1032 |
|
|
DAT_O <= { data_write_i[15:0], 16'b0 };
|
| 1033 |
|
|
SEL_O <= 4'b1100;
|
| 1034 |
|
|
end
|
| 1035 |
|
|
else if(address_i[1:0] == 2'b11 && size_i == 2'b00) begin
|
| 1036 |
|
|
DAT_O <= { 24'b0, data_write_i[7:0] };
|
| 1037 |
|
|
SEL_O <= 4'b0001;
|
| 1038 |
|
|
end
|
| 1039 |
|
|
else if(address_i[1:0] == 2'b10 && size_i == 2'b00) begin
|
| 1040 |
|
|
DAT_O <= { 16'b0, data_write_i[7:0], 8'b0 };
|
| 1041 |
|
|
SEL_O <= 4'b0010;
|
| 1042 |
|
|
end
|
| 1043 |
|
|
else if(address_i[1:0] == 2'b01 && size_i == 2'b00) begin
|
| 1044 |
|
|
DAT_O <= { 8'b0, data_write_i[7:0], 16'b0 };
|
| 1045 |
|
|
SEL_O <= 4'b0100;
|
| 1046 |
|
|
end
|
| 1047 |
|
|
else if(address_i[1:0] == 2'b00 && size_i == 2'b00) begin
|
| 1048 |
|
|
DAT_O <= { data_write_i[7:0], 24'b0 };
|
| 1049 |
|
|
SEL_O <= 4'b1000;
|
| 1050 |
|
|
end
|
| 1051 |
|
|
|
| 1052 |
|
|
if(read_modify_write_i == 1'b1) begin
|
| 1053 |
|
|
SGL_O <= 1'b0;
|
| 1054 |
|
|
BLK_O <= 1'b0;
|
| 1055 |
|
|
RMW_O <= 1'b1;
|
| 1056 |
|
|
CTI_O <= CTI_END_OF_BURST;
|
| 1057 |
|
|
end
|
| 1058 |
|
|
else if(address_i[1:0] == 2'b10 && size_i == 2'b10) begin
|
| 1059 |
|
|
SGL_O <= 1'b0;
|
| 1060 |
|
|
BLK_O <= 1'b1;
|
| 1061 |
|
|
RMW_O <= 1'b0;
|
| 1062 |
|
|
CTI_O <= CTI_INCR_CYCLE;
|
| 1063 |
|
|
end
|
| 1064 |
|
|
else begin
|
| 1065 |
|
|
SGL_O <= 1'b1;
|
| 1066 |
|
|
BLK_O <= 1'b0;
|
| 1067 |
|
|
RMW_O <= 1'b0;
|
| 1068 |
|
|
CTI_O <= CTI_END_OF_BURST;
|
| 1069 |
|
|
end
|
| 1070 |
|
|
|
| 1071 |
|
|
current_state <= S_WRITE_1;
|
| 1072 |
|
|
end
|
| 1073 |
|
|
end
|
| 1074 |
|
|
// pc
|
| 1075 |
|
|
else if(prefetch_ir_valid_o == 1'b0 || pc_change_i != 2'b00) begin
|
| 1076 |
|
|
|
| 1077 |
|
|
if(prefetch_ir_valid_o == 1'b0 || pc_change_i == 2'b10 || pc_change_i == 2'b11) begin
|
| 1078 |
|
|
// load 4 words: [79:16] in 2,3 cycles
|
| 1079 |
|
|
prefetch_ir_valid_32_o <= 1'b0;
|
| 1080 |
|
|
prefetch_ir_valid_o <= 1'b0;
|
| 1081 |
|
|
prefetch_ir_valid_80_o <= 1'b0;
|
| 1082 |
|
|
|
| 1083 |
|
|
current_state <= S_PC_0;
|
| 1084 |
|
|
end
|
| 1085 |
|
|
else if(prefetch_ir_valid_80_o == 1'b0 && pc_change_i == 2'b01) begin
|
| 1086 |
|
|
// load 2 words: [31:0] in 1 cycle
|
| 1087 |
|
|
prefetch_ir_valid_32_o <= 1'b1;
|
| 1088 |
|
|
prefetch_ir_valid_o <= 1'b0;
|
| 1089 |
|
|
prefetch_ir_valid_80_o <= 1'b0;
|
| 1090 |
|
|
|
| 1091 |
|
|
prefetch_ir_o <= { prefetch_ir_o[63:0], 16'b0 };
|
| 1092 |
|
|
current_state <= S_PC_0;
|
| 1093 |
|
|
end
|
| 1094 |
|
|
else begin
|
| 1095 |
|
|
// do not load any words
|
| 1096 |
|
|
prefetch_ir_valid_32_o <= 1'b1;
|
| 1097 |
|
|
prefetch_ir_valid_o <= 1'b1;
|
| 1098 |
|
|
prefetch_ir_valid_80_o <= 1'b0;
|
| 1099 |
|
|
|
| 1100 |
|
|
prefetch_ir_o <= { prefetch_ir_o[63:0], 16'b0 };
|
| 1101 |
|
|
end
|
| 1102 |
|
|
|
| 1103 |
|
|
|
| 1104 |
|
|
end
|
| 1105 |
|
|
// interrupt
|
| 1106 |
|
|
else if(do_interrupt_i == 1'b1) begin
|
| 1107 |
|
|
CYC_O <= 1'b1;
|
| 1108 |
|
|
ADR_O <= { 27'b111_1111_1111_1111_1111_1111_1111, last_interrupt_mask };
|
| 1109 |
|
|
SEL_O <= 4'b1111;
|
| 1110 |
|
|
STB_O <= 1'b1;
|
| 1111 |
|
|
WE_O <= 1'b0;
|
| 1112 |
|
|
|
| 1113 |
|
|
SGL_O <= 1'b1;
|
| 1114 |
|
|
BLK_O <= 1'b0;
|
| 1115 |
|
|
RMW_O <= 1'b0;
|
| 1116 |
|
|
CTI_O <= CTI_END_OF_BURST;
|
| 1117 |
|
|
|
| 1118 |
|
|
fc_o <= FC_CPU_SPACE;
|
| 1119 |
|
|
|
| 1120 |
|
|
current_state <= S_INT_1;
|
| 1121 |
|
|
end
|
| 1122 |
|
|
end
|
| 1123 |
|
|
|
| 1124 |
|
|
S_RESET: begin
|
| 1125 |
|
|
reset_counter <= reset_counter - 8'd1;
|
| 1126 |
|
|
|
| 1127 |
|
|
if(reset_counter == 8'd0) begin
|
| 1128 |
|
|
finished_o <= 1'b1;
|
| 1129 |
|
|
current_state <= S_WAIT;
|
| 1130 |
|
|
end
|
| 1131 |
|
|
end
|
| 1132 |
|
|
|
| 1133 |
|
|
S_BLOCKED: begin
|
| 1134 |
|
|
end
|
| 1135 |
|
|
|
| 1136 |
|
|
S_INT_1: begin
|
| 1137 |
|
|
if(ACK_I == 1'b1) begin
|
| 1138 |
|
|
CYC_O <= 1'b0;
|
| 1139 |
|
|
STB_O <= 1'b0;
|
| 1140 |
|
|
|
| 1141 |
|
|
interrupt_trap_o <= DAT_I[7:0];
|
| 1142 |
|
|
|
| 1143 |
|
|
finished_o <= 1'b1;
|
| 1144 |
|
|
current_state <= S_WAIT;
|
| 1145 |
|
|
end
|
| 1146 |
|
|
else if(RTY_I == 1'b1) begin
|
| 1147 |
|
|
CYC_O <= 1'b0;
|
| 1148 |
|
|
STB_O <= 1'b0;
|
| 1149 |
|
|
|
| 1150 |
|
|
interrupt_trap_o <= 8'd24 + { 5'b0, interrupt_mask_o };
|
| 1151 |
|
|
|
| 1152 |
|
|
finished_o <= 1'b1;
|
| 1153 |
|
|
current_state <= S_WAIT;
|
| 1154 |
|
|
end
|
| 1155 |
|
|
else if(ERR_I == 1'b1) begin
|
| 1156 |
|
|
CYC_O <= 1'b0;
|
| 1157 |
|
|
STB_O <= 1'b0;
|
| 1158 |
|
|
|
| 1159 |
|
|
interrupt_trap_o <= 8'd24; // spurious interrupt
|
| 1160 |
|
|
|
| 1161 |
|
|
finished_o <= 1'b1;
|
| 1162 |
|
|
current_state <= S_WAIT;
|
| 1163 |
|
|
end
|
| 1164 |
|
|
end
|
| 1165 |
|
|
|
| 1166 |
|
|
S_PC_0: begin
|
| 1167 |
|
|
WE_O <= 1'b0;
|
| 1168 |
|
|
if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;
|
| 1169 |
|
|
else fc_o <= FC_USER_PROGRAM;
|
| 1170 |
|
|
|
| 1171 |
|
|
if(pc_i[0] == 1'b1) begin
|
| 1172 |
|
|
prefetch_ir_valid_32_o <= 1'b1;
|
| 1173 |
|
|
prefetch_ir_valid_o <= 1'b1;
|
| 1174 |
|
|
prefetch_ir_valid_80_o <= 1'b1;
|
| 1175 |
|
|
|
| 1176 |
|
|
fault_address_state_o <= pc_i;
|
| 1177 |
|
|
rw_state_o <= 1'b1;
|
| 1178 |
|
|
fc_state_o <= (supervisor_i == 1'b1) ? FC_SUPERVISOR_PROGRAM : FC_USER_PROGRAM;
|
| 1179 |
|
|
interrupt_trap_o <= VECTOR_ADDRESS_TRAP;
|
| 1180 |
|
|
|
| 1181 |
|
|
jmp_address_trap_o <= 1'b1;
|
| 1182 |
|
|
current_state <= S_WAIT;
|
| 1183 |
|
|
end
|
| 1184 |
|
|
else begin
|
| 1185 |
|
|
CYC_O <= 1'b1;
|
| 1186 |
|
|
|
| 1187 |
|
|
if(prefetch_ir_valid_32_o == 1'b0) ADR_O <= pc_i[31:2];
|
| 1188 |
|
|
else ADR_O <= pc_i_plus_6[31:2];
|
| 1189 |
|
|
|
| 1190 |
|
|
SEL_O <= (pc_i[1:0] == 2'b10)? 4'b0011 :
|
| 1191 |
|
|
4'b1111;
|
| 1192 |
|
|
STB_O <= 1'b1;
|
| 1193 |
|
|
|
| 1194 |
|
|
if(prefetch_ir_valid_32_o == 1'b0) begin
|
| 1195 |
|
|
SGL_O <= 1'b0;
|
| 1196 |
|
|
BLK_O <= 1'b1;
|
| 1197 |
|
|
RMW_O <= 1'b0;
|
| 1198 |
|
|
CTI_O <= CTI_INCR_CYCLE;
|
| 1199 |
|
|
end
|
| 1200 |
|
|
else begin
|
| 1201 |
|
|
SGL_O <= 1'b1;
|
| 1202 |
|
|
BLK_O <= 1'b0;
|
| 1203 |
|
|
RMW_O <= 1'b0;
|
| 1204 |
|
|
CTI_O <= CTI_END_OF_BURST;
|
| 1205 |
|
|
end
|
| 1206 |
|
|
|
| 1207 |
|
|
saved_pc_change <= pc_change_i;
|
| 1208 |
|
|
prefetch_ir_valid_32_o <= 1'b0;
|
| 1209 |
|
|
|
| 1210 |
|
|
current_state <= S_PC_1;
|
| 1211 |
|
|
end
|
| 1212 |
|
|
end
|
| 1213 |
|
|
|
| 1214 |
|
|
S_PC_1: begin
|
| 1215 |
|
|
if(pc_change_i != 2'b00) saved_pc_change <= pc_change_i;
|
| 1216 |
|
|
|
| 1217 |
|
|
if(ACK_I == 1'b1) begin
|
| 1218 |
|
|
if(CTI_O == CTI_INCR_CYCLE) begin
|
| 1219 |
|
|
//CYC_O <= 1'b1;
|
| 1220 |
|
|
ADR_O <= pc_i_plus_4[31:2];
|
| 1221 |
|
|
SEL_O <= 4'b1111;
|
| 1222 |
|
|
//STB_O <= 1'b1;
|
| 1223 |
|
|
//WE_O <= 1'b0;
|
| 1224 |
|
|
|
| 1225 |
|
|
if(pc_i[1:0] == 2'b10) begin
|
| 1226 |
|
|
SGL_O <= 1'b0;
|
| 1227 |
|
|
BLK_O <= 1'b1;
|
| 1228 |
|
|
RMW_O <= 1'b0;
|
| 1229 |
|
|
CTI_O <= CTI_INCR_CYCLE;
|
| 1230 |
|
|
end
|
| 1231 |
|
|
else begin
|
| 1232 |
|
|
SGL_O <= 1'b0;
|
| 1233 |
|
|
BLK_O <= 1'b1;
|
| 1234 |
|
|
RMW_O <= 1'b0;
|
| 1235 |
|
|
CTI_O <= CTI_END_OF_BURST;
|
| 1236 |
|
|
end
|
| 1237 |
|
|
|
| 1238 |
|
|
//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;
|
| 1239 |
|
|
//else fc_o <= FC_USER_PROGRAM;
|
| 1240 |
|
|
|
| 1241 |
|
|
if(pc_i[1:0] == 2'b10) prefetch_ir_o <= { DAT_I[15:0], 64'b0 };
|
| 1242 |
|
|
else prefetch_ir_o <= { DAT_I[31:0], 48'b0 };
|
| 1243 |
|
|
|
| 1244 |
|
|
current_state <= S_PC_3;
|
| 1245 |
|
|
end
|
| 1246 |
|
|
else begin
|
| 1247 |
|
|
CYC_O <= 1'b0;
|
| 1248 |
|
|
STB_O <= 1'b0;
|
| 1249 |
|
|
|
| 1250 |
|
|
if(saved_pc_change == 2'b10 || saved_pc_change == 2'b11 || pc_change_i == 2'b10 || pc_change_i == 2'b11) begin
|
| 1251 |
|
|
// load 4 words: [79:16] in 2,3 cycles
|
| 1252 |
|
|
prefetch_ir_valid_32_o <= 1'b0;
|
| 1253 |
|
|
prefetch_ir_valid_o <= 1'b0;
|
| 1254 |
|
|
prefetch_ir_valid_80_o <= 1'b0;
|
| 1255 |
|
|
|
| 1256 |
|
|
current_state <= S_PC_0;
|
| 1257 |
|
|
end
|
| 1258 |
|
|
else if(saved_pc_change == 2'b01 || pc_change_i == 2'b01) begin
|
| 1259 |
|
|
// do not load any words
|
| 1260 |
|
|
prefetch_ir_valid_32_o <= 1'b1;
|
| 1261 |
|
|
prefetch_ir_valid_o <= 1'b1;
|
| 1262 |
|
|
prefetch_ir_valid_80_o <= 1'b0;
|
| 1263 |
|
|
|
| 1264 |
|
|
prefetch_ir_o <= { prefetch_ir_o[63:32], DAT_I[31:0], 16'b0 };
|
| 1265 |
|
|
current_state <= S_INIT;
|
| 1266 |
|
|
end
|
| 1267 |
|
|
else begin
|
| 1268 |
|
|
prefetch_ir_valid_32_o <= 1'b1;
|
| 1269 |
|
|
prefetch_ir_valid_o <= 1'b1;
|
| 1270 |
|
|
prefetch_ir_valid_80_o <= 1'b1;
|
| 1271 |
|
|
|
| 1272 |
|
|
prefetch_ir_o <= { prefetch_ir_o[79:32], DAT_I[31:0] };
|
| 1273 |
|
|
current_state <= S_INIT;
|
| 1274 |
|
|
end
|
| 1275 |
|
|
end
|
| 1276 |
|
|
end
|
| 1277 |
|
|
else if(RTY_I == 1'b1) begin
|
| 1278 |
|
|
CYC_O <= 1'b0;
|
| 1279 |
|
|
STB_O <= 1'b0;
|
| 1280 |
|
|
|
| 1281 |
|
|
current_state <= S_PC_2;
|
| 1282 |
|
|
end
|
| 1283 |
|
|
else if(ERR_I == 1'b1) begin
|
| 1284 |
|
|
CYC_O <= 1'b0;
|
| 1285 |
|
|
STB_O <= 1'b0;
|
| 1286 |
|
|
|
| 1287 |
|
|
fault_address_state_o <= { ADR_O, 2'b00 };
|
| 1288 |
|
|
rw_state_o <= ~WE_O;
|
| 1289 |
|
|
fc_state_o <= fc_o;
|
| 1290 |
|
|
interrupt_trap_o <= VECTOR_BUS_TRAP;
|
| 1291 |
|
|
|
| 1292 |
|
|
jmp_bus_trap_o <= 1'b1;
|
| 1293 |
|
|
current_state <= S_WAIT;
|
| 1294 |
|
|
end
|
| 1295 |
|
|
end
|
| 1296 |
|
|
S_PC_2: begin
|
| 1297 |
|
|
CYC_O <= 1'b1;
|
| 1298 |
|
|
STB_O <= 1'b1;
|
| 1299 |
|
|
|
| 1300 |
|
|
current_state <= S_PC_1;
|
| 1301 |
|
|
end
|
| 1302 |
|
|
S_PC_3: begin
|
| 1303 |
|
|
if(ACK_I == 1'b1) begin
|
| 1304 |
|
|
if(pc_i[1:0] == 2'b10) begin
|
| 1305 |
|
|
//CYC_O <= 1'b1;
|
| 1306 |
|
|
ADR_O <= pc_i_plus_6[31:2];
|
| 1307 |
|
|
SEL_O <= 4'b1111;
|
| 1308 |
|
|
//STB_O <= 1'b1;
|
| 1309 |
|
|
//WE_O <= 1'b0;
|
| 1310 |
|
|
|
| 1311 |
|
|
SGL_O <= 1'b0;
|
| 1312 |
|
|
BLK_O <= 1'b1;
|
| 1313 |
|
|
RMW_O <= 1'b0;
|
| 1314 |
|
|
CTI_O <= CTI_END_OF_BURST;
|
| 1315 |
|
|
|
| 1316 |
|
|
//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_PROGRAM;
|
| 1317 |
|
|
//else fc_o <= FC_USER_PROGRAM;
|
| 1318 |
|
|
|
| 1319 |
|
|
prefetch_ir_o <= { prefetch_ir_o[79:64], DAT_I[31:0], 32'b0 };
|
| 1320 |
|
|
|
| 1321 |
|
|
current_state <= S_PC_5;
|
| 1322 |
|
|
end
|
| 1323 |
|
|
else begin
|
| 1324 |
|
|
CYC_O <= 1'b0;
|
| 1325 |
|
|
STB_O <= 1'b0;
|
| 1326 |
|
|
|
| 1327 |
|
|
prefetch_ir_o <= { prefetch_ir_o[79:48], DAT_I[31:0], 16'b0 };
|
| 1328 |
|
|
|
| 1329 |
|
|
prefetch_ir_valid_32_o <= 1'b1;
|
| 1330 |
|
|
prefetch_ir_valid_o <= 1'b1;
|
| 1331 |
|
|
prefetch_ir_valid_80_o <= 1'b0;
|
| 1332 |
|
|
current_state <= S_INIT;
|
| 1333 |
|
|
end
|
| 1334 |
|
|
end
|
| 1335 |
|
|
else if(RTY_I == 1'b1) begin
|
| 1336 |
|
|
CYC_O <= 1'b0;
|
| 1337 |
|
|
STB_O <= 1'b0;
|
| 1338 |
|
|
|
| 1339 |
|
|
current_state <= S_PC_4;
|
| 1340 |
|
|
end
|
| 1341 |
|
|
else if(ERR_I == 1'b1) begin
|
| 1342 |
|
|
CYC_O <= 1'b0;
|
| 1343 |
|
|
STB_O <= 1'b0;
|
| 1344 |
|
|
|
| 1345 |
|
|
fault_address_state_o <= { ADR_O, 2'b00 };
|
| 1346 |
|
|
rw_state_o <= ~WE_O;
|
| 1347 |
|
|
fc_state_o <= fc_o;
|
| 1348 |
|
|
interrupt_trap_o <= VECTOR_BUS_TRAP;
|
| 1349 |
|
|
|
| 1350 |
|
|
jmp_bus_trap_o <= 1'b1;
|
| 1351 |
|
|
current_state <= S_WAIT;
|
| 1352 |
|
|
end
|
| 1353 |
|
|
end
|
| 1354 |
|
|
S_PC_4: begin
|
| 1355 |
|
|
CYC_O <= 1'b1;
|
| 1356 |
|
|
STB_O <= 1'b1;
|
| 1357 |
|
|
|
| 1358 |
|
|
current_state <= S_PC_3;
|
| 1359 |
|
|
end
|
| 1360 |
|
|
S_PC_5: begin
|
| 1361 |
|
|
if(ACK_I == 1'b1) begin
|
| 1362 |
|
|
CYC_O <= 1'b0;
|
| 1363 |
|
|
STB_O <= 1'b0;
|
| 1364 |
|
|
|
| 1365 |
|
|
prefetch_ir_o <= { prefetch_ir_o[79:32], DAT_I[31:0] };
|
| 1366 |
|
|
|
| 1367 |
|
|
prefetch_ir_valid_32_o <= 1'b1;
|
| 1368 |
|
|
prefetch_ir_valid_o <= 1'b1;
|
| 1369 |
|
|
prefetch_ir_valid_80_o <= 1'b1;
|
| 1370 |
|
|
current_state <= S_INIT;
|
| 1371 |
|
|
end
|
| 1372 |
|
|
else if(RTY_I == 1'b1) begin
|
| 1373 |
|
|
CYC_O <= 1'b0;
|
| 1374 |
|
|
STB_O <= 1'b0;
|
| 1375 |
|
|
|
| 1376 |
|
|
current_state <= S_PC_6;
|
| 1377 |
|
|
end
|
| 1378 |
|
|
else if(ERR_I == 1'b1) begin
|
| 1379 |
|
|
CYC_O <= 1'b0;
|
| 1380 |
|
|
STB_O <= 1'b0;
|
| 1381 |
|
|
|
| 1382 |
|
|
fault_address_state_o <= { ADR_O, 2'b00 };
|
| 1383 |
|
|
rw_state_o <= ~WE_O;
|
| 1384 |
|
|
fc_state_o <= fc_o;
|
| 1385 |
|
|
interrupt_trap_o <= VECTOR_BUS_TRAP;
|
| 1386 |
|
|
|
| 1387 |
|
|
jmp_bus_trap_o <= 1'b1;
|
| 1388 |
|
|
current_state <= S_WAIT;
|
| 1389 |
|
|
end
|
| 1390 |
|
|
end
|
| 1391 |
|
|
S_PC_6: begin
|
| 1392 |
|
|
CYC_O <= 1'b1;
|
| 1393 |
|
|
STB_O <= 1'b1;
|
| 1394 |
|
|
|
| 1395 |
|
|
current_state <= S_PC_5;
|
| 1396 |
|
|
end
|
| 1397 |
|
|
|
| 1398 |
|
|
//*******************
|
| 1399 |
|
|
S_READ_1: begin
|
| 1400 |
|
|
if(ACK_I == 1'b1) begin
|
| 1401 |
|
|
if(address_i[1:0] == 2'b10 && size_i == 2'b10) begin
|
| 1402 |
|
|
//CYC_O <= 1'b1;
|
| 1403 |
|
|
ADR_O <= address_i_plus_4[31:2];
|
| 1404 |
|
|
SEL_O <= 4'b1100;
|
| 1405 |
|
|
//STB_O <= 1'b1;
|
| 1406 |
|
|
//WE_O <= 1'b0;
|
| 1407 |
|
|
|
| 1408 |
|
|
//SGL_O <= 1'b0;
|
| 1409 |
|
|
//BLK_O <= 1'b1;
|
| 1410 |
|
|
//RMW_O <= 1'b0;
|
| 1411 |
|
|
CTI_O <= CTI_END_OF_BURST;
|
| 1412 |
|
|
|
| 1413 |
|
|
//if(supervisor_i == 1'b1) fc_o <= (address_type_i == 1'b0) ? FC_SUPERVISOR_DATA : FC_SUPERVISOR_PROGRAM;
|
| 1414 |
|
|
//else fc_o <= (address_type_i == 1'b0) ? FC_USER_DATA : FC_USER_PROGRAM;
|
| 1415 |
|
|
|
| 1416 |
|
|
data_read_o <= { DAT_I[15:0], 16'b0 };
|
| 1417 |
|
|
|
| 1418 |
|
|
current_state <= S_READ_2;
|
| 1419 |
|
|
end
|
| 1420 |
|
|
else begin
|
| 1421 |
|
|
if(read_modify_write_i == 1'b1) begin
|
| 1422 |
|
|
CYC_O <= 1'b1;
|
| 1423 |
|
|
STB_O <= 1'b0;
|
| 1424 |
|
|
end
|
| 1425 |
|
|
else begin
|
| 1426 |
|
|
CYC_O <= 1'b0;
|
| 1427 |
|
|
STB_O <= 1'b0;
|
| 1428 |
|
|
end
|
| 1429 |
|
|
|
| 1430 |
|
|
if(address_i[1:0] == 2'b00 && size_i == 2'b10) data_read_o <= DAT_I[31:0];
|
| 1431 |
|
|
else if(address_i[1:0] == 2'b10 && size_i == 2'b01) data_read_o <= { {16{DAT_I[15]}}, DAT_I[15:0] };
|
| 1432 |
|
|
else if(address_i[1:0] == 2'b00 && size_i == 2'b01) data_read_o <= { {16{DAT_I[31]}}, DAT_I[31:16] };
|
| 1433 |
|
|
else if(address_i[1:0] == 2'b11 && size_i == 2'b00) data_read_o <= { {24{DAT_I[7]}}, DAT_I[7:0] };
|
| 1434 |
|
|
else if(address_i[1:0] == 2'b10 && size_i == 2'b00) data_read_o <= { {24{DAT_I[15]}}, DAT_I[15:8] };
|
| 1435 |
|
|
else if(address_i[1:0] == 2'b01 && size_i == 2'b00) data_read_o <= { {24{DAT_I[23]}}, DAT_I[23:16] };
|
| 1436 |
|
|
else if(address_i[1:0] == 2'b00 && size_i == 2'b00) data_read_o <= { {24{DAT_I[31]}}, DAT_I[31:24] };
|
| 1437 |
|
|
|
| 1438 |
|
|
finished_o <= 1'b1;
|
| 1439 |
|
|
current_state <= S_WAIT;
|
| 1440 |
|
|
end
|
| 1441 |
|
|
end
|
| 1442 |
|
|
else if(RTY_I == 1'b1) begin
|
| 1443 |
|
|
CYC_O <= 1'b0;
|
| 1444 |
|
|
STB_O <= 1'b0;
|
| 1445 |
|
|
|
| 1446 |
|
|
current_state <= S_INIT;
|
| 1447 |
|
|
end
|
| 1448 |
|
|
else if(ERR_I == 1'b1) begin
|
| 1449 |
|
|
CYC_O <= 1'b0;
|
| 1450 |
|
|
STB_O <= 1'b0;
|
| 1451 |
|
|
|
| 1452 |
|
|
fault_address_state_o <= { ADR_O, 2'b00 };
|
| 1453 |
|
|
rw_state_o <= ~WE_O;
|
| 1454 |
|
|
fc_state_o <= fc_o;
|
| 1455 |
|
|
interrupt_trap_o <= VECTOR_BUS_TRAP;
|
| 1456 |
|
|
|
| 1457 |
|
|
jmp_bus_trap_o <= 1'b1;
|
| 1458 |
|
|
current_state <= S_WAIT;
|
| 1459 |
|
|
end
|
| 1460 |
|
|
end
|
| 1461 |
|
|
S_READ_2: begin
|
| 1462 |
|
|
if(ACK_I == 1'b1) begin
|
| 1463 |
|
|
CYC_O <= 1'b0;
|
| 1464 |
|
|
STB_O <= 1'b0;
|
| 1465 |
|
|
|
| 1466 |
|
|
data_read_o <= { data_read_o[31:16], DAT_I[31:16] };
|
| 1467 |
|
|
|
| 1468 |
|
|
finished_o <= 1'b1;
|
| 1469 |
|
|
current_state <= S_WAIT;
|
| 1470 |
|
|
|
| 1471 |
|
|
end
|
| 1472 |
|
|
else if(RTY_I == 1'b1) begin
|
| 1473 |
|
|
CYC_O <= 1'b0;
|
| 1474 |
|
|
STB_O <= 1'b0;
|
| 1475 |
|
|
|
| 1476 |
|
|
current_state <= S_READ_3;
|
| 1477 |
|
|
end
|
| 1478 |
|
|
else if(ERR_I == 1'b1) begin
|
| 1479 |
|
|
CYC_O <= 1'b0;
|
| 1480 |
|
|
STB_O <= 1'b0;
|
| 1481 |
|
|
|
| 1482 |
|
|
fault_address_state_o <= { ADR_O, 2'b00 };
|
| 1483 |
|
|
rw_state_o <= ~WE_O;
|
| 1484 |
|
|
fc_state_o <= fc_o;
|
| 1485 |
|
|
interrupt_trap_o <= VECTOR_BUS_TRAP;
|
| 1486 |
|
|
|
| 1487 |
|
|
jmp_bus_trap_o <= 1'b1;
|
| 1488 |
|
|
current_state <= S_WAIT;
|
| 1489 |
|
|
end
|
| 1490 |
|
|
|
| 1491 |
|
|
end
|
| 1492 |
|
|
S_READ_3: begin
|
| 1493 |
|
|
CYC_O <= 1'b1;
|
| 1494 |
|
|
STB_O <= 1'b1;
|
| 1495 |
|
|
|
| 1496 |
|
|
current_state <= S_READ_2;
|
| 1497 |
|
|
end
|
| 1498 |
|
|
|
| 1499 |
|
|
|
| 1500 |
|
|
S_WAIT: begin
|
| 1501 |
|
|
jmp_address_trap_o <= 1'b0;
|
| 1502 |
|
|
jmp_bus_trap_o <= 1'b0;
|
| 1503 |
|
|
|
| 1504 |
|
|
if(do_read_i == 1'b0 && do_write_i == 1'b0 && do_interrupt_i == 1'b0 && do_reset_i == 1'b0) begin
|
| 1505 |
|
|
finished_o <= 1'b0;
|
| 1506 |
|
|
current_state <= S_INIT;
|
| 1507 |
|
|
end
|
| 1508 |
|
|
end
|
| 1509 |
|
|
|
| 1510 |
|
|
//**********************
|
| 1511 |
|
|
S_WRITE_1: begin
|
| 1512 |
|
|
if(ACK_I == 1'b1) begin
|
| 1513 |
|
|
if(address_i[1:0] == 2'b10 && size_i == 2'b10) begin
|
| 1514 |
|
|
//CYC_O <= 1'b1;
|
| 1515 |
|
|
ADR_O <= address_i_plus_4[31:2];
|
| 1516 |
|
|
//STB_O <= 1'b1;
|
| 1517 |
|
|
//WE_O <= 1'b1;
|
| 1518 |
|
|
|
| 1519 |
|
|
DAT_O <= { data_write_i[15:0], 16'b0 };
|
| 1520 |
|
|
SEL_O <= 4'b1100;
|
| 1521 |
|
|
|
| 1522 |
|
|
//SGL_O <= 1'b0;
|
| 1523 |
|
|
//BLK_O <= 1'b1;
|
| 1524 |
|
|
//RMW_O <= 1'b0;
|
| 1525 |
|
|
CTI_O <= CTI_END_OF_BURST;
|
| 1526 |
|
|
|
| 1527 |
|
|
//if(supervisor_i == 1'b1) fc_o <= FC_SUPERVISOR_DATA;
|
| 1528 |
|
|
//else fc_o <= FC_USER_DATA;
|
| 1529 |
|
|
|
| 1530 |
|
|
current_state <= S_WRITE_2;
|
| 1531 |
|
|
end
|
| 1532 |
|
|
else begin
|
| 1533 |
|
|
CYC_O <= 1'b0;
|
| 1534 |
|
|
STB_O <= 1'b0;
|
| 1535 |
|
|
|
| 1536 |
|
|
finished_o <= 1'b1;
|
| 1537 |
|
|
current_state <= S_WAIT;
|
| 1538 |
|
|
end
|
| 1539 |
|
|
end
|
| 1540 |
|
|
else if(RTY_I == 1'b1) begin
|
| 1541 |
|
|
CYC_O <= 1'b0;
|
| 1542 |
|
|
STB_O <= 1'b0;
|
| 1543 |
|
|
|
| 1544 |
|
|
current_state <= S_INIT;
|
| 1545 |
|
|
end
|
| 1546 |
|
|
else if(ERR_I == 1'b1) begin
|
| 1547 |
|
|
CYC_O <= 1'b0;
|
| 1548 |
|
|
STB_O <= 1'b0;
|
| 1549 |
|
|
|
| 1550 |
|
|
fault_address_state_o <= { ADR_O, 2'b00 };
|
| 1551 |
|
|
rw_state_o <= ~WE_O;
|
| 1552 |
|
|
fc_state_o <= fc_o;
|
| 1553 |
|
|
interrupt_trap_o <= VECTOR_BUS_TRAP;
|
| 1554 |
|
|
|
| 1555 |
|
|
jmp_bus_trap_o <= 1'b1;
|
| 1556 |
|
|
current_state <= S_WAIT;
|
| 1557 |
|
|
end
|
| 1558 |
|
|
|
| 1559 |
|
|
end
|
| 1560 |
|
|
S_WRITE_2: begin
|
| 1561 |
|
|
if(ACK_I == 1'b1) begin
|
| 1562 |
|
|
CYC_O <= 1'b0;
|
| 1563 |
|
|
STB_O <= 1'b0;
|
| 1564 |
|
|
|
| 1565 |
|
|
finished_o <= 1'b1;
|
| 1566 |
|
|
current_state <= S_WAIT;
|
| 1567 |
|
|
|
| 1568 |
|
|
end
|
| 1569 |
|
|
else if(RTY_I == 1'b1) begin
|
| 1570 |
|
|
CYC_O <= 1'b0;
|
| 1571 |
|
|
STB_O <= 1'b0;
|
| 1572 |
|
|
|
| 1573 |
|
|
current_state <= S_WRITE_3;
|
| 1574 |
|
|
end
|
| 1575 |
|
|
else if(ERR_I == 1'b1) begin
|
| 1576 |
|
|
CYC_O <= 1'b0;
|
| 1577 |
|
|
STB_O <= 1'b0;
|
| 1578 |
|
|
|
| 1579 |
|
|
fault_address_state_o <= { ADR_O, 2'b00 };
|
| 1580 |
|
|
rw_state_o <= ~WE_O;
|
| 1581 |
|
|
fc_state_o <= fc_o;
|
| 1582 |
|
|
interrupt_trap_o <= VECTOR_BUS_TRAP;
|
| 1583 |
|
|
|
| 1584 |
|
|
jmp_bus_trap_o <= 1'b1;
|
| 1585 |
|
|
current_state <= S_WAIT;
|
| 1586 |
|
|
end
|
| 1587 |
|
|
|
| 1588 |
|
|
end
|
| 1589 |
|
|
S_WRITE_3: begin
|
| 1590 |
|
|
CYC_O <= 1'b1;
|
| 1591 |
|
|
STB_O <= 1'b1;
|
| 1592 |
|
|
|
| 1593 |
|
|
current_state <= S_WRITE_2;
|
| 1594 |
|
|
end
|
| 1595 |
|
|
|
| 1596 |
|
|
endcase
|
| 1597 |
|
|
end
|
| 1598 |
|
|
end
|
| 1599 |
|
|
|
| 1600 |
|
|
endmodule
|
| 1601 |
|
|
|
| 1602 |
|
|
/***********************************************************************************************************************
|
| 1603 |
|
|
* Registers
|
| 1604 |
|
|
**********************************************************************************************************************/
|
| 1605 |
|
|
|
| 1606 |
|
|
/*! \brief Microcode controlled registers.
|
| 1607 |
|
|
*
|
| 1608 |
|
|
* Most of the ao68000 IP core registers are located in this module. At every clock cycle the microcode controls what
|
| 1609 |
|
|
* to save into these registers. Some of the more important registers include:
|
| 1610 |
|
|
* - operand1, operand2 registers are inputs to the ALU,
|
| 1611 |
|
|
* - address, size, do_read_flag, do_write_flag, do_interrupt_flag registers tell the bus_control module what kind
|
| 1612 |
|
|
* of bus cycle to perform,
|
| 1613 |
|
|
* - pc register stores the current program counter,
|
| 1614 |
|
|
* - ir register stores the current instruction word,
|
| 1615 |
|
|
* - ea_mod, ea_type registers store the currently selected addressing mode.
|
| 1616 |
|
|
*/
|
| 1617 |
|
|
module registers(
|
| 1618 |
|
|
input clock,
|
| 1619 |
|
|
input reset_n,
|
| 1620 |
|
|
|
| 1621 |
|
|
input [31:0] data_read,
|
| 1622 |
|
|
input [79:0] prefetch_ir,
|
| 1623 |
|
|
input prefetch_ir_valid,
|
| 1624 |
|
|
input [31:0] result,
|
| 1625 |
|
|
input [15:0] sr,
|
| 1626 |
|
|
input rw_state,
|
| 1627 |
|
|
input [2:0] fc_state,
|
| 1628 |
|
|
input [31:0] fault_address_state,
|
| 1629 |
|
|
input [7:0] interrupt_trap,
|
| 1630 |
|
|
input [2:0] interrupt_mask,
|
| 1631 |
|
|
input [7:0] decoder_trap,
|
| 1632 |
|
|
|
| 1633 |
|
|
input [31:0] usp,
|
| 1634 |
|
|
input [31:0] Dn_output,
|
| 1635 |
|
|
input [31:0] An_output,
|
| 1636 |
|
|
|
| 1637 |
|
|
output [1:0] pc_change,
|
| 1638 |
|
|
|
| 1639 |
|
|
output reg [2:0] ea_reg,
|
| 1640 |
|
|
input [2:0] ea_reg_control,
|
| 1641 |
|
|
|
| 1642 |
|
|
output reg [2:0] ea_mod,
|
| 1643 |
|
|
input [3:0] ea_mod_control,
|
| 1644 |
|
|
|
| 1645 |
|
|
output reg [3:0] ea_type,
|
| 1646 |
|
|
input [3:0] ea_type_control,
|
| 1647 |
|
|
|
| 1648 |
|
|
// for DIVU/DIVS simulation, register must be not zero
|
| 1649 |
|
|
output reg [31:0] operand1 = 32'hFFFFFFFF,
|
| 1650 |
|
|
input [3:0] operand1_control,
|
| 1651 |
|
|
|
| 1652 |
|
|
output reg [31:0] operand2 = 32'hFFFFFFFF,
|
| 1653 |
|
|
input [2:0] operand2_control,
|
| 1654 |
|
|
|
| 1655 |
|
|
output reg [31:0] address,
|
| 1656 |
|
|
output reg address_type,
|
| 1657 |
|
|
input [3:0] address_control,
|
| 1658 |
|
|
|
| 1659 |
|
|
output reg [1:0] size,
|
| 1660 |
|
|
input [3:0] size_control,
|
| 1661 |
|
|
|
| 1662 |
|
|
output reg [5:0] movem_modreg,
|
| 1663 |
|
|
input [2:0] movem_modreg_control,
|
| 1664 |
|
|
|
| 1665 |
|
|
output reg [4:0] movem_loop,
|
| 1666 |
|
|
input [1:0] movem_loop_control,
|
| 1667 |
|
|
|
| 1668 |
|
|
output reg [15:0] movem_reg,
|
| 1669 |
|
|
input [1:0] movem_reg_control,
|
| 1670 |
|
|
|
| 1671 |
|
|
output reg [15:0] ir,
|
| 1672 |
|
|
input [1:0] ir_control,
|
| 1673 |
|
|
|
| 1674 |
|
|
output reg [31:0] pc,
|
| 1675 |
|
|
input [2:0] pc_control,
|
| 1676 |
|
|
|
| 1677 |
|
|
output reg [7:0] trap,
|
| 1678 |
|
|
input [3:0] trap_control,
|
| 1679 |
|
|
|
| 1680 |
|
|
output reg [31:0] offset,
|
| 1681 |
|
|
input [1:0] offset_control,
|
| 1682 |
|
|
|
| 1683 |
|
|
output reg [31:0] index,
|
| 1684 |
|
|
input [1:0] index_control,
|
| 1685 |
|
|
|
| 1686 |
|
|
|
| 1687 |
|
|
output reg stop_flag,
|
| 1688 |
|
|
input [1:0] stop_flag_control,
|
| 1689 |
|
|
|
| 1690 |
|
|
output reg trace_flag,
|
| 1691 |
|
|
input [1:0] trace_flag_control,
|
| 1692 |
|
|
|
| 1693 |
|
|
output reg group_0_flag,
|
| 1694 |
|
|
input [1:0] group_0_flag_control,
|
| 1695 |
|
|
|
| 1696 |
|
|
output reg instruction_flag,
|
| 1697 |
|
|
input [1:0] instruction_flag_control,
|
| 1698 |
|
|
|
| 1699 |
|
|
output reg read_modify_write_flag,
|
| 1700 |
|
|
input [1:0] read_modify_write_flag_control,
|
| 1701 |
|
|
|
| 1702 |
|
|
output reg do_reset_flag,
|
| 1703 |
|
|
input [1:0] do_reset_flag_control,
|
| 1704 |
|
|
|
| 1705 |
|
|
output reg do_interrupt_flag,
|
| 1706 |
|
|
input [1:0] do_interrupt_flag_control,
|
| 1707 |
|
|
|
| 1708 |
|
|
output reg do_read_flag,
|
| 1709 |
|
|
input [1:0] do_read_flag_control,
|
| 1710 |
|
|
|
| 1711 |
|
|
output reg do_write_flag,
|
| 1712 |
|
|
input [1:0] do_write_flag_control,
|
| 1713 |
|
|
|
| 1714 |
|
|
output reg do_blocked_flag,
|
| 1715 |
|
|
input [1:0] do_blocked_flag_control,
|
| 1716 |
|
|
|
| 1717 |
|
|
output reg [31:0] data_write,
|
| 1718 |
|
|
input [1:0] data_write_control,
|
| 1719 |
|
|
|
| 1720 |
|
|
|
| 1721 |
|
|
output [3:0] An_address,
|
| 1722 |
|
|
input [1:0] An_address_control,
|
| 1723 |
|
|
|
| 1724 |
|
|
output [31:0] An_input,
|
| 1725 |
|
|
input [1:0] An_input_control,
|
| 1726 |
|
|
|
| 1727 |
|
|
output [2:0] Dn_address,
|
| 1728 |
|
|
input Dn_address_control
|
| 1729 |
|
|
);
|
| 1730 |
|
|
|
| 1731 |
|
|
reg [31:0] pc_valid;
|
| 1732 |
|
|
|
| 1733 |
|
|
// pc_change connected
|
| 1734 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1735 |
|
|
if(reset_n == 1'b0) begin
|
| 1736 |
|
|
pc <= 32'd0;
|
| 1737 |
|
|
pc_valid <= 32'd0;
|
| 1738 |
|
|
end
|
| 1739 |
|
|
else begin
|
| 1740 |
|
|
if(pc_control == `PC_FROM_RESULT) pc = result;
|
| 1741 |
|
|
else if(pc_control == `PC_INCR_BY_2) pc = pc + 32'd2;
|
| 1742 |
|
|
else if(pc_control == `PC_INCR_BY_4) pc = pc + 32'd4;
|
| 1743 |
|
|
else if(pc_control == `PC_INCR_BY_SIZE) pc = (size == 2'b00 || size == 2'b01) ? pc + 32'd2 : pc + 32'd4;
|
| 1744 |
|
|
else if(pc_control == `PC_FROM_PREFETCH_IR) pc = prefetch_ir[47:16];
|
| 1745 |
|
|
else if(pc_control == `PC_INCR_BY_2_IN_MAIN_LOOP && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0 && stop_flag == 1'b0)
|
| 1746 |
|
|
pc = pc + 32'd2;
|
| 1747 |
|
|
if(pc[0] == 1'b0) pc_valid <= pc;
|
| 1748 |
|
|
end
|
| 1749 |
|
|
end
|
| 1750 |
|
|
|
| 1751 |
|
|
assign pc_change =
|
| 1752 |
|
|
( pc_control == `PC_FROM_RESULT || pc_control == `PC_FROM_PREFETCH_IR
|
| 1753 |
|
|
) ? 2'b11 :
|
| 1754 |
|
|
( pc_control == `PC_INCR_BY_4 || (pc_control == `PC_INCR_BY_SIZE && size == 2'b10)
|
| 1755 |
|
|
) ? 2'b10 :
|
| 1756 |
|
|
( pc_control == `PC_INCR_BY_2 || (pc_control == `PC_INCR_BY_SIZE && (size == 2'b00 || size == 2'b01)) ||
|
| 1757 |
|
|
(pc_control == `PC_INCR_BY_2_IN_MAIN_LOOP && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0 && stop_flag == 1'b0)
|
| 1758 |
|
|
) ? 2'b01 :
|
| 1759 |
|
|
2'b00;
|
| 1760 |
|
|
|
| 1761 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1762 |
|
|
if(reset_n == 1'b0) size <= 2'b00;
|
| 1763 |
|
|
else if(size_control == `SIZE_BYTE) size <= 2'b00;
|
| 1764 |
|
|
else if(size_control == `SIZE_WORD) size <= 2'b01;
|
| 1765 |
|
|
else if(size_control == `SIZE_LONG) size <= 2'b10;
|
| 1766 |
|
|
else if(size_control == `SIZE_1) size <= ( ir[7:6] == 2'b00 ) ? 2'b01 : 2'b10;
|
| 1767 |
|
|
else if(size_control == `SIZE_1_PLUS) size <= ( ir[7:6] == 2'b10 ) ? 2'b01 : 2'b10;
|
| 1768 |
|
|
else if(size_control == `SIZE_2) size <= ( ir[6] == 1'b0 ) ? 2'b01 : 2'b10;
|
| 1769 |
|
|
else if(size_control == `SIZE_3) size <= ( ir[7:6] == 2'b00 ) ? 2'b00 : ( ( ir[7:6] == 2'b01 ) ? 2'b01 : 2'b10 );
|
| 1770 |
|
|
else if(size_control == `SIZE_4) size <= ( ir[13:12] == 2'b01 ) ? 2'b00 : ( ( ir[13:12] == 2'b11 ) ? 2'b01 : 2'b10 );
|
| 1771 |
|
|
else if(size_control == `SIZE_5) size <= ( ir[8] == 1'b0 ) ? 2'b01 : 2'b10;
|
| 1772 |
|
|
else if(size_control == `SIZE_6) size <= ( ir[5:3] != 3'b000 ) ? 2'b00 : 2'b10;
|
| 1773 |
|
|
end
|
| 1774 |
|
|
|
| 1775 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1776 |
|
|
if(reset_n == 1'b0) ea_reg <= 3'b000;
|
| 1777 |
|
|
else if(ea_reg_control == `EA_REG_IR_2_0) ea_reg <= ir[2:0];
|
| 1778 |
|
|
else if(ea_reg_control == `EA_REG_IR_11_9) ea_reg <= ir[11:9];
|
| 1779 |
|
|
else if(ea_reg_control == `EA_REG_MOVEM_REG_2_0) ea_reg <= movem_modreg[2:0];
|
| 1780 |
|
|
else if(ea_reg_control == `EA_REG_3b111) ea_reg <= 3'b111;
|
| 1781 |
|
|
else if(ea_reg_control == `EA_REG_3b100) ea_reg <= 3'b100;
|
| 1782 |
|
|
end
|
| 1783 |
|
|
|
| 1784 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1785 |
|
|
if(reset_n == 1'b0) ea_mod <= 3'b000;
|
| 1786 |
|
|
else if(ea_mod_control == `EA_MOD_IR_5_3) ea_mod <= ir[5:3];
|
| 1787 |
|
|
else if(ea_mod_control == `EA_MOD_MOVEM_MOD_5_3) ea_mod <= movem_modreg[5:3];
|
| 1788 |
|
|
else if(ea_mod_control == `EA_MOD_IR_8_6) ea_mod <= ir[8:6];
|
| 1789 |
|
|
else if(ea_mod_control == `EA_MOD_PREDEC) ea_mod <= 3'b100;
|
| 1790 |
|
|
else if(ea_mod_control == `EA_MOD_3b111) ea_mod <= 3'b111;
|
| 1791 |
|
|
else if(ea_mod_control == `EA_MOD_DN_PREDEC) ea_mod <= (ir[3] == 1'b0) ? /* Dn */ 3'b000 : /* -(An) */ 3'b100;
|
| 1792 |
|
|
else if(ea_mod_control == `EA_MOD_DN_AN_EXG) ea_mod <= (ir[7:3] == 5'b01000 || ir[7:3] == 5'b10001) ? /* Dn */ 3'b000 : /* An */ 3'b001;
|
| 1793 |
|
|
else if(ea_mod_control == `EA_MOD_POSTINC) ea_mod <= 3'b011;
|
| 1794 |
|
|
else if(ea_mod_control == `EA_MOD_AN) ea_mod <= 3'b001;
|
| 1795 |
|
|
else if(ea_mod_control == `EA_MOD_DN) ea_mod <= 3'b000;
|
| 1796 |
|
|
else if(ea_mod_control == `EA_MOD_INDIRECTOFFSET) ea_mod <= 3'b101;
|
| 1797 |
|
|
end
|
| 1798 |
|
|
|
| 1799 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1800 |
|
|
if(reset_n == 1'b0) ea_type <= `EA_TYPE_IDLE;
|
| 1801 |
|
|
else if(ea_type_control == `EA_TYPE_ALL) ea_type <= `EA_TYPE_ALL;
|
| 1802 |
|
|
else if(ea_type_control == `EA_TYPE_CONTROL_POSTINC) ea_type <= `EA_TYPE_CONTROL_POSTINC;
|
| 1803 |
|
|
else if(ea_type_control == `EA_TYPE_CONTROLALTER_PREDEC) ea_type <= `EA_TYPE_CONTROLALTER_PREDEC;
|
| 1804 |
|
|
else if(ea_type_control == `EA_TYPE_CONTROL) ea_type <= `EA_TYPE_CONTROL;
|
| 1805 |
|
|
else if(ea_type_control == `EA_TYPE_DATAALTER) ea_type <= `EA_TYPE_DATAALTER;
|
| 1806 |
|
|
else if(ea_type_control == `EA_TYPE_DN_AN) ea_type <= `EA_TYPE_DN_AN;
|
| 1807 |
|
|
else if(ea_type_control == `EA_TYPE_MEMORYALTER) ea_type <= `EA_TYPE_MEMORYALTER;
|
| 1808 |
|
|
else if(ea_type_control == `EA_TYPE_DATA) ea_type <= `EA_TYPE_DATA;
|
| 1809 |
|
|
end
|
| 1810 |
|
|
|
| 1811 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1812 |
|
|
if(reset_n == 1'b0) operand1 <= 32'hFFFFFFFF;
|
| 1813 |
|
|
else if(operand1_control == `OP1_FROM_OP2) operand1 <= operand2;
|
| 1814 |
|
|
else if(operand1_control == `OP1_FROM_ADDRESS) operand1 <= address;
|
| 1815 |
|
|
else if(operand1_control == `OP1_FROM_DATA) operand1 <=
|
| 1816 |
|
|
(size == 2'b00) ? { {24{data_read[7]}}, data_read[7:0] } :
|
| 1817 |
|
|
(size == 2'b01) ? { {16{data_read[15]}}, data_read[15:0] } :
|
| 1818 |
|
|
data_read[31:0];
|
| 1819 |
|
|
else if(operand1_control == `OP1_FROM_IMMEDIATE) operand1 <=
|
| 1820 |
|
|
(size == 2'b00) ? { {24{prefetch_ir[71]}}, prefetch_ir[71:64] } :
|
| 1821 |
|
|
(size == 2'b01) ? { {16{prefetch_ir[79]}}, prefetch_ir[79:64] } :
|
| 1822 |
|
|
prefetch_ir[79:48];
|
| 1823 |
|
|
else if(operand1_control == `OP1_FROM_RESULT) operand1 <= result;
|
| 1824 |
|
|
else if(operand1_control == `OP1_MOVEQ) operand1 <= { {24{ir[7]}}, ir[7:0] };
|
| 1825 |
|
|
else if(operand1_control == `OP1_FROM_PC) operand1 <= pc_valid;
|
| 1826 |
|
|
else if(operand1_control == `OP1_LOAD_ZEROS) operand1 <= 32'b0;
|
| 1827 |
|
|
else if(operand1_control == `OP1_LOAD_ONES) operand1 <= 32'hFFFFFFFF;
|
| 1828 |
|
|
else if(operand1_control == `OP1_FROM_SR) operand1 <= { 16'b0, sr[15], 1'b0, sr[13], 2'b0, sr[10:8], 3'b0, sr[4:0] };
|
| 1829 |
|
|
else if(operand1_control == `OP1_FROM_USP) operand1 <= usp;
|
| 1830 |
|
|
else if(operand1_control == `OP1_FROM_AN) operand1 <=
|
| 1831 |
|
|
(size == 2'b01) ? { {16{An_output[15]}}, An_output[15:0] } :
|
| 1832 |
|
|
An_output[31:0];
|
| 1833 |
|
|
else if(operand1_control == `OP1_FROM_DN) operand1 <=
|
| 1834 |
|
|
(size == 2'b00) ? { {24{Dn_output[7]}}, Dn_output[7:0] } :
|
| 1835 |
|
|
(size == 2'b01) ? { {16{Dn_output[15]}}, Dn_output[15:0] } :
|
| 1836 |
|
|
Dn_output[31:0];
|
| 1837 |
|
|
else if(operand1_control == `OP1_FROM_IR) operand1 <= { 16'b0, ir[15:0] };
|
| 1838 |
|
|
else if(operand1_control == `OP1_FROM_FAULT_ADDRESS) operand1 <= fault_address_state;
|
| 1839 |
|
|
end
|
| 1840 |
|
|
|
| 1841 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1842 |
|
|
if(reset_n == 1'b0) operand2 <= 32'hFFFFFFFF;
|
| 1843 |
|
|
else if(operand2_control == `OP2_FROM_OP1) operand2 <= operand1;
|
| 1844 |
|
|
else if(operand2_control == `OP2_LOAD_1) operand2 <= 32'd1;
|
| 1845 |
|
|
else if(operand2_control == `OP2_LOAD_COUNT) operand2 <=
|
| 1846 |
|
|
(ir[5] == 1'b0) ? ( (ir[11:9] == 3'b000) ? 32'b1000 : { 29'b0, ir[11:9] } ) :
|
| 1847 |
|
|
{ 26'b0, operand2[5:0] };
|
| 1848 |
|
|
else if(operand2_control == `OP2_ADDQ_SUBQ) operand2 <= (ir[11:9] == 3'b000) ? 32'b1000 : { 29'b0, ir[11:9] };
|
| 1849 |
|
|
else if(operand2_control == `OP2_MOVE_OFFSET) operand2 <= (ir[7:0] == 8'b0) ? operand2[31:0] : { {24{ir[7]}}, ir[7:0] };
|
| 1850 |
|
|
else if(operand2_control == `OP2_MOVE_ADDRESS_BUS_INFO) operand2 <= { 16'b0, 11'b0, rw_state, instruction_flag, fc_state};
|
| 1851 |
|
|
else if(operand2_control == `OP2_DECR_BY_1) operand2 <= operand2 - 32'b1;
|
| 1852 |
|
|
end
|
| 1853 |
|
|
|
| 1854 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1855 |
|
|
if(reset_n == 1'b0) address <= 32'b0;
|
| 1856 |
|
|
else if(address_control == `ADDRESS_INCR_BY_SIZE) address <=
|
| 1857 |
|
|
(size == 2'b00 && ea_reg != 3'b111) ? address + 32'd1 :
|
| 1858 |
|
|
(size == 2'b01 || (size == 2'b00 && ea_reg == 3'b111)) ? address + 32'd2 :
|
| 1859 |
|
|
(size == 2'b10) ? address + 32'd4 :
|
| 1860 |
|
|
address;
|
| 1861 |
|
|
else if(address_control == `ADDRESS_DECR_BY_SIZE) address <=
|
| 1862 |
|
|
(size == 2'b00 && ea_reg != 3'b111) ? address - 32'd1 :
|
| 1863 |
|
|
(size == 2'b01 || (size == 2'b00 && ea_reg == 3'b111)) ? address - 32'd2 :
|
| 1864 |
|
|
(size == 2'b10) ? address - 32'd4 :
|
| 1865 |
|
|
address;
|
| 1866 |
|
|
else if(address_control == `ADDRESS_INCR_BY_2) address <= address + 32'd2;
|
| 1867 |
|
|
else if(address_control == `ADDRESS_FROM_AN_OUTPUT) address <= An_output;
|
| 1868 |
|
|
else if(address_control == `ADDRESS_FROM_BASE_INDEX_OFFSET) address <= address + index + offset;
|
| 1869 |
|
|
else if(address_control == `ADDRESS_FROM_IMM_16) address <= { {16{prefetch_ir[79]}}, prefetch_ir[79:64] };
|
| 1870 |
|
|
else if(address_control == `ADDRESS_FROM_IMM_32) address <= prefetch_ir[79:48];
|
| 1871 |
|
|
else if(address_control == `ADDRESS_FROM_PC_INDEX_OFFSET) address <= pc_valid + index + offset;
|
| 1872 |
|
|
else if(address_control == `ADDRESS_FROM_TRAP) address <= {22'b0, trap[7:0], 2'b0};
|
| 1873 |
|
|
end
|
| 1874 |
|
|
|
| 1875 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1876 |
|
|
if(reset_n == 1'b0) address_type <= 1'b0;
|
| 1877 |
|
|
else if(address_control == `ADDRESS_FROM_PC_INDEX_OFFSET) address_type <= 1'b1;
|
| 1878 |
|
|
else if(address_control != `ADDRESS_IDLE) address_type <= 1'b0;
|
| 1879 |
|
|
end
|
| 1880 |
|
|
|
| 1881 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1882 |
|
|
if(reset_n == 1'b0) movem_modreg <= 6'b0;
|
| 1883 |
|
|
else if(movem_modreg_control == `MOVEM_MODREG_LOAD_0) movem_modreg <= 6'b0;
|
| 1884 |
|
|
else if(movem_modreg_control == `MOVEM_MODREG_LOAD_6b001111)movem_modreg <= 6'b001111;
|
| 1885 |
|
|
else if(movem_modreg_control == `MOVEM_MODREG_INCR_BY_1) movem_modreg <= movem_modreg + 6'd1;
|
| 1886 |
|
|
else if(movem_modreg_control == `MOVEM_MODREG_DECR_BY_1) movem_modreg <= movem_modreg - 6'd1;
|
| 1887 |
|
|
end
|
| 1888 |
|
|
|
| 1889 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1890 |
|
|
if(reset_n == 1'b0) movem_loop <= 5'b0;
|
| 1891 |
|
|
else if(movem_loop_control == `MOVEM_LOOP_LOAD_0) movem_loop <= 5'b0;
|
| 1892 |
|
|
else if(movem_loop_control == `MOVEM_LOOP_INCR_BY_1) movem_loop <= movem_loop + 5'd1;
|
| 1893 |
|
|
end
|
| 1894 |
|
|
|
| 1895 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1896 |
|
|
if(reset_n == 1'b0) movem_reg <= 16'b0;
|
| 1897 |
|
|
else if(movem_reg_control == `MOVEM_REG_FROM_OP1) movem_reg <= operand1[15:0];
|
| 1898 |
|
|
else if(movem_reg_control == `MOVEM_REG_SHIFT_RIGHT) movem_reg <= { 1'b0, movem_reg[15:1] };
|
| 1899 |
|
|
end
|
| 1900 |
|
|
|
| 1901 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1902 |
|
|
if(reset_n == 1'b0) ir <= 16'b0;
|
| 1903 |
|
|
else if(ir_control == `IR_LOAD_WHEN_PREFETCH_VALID && prefetch_ir_valid == 1'b1 && stop_flag == 1'b0)
|
| 1904 |
|
|
ir <= prefetch_ir[79:64];
|
| 1905 |
|
|
end
|
| 1906 |
|
|
|
| 1907 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1908 |
|
|
if(reset_n == 1'b0) trap <= 8'd0;
|
| 1909 |
|
|
else if(trap_control == `TRAP_ILLEGAL_INSTR) trap <= 8'd4;
|
| 1910 |
|
|
else if(trap_control == `TRAP_DIV_BY_ZERO) trap <= 8'd5;
|
| 1911 |
|
|
else if(trap_control == `TRAP_CHK) trap <= 8'd6;
|
| 1912 |
|
|
else if(trap_control == `TRAP_TRAPV) trap <= 8'd7;
|
| 1913 |
|
|
else if(trap_control == `TRAP_PRIVIL_VIOLAT) trap <= 8'd8;
|
| 1914 |
|
|
else if(trap_control == `TRAP_TRACE) trap <= 8'd9;
|
| 1915 |
|
|
else if(trap_control == `TRAP_TRAP) trap <= { 4'b0010, ir[3:0] };
|
| 1916 |
|
|
else if(trap_control == `TRAP_FROM_DECODER) trap <= decoder_trap;
|
| 1917 |
|
|
else if(trap_control == `TRAP_FROM_INTERRUPT) trap <= interrupt_trap;
|
| 1918 |
|
|
end
|
| 1919 |
|
|
|
| 1920 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1921 |
|
|
if(reset_n == 1'b0) offset <= 32'd0;
|
| 1922 |
|
|
else if(offset_control == `OFFSET_IMM_8) offset <= { {24{prefetch_ir[71]}}, prefetch_ir[71:64] };
|
| 1923 |
|
|
else if(offset_control == `OFFSET_IMM_16) offset <= { {16{prefetch_ir[79]}}, prefetch_ir[79:64] };
|
| 1924 |
|
|
end
|
| 1925 |
|
|
|
| 1926 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1927 |
|
|
if(reset_n == 1'b0) index <= 32'd0;
|
| 1928 |
|
|
else if(index_control == `INDEX_0) index <= 32'd0;
|
| 1929 |
|
|
else if(index_control == `INDEX_LOAD_EXTENDED) index <=
|
| 1930 |
|
|
(prefetch_ir[79] == 1'b0) ?
|
| 1931 |
|
|
( (prefetch_ir[75] == 1'b0) ?
|
| 1932 |
|
|
{ {16{Dn_output[15]}}, Dn_output[15:0] } : Dn_output[31:0]
|
| 1933 |
|
|
) :
|
| 1934 |
|
|
( (prefetch_ir[75] == 1'b0) ?
|
| 1935 |
|
|
{ {16{An_output[15]}}, An_output[15:0] } : An_output[31:0]
|
| 1936 |
|
|
);
|
| 1937 |
|
|
end
|
| 1938 |
|
|
|
| 1939 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1940 |
|
|
if(reset_n == 1'b0) stop_flag <= 1'b0;
|
| 1941 |
|
|
else if(stop_flag_control == `STOP_FLAG_SET) stop_flag <= 1'b1;
|
| 1942 |
|
|
else if(stop_flag_control == `STOP_FLAG_CLEAR) stop_flag <= 1'b0;
|
| 1943 |
|
|
end
|
| 1944 |
|
|
|
| 1945 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1946 |
|
|
if(reset_n == 1'b0) trace_flag <= 1'b0;
|
| 1947 |
|
|
else if(trace_flag_control == `TRACE_FLAG_COPY_WHEN_NO_STOP && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0 && stop_flag == 1'b0)
|
| 1948 |
|
|
trace_flag <= sr[15];
|
| 1949 |
|
|
end
|
| 1950 |
|
|
|
| 1951 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1952 |
|
|
if(reset_n == 1'b0) group_0_flag <= 1'b0;
|
| 1953 |
|
|
else if(group_0_flag_control == `GROUP_0_FLAG_SET) group_0_flag <= 1'b1;
|
| 1954 |
|
|
else if(group_0_flag_control == `GROUP_0_FLAG_CLEAR_WHEN_VALID_PREFETCH && prefetch_ir_valid == 1'b1 && stop_flag == 1'b0)
|
| 1955 |
|
|
group_0_flag <= 1'b0;
|
| 1956 |
|
|
end
|
| 1957 |
|
|
|
| 1958 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1959 |
|
|
if(reset_n == 1'b0) instruction_flag <= 1'b0;
|
| 1960 |
|
|
else if(instruction_flag_control == `INSTRUCTION_FLAG_SET) instruction_flag <= 1'b1;
|
| 1961 |
|
|
else if(instruction_flag_control == `INSTRUCTION_FLAG_CLEAR_IN_MAIN_LOOP && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0 && stop_flag == 1'b0)
|
| 1962 |
|
|
instruction_flag <= 1'b0;
|
| 1963 |
|
|
end
|
| 1964 |
|
|
|
| 1965 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1966 |
|
|
if(reset_n == 1'b0) read_modify_write_flag <= 1'b0;
|
| 1967 |
|
|
else if(read_modify_write_flag_control == `READ_MODIFY_WRITE_FLAG_SET) read_modify_write_flag <= 1'b1;
|
| 1968 |
|
|
else if(read_modify_write_flag_control == `READ_MODIFY_WRITE_FLAG_CLEAR) read_modify_write_flag <= 1'b0;
|
| 1969 |
|
|
end
|
| 1970 |
|
|
|
| 1971 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1972 |
|
|
if(reset_n == 1'b0) do_reset_flag <= 1'b0;
|
| 1973 |
|
|
else if(do_reset_flag_control == `DO_RESET_FLAG_SET) do_reset_flag <= 1'b1;
|
| 1974 |
|
|
else if(do_reset_flag_control == `DO_RESET_FLAG_CLEAR) do_reset_flag <= 1'b0;
|
| 1975 |
|
|
end
|
| 1976 |
|
|
|
| 1977 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1978 |
|
|
if(reset_n == 1'b0) do_interrupt_flag <= 1'b0;
|
| 1979 |
|
|
else if(do_interrupt_flag_control == `DO_INTERRUPT_FLAG_SET_IF_ACTIVE) do_interrupt_flag <= (interrupt_mask != 3'b000) ? 1'b1 : 1'b0;
|
| 1980 |
|
|
else if(do_interrupt_flag_control == `DO_INTERRUPT_FLAG_CLEAR) do_interrupt_flag <= 1'b0;
|
| 1981 |
|
|
end
|
| 1982 |
|
|
|
| 1983 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1984 |
|
|
if(reset_n == 1'b0) do_read_flag <= 1'b0;
|
| 1985 |
|
|
else if(do_read_flag_control == `DO_READ_FLAG_SET) do_read_flag <= 1'b1;
|
| 1986 |
|
|
else if(do_read_flag_control == `DO_READ_FLAG_CLEAR) do_read_flag <= 1'b0;
|
| 1987 |
|
|
end
|
| 1988 |
|
|
|
| 1989 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1990 |
|
|
if(reset_n == 1'b0) do_write_flag <= 1'b0;
|
| 1991 |
|
|
else if(do_write_flag_control == `DO_WRITE_FLAG_SET) do_write_flag <= 1'b1;
|
| 1992 |
|
|
else if(do_write_flag_control == `DO_WRITE_FLAG_CLEAR) do_write_flag <= 1'b0;
|
| 1993 |
|
|
end
|
| 1994 |
|
|
|
| 1995 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 1996 |
|
|
if(reset_n == 1'b0) do_blocked_flag <= 1'b0;
|
| 1997 |
|
|
else if(do_blocked_flag_control == `DO_BLOCKED_FLAG_SET) do_blocked_flag <= 1'b1;
|
| 1998 |
|
|
end
|
| 1999 |
|
|
|
| 2000 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 2001 |
|
|
if(reset_n == 1'b0) data_write <= 32'd0;
|
| 2002 |
|
|
else if(data_write_control == `DATA_WRITE_FROM_RESULT) data_write <= result;
|
| 2003 |
|
|
end
|
| 2004 |
|
|
|
| 2005 |
|
|
assign An_address =
|
| 2006 |
|
|
(An_address_control == `AN_ADDRESS_FROM_EXTENDED) ? { sr[13], prefetch_ir[78:76] } :
|
| 2007 |
|
|
(An_address_control == `AN_ADDRESS_USP) ? 4'b0111 :
|
| 2008 |
|
|
(An_address_control == `AN_ADDRESS_SSP) ? 4'b1111 :
|
| 2009 |
|
|
{ sr[13], ea_reg };
|
| 2010 |
|
|
|
| 2011 |
|
|
assign An_input =
|
| 2012 |
|
|
(An_input_control == `AN_INPUT_FROM_ADDRESS) ? address :
|
| 2013 |
|
|
(An_input_control == `AN_INPUT_FROM_PREFETCH_IR) ? prefetch_ir[79:48] :
|
| 2014 |
|
|
result;
|
| 2015 |
|
|
|
| 2016 |
|
|
assign Dn_address = (Dn_address_control == `DN_ADDRESS_FROM_EXTENDED) ? prefetch_ir[78:76] : ea_reg;
|
| 2017 |
|
|
|
| 2018 |
|
|
endmodule
|
| 2019 |
|
|
|
| 2020 |
|
|
/***********************************************************************************************************************
|
| 2021 |
|
|
* Memory registers
|
| 2022 |
|
|
**********************************************************************************************************************/
|
| 2023 |
|
|
|
| 2024 |
|
|
/*! \brief Contains the microcode ROM and D0-D7, A0-A7 registers.
|
| 2025 |
|
|
*
|
| 2026 |
|
|
* The memory_registers module contains:
|
| 2027 |
|
|
* - data and address registers (D0-D7, A0-A7) implemented as an on-chip RAM.
|
| 2028 |
|
|
* - the microcode implemented as an on-chip ROM.
|
| 2029 |
|
|
*
|
| 2030 |
|
|
* Currently this module contains <em>altsyncram</em> instantiations
|
| 2031 |
|
|
* from Altera Megafunction/LPM library.
|
| 2032 |
|
|
*/
|
| 2033 |
|
|
module memory_registers(
|
| 2034 |
|
|
input clock,
|
| 2035 |
|
|
input reset_n,
|
| 2036 |
|
|
|
| 2037 |
|
|
// 0000,0001,0010,0011,0100,0101,0110: A0-A6, 0111: USP, 1111: SSP
|
| 2038 |
|
|
input [3:0] An_address,
|
| 2039 |
|
|
input [31:0] An_input,
|
| 2040 |
|
|
input An_write_enable,
|
| 2041 |
|
|
output [31:0] An_output,
|
| 2042 |
|
|
|
| 2043 |
|
|
output reg [31:0] usp,
|
| 2044 |
|
|
|
| 2045 |
|
|
input [2:0] Dn_address,
|
| 2046 |
|
|
input [31:0] Dn_input,
|
| 2047 |
|
|
input Dn_write_enable,
|
| 2048 |
|
|
// 00: byte, 01: word, 10: long
|
| 2049 |
|
|
input [1:0] Dn_size,
|
| 2050 |
|
|
output [31:0] Dn_output,
|
| 2051 |
|
|
|
| 2052 |
|
|
input [8:0] micro_pc,
|
| 2053 |
|
|
output [87:0] micro_data
|
| 2054 |
|
|
);
|
| 2055 |
|
|
|
| 2056 |
|
|
wire An_ram_write_enable = (An_address == 4'b0111) ? 1'b0 : An_write_enable;
|
| 2057 |
|
|
|
| 2058 |
|
|
wire [31:0] An_ram_output;
|
| 2059 |
|
|
assign An_output = (An_address == 4'b0111) ? usp : An_ram_output;
|
| 2060 |
|
|
|
| 2061 |
|
|
wire [3:0] dn_byteena = (Dn_size == 2'b00) ? 4'b0001 :
|
| 2062 |
|
|
(Dn_size == 2'b01) ? 4'b0011 :
|
| 2063 |
|
|
(Dn_size == 2'b10) ? 4'b1111 :
|
| 2064 |
|
|
4'b0000;
|
| 2065 |
|
|
|
| 2066 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 2067 |
|
|
if(reset_n == 1'b0) usp <= 32'd0;
|
| 2068 |
|
|
else if(An_address == 4'b0111 && An_write_enable) usp <= An_input;
|
| 2069 |
|
|
end
|
| 2070 |
|
|
|
| 2071 |
|
|
// Register set An implemented as RAM.
|
| 2072 |
|
|
altsyncram an_ram_inst(
|
| 2073 |
|
|
.clock0 (clock),
|
| 2074 |
|
|
|
| 2075 |
|
|
.address_a (An_address[2:0]),
|
| 2076 |
|
|
.byteena_a (4'b1111),
|
| 2077 |
|
|
.wren_a (An_ram_write_enable),
|
| 2078 |
|
|
.data_a (An_input),
|
| 2079 |
|
|
.q_a (An_ram_output)
|
| 2080 |
|
|
);
|
| 2081 |
|
|
defparam
|
| 2082 |
|
|
an_ram_inst.operation_mode = "SINGLE_PORT",
|
| 2083 |
|
|
an_ram_inst.width_a = 32,
|
| 2084 |
|
|
an_ram_inst.widthad_a = 3,
|
| 2085 |
|
|
an_ram_inst.width_byteena_a = 4;
|
| 2086 |
|
|
|
| 2087 |
|
|
// Register set Dn implemented as RAM.
|
| 2088 |
|
|
altsyncram dn_ram_inst(
|
| 2089 |
|
|
.clock0 (clock),
|
| 2090 |
|
|
|
| 2091 |
|
|
.address_a (Dn_address),
|
| 2092 |
|
|
.byteena_a (dn_byteena),
|
| 2093 |
|
|
.wren_a (Dn_write_enable),
|
| 2094 |
|
|
.data_a (Dn_input),
|
| 2095 |
|
|
.q_a (Dn_output)
|
| 2096 |
|
|
);
|
| 2097 |
|
|
defparam
|
| 2098 |
|
|
dn_ram_inst.operation_mode = "SINGLE_PORT",
|
| 2099 |
|
|
dn_ram_inst.width_a = 32,
|
| 2100 |
|
|
dn_ram_inst.widthad_a = 3,
|
| 2101 |
|
|
dn_ram_inst.width_byteena_a = 4;
|
| 2102 |
|
|
|
| 2103 |
|
|
// Microcode ROM
|
| 2104 |
|
|
altsyncram micro_rom_inst(
|
| 2105 |
|
|
.clock0 (clock),
|
| 2106 |
|
|
|
| 2107 |
|
|
.address_a (micro_pc),
|
| 2108 |
|
|
.q_a (micro_data)
|
| 2109 |
|
|
);
|
| 2110 |
|
|
defparam
|
| 2111 |
|
|
micro_rom_inst.operation_mode = "ROM",
|
| 2112 |
|
|
micro_rom_inst.width_a = 88,
|
| 2113 |
|
|
micro_rom_inst.widthad_a = 9,
|
| 2114 |
|
|
micro_rom_inst.init_file = "ao68000_microcode.mif";
|
| 2115 |
|
|
|
| 2116 |
|
|
endmodule
|
| 2117 |
|
|
|
| 2118 |
|
|
/***********************************************************************************************************************
|
| 2119 |
|
|
* Instruction decoder
|
| 2120 |
|
|
**********************************************************************************************************************/
|
| 2121 |
|
|
|
| 2122 |
|
|
/*! \brief Decode instruction and addressing mode.
|
| 2123 |
|
|
*
|
| 2124 |
|
|
* The decoder is an instruction and addressing mode decoder. For instructions it takes as input the ir register
|
| 2125 |
|
|
* from the registers module. The output of the decoder, in this case, is a microcode address of the first microcode
|
| 2126 |
|
|
* word that performs the instruction.
|
| 2127 |
|
|
*
|
| 2128 |
|
|
* In case of addressing mode decoding, the output is the address of the first microcode word that performs the operand
|
| 2129 |
|
|
* loading or saving. This address is obtained from the currently selected addressing mode saved in the ea_mod
|
| 2130 |
|
|
* and ea_type registers in the registers module.
|
| 2131 |
|
|
*/
|
| 2132 |
|
|
module decoder(
|
| 2133 |
|
|
input clock,
|
| 2134 |
|
|
input reset_n,
|
| 2135 |
|
|
|
| 2136 |
|
|
input supervisor,
|
| 2137 |
|
|
input [15:0] ir,
|
| 2138 |
|
|
|
| 2139 |
|
|
// zero: no trap
|
| 2140 |
|
|
output [7:0] decoder_trap,
|
| 2141 |
|
|
output [8:0] decoder_micropc,
|
| 2142 |
|
|
|
| 2143 |
|
|
output [8:0] save_ea,
|
| 2144 |
|
|
output [8:0] perform_ea_write,
|
| 2145 |
|
|
output [8:0] perform_ea_read,
|
| 2146 |
|
|
output [8:0] load_ea,
|
| 2147 |
|
|
|
| 2148 |
|
|
input [3:0] ea_type,
|
| 2149 |
|
|
input [2:0] ea_mod,
|
| 2150 |
|
|
input [2:0] ea_reg
|
| 2151 |
|
|
);
|
| 2152 |
|
|
|
| 2153 |
|
|
parameter [7:0]
|
| 2154 |
|
|
NO_TRAP = 8'd0,
|
| 2155 |
|
|
ILLEGAL_INSTRUCTION_TRAP = 8'd4,
|
| 2156 |
|
|
PRIVILEGE_VIOLATION_TRAP = 8'd8,
|
| 2157 |
|
|
ILLEGAL_1010_INSTRUCTION_TRAP = 8'd10,
|
| 2158 |
|
|
ILLEGAL_1111_INSTRUCTION_TRAP = 8'd11;
|
| 2159 |
|
|
|
| 2160 |
|
|
parameter [8:0]
|
| 2161 |
|
|
UNUSED_MICROPC = 9'd0;
|
| 2162 |
|
|
|
| 2163 |
|
|
assign { decoder_trap, decoder_micropc } =
|
| 2164 |
|
|
(reset_n == 1'b0) ? { NO_TRAP, UNUSED_MICROPC } :
|
| 2165 |
|
|
|
| 2166 |
|
|
// Privilege violation and illegal instruction
|
| 2167 |
|
|
|
| 2168 |
|
|
// ANDI to SR,EORI to SR,ORI to SR,RESET,STOP,RTE,MOVE TO SR,MOVE USP TO USP,MOVE USP TO An privileged instructions
|
| 2169 |
|
|
( ( ir[15:0] == 16'b0000_0010_01_111_100 ||
|
| 2170 |
|
|
ir[15:0] == 16'b0000_1010_01_111_100 ||
|
| 2171 |
|
|
ir[15:0] == 16'b0000_0000_01_111_100 ||
|
| 2172 |
|
|
ir[15:0] == 16'b0100_1110_0111_0000 ||
|
| 2173 |
|
|
ir[15:0] == 16'b0100_1110_0111_0010 ||
|
| 2174 |
|
|
ir[15:0] == 16'b0100_1110_0111_0011 ||
|
| 2175 |
|
|
(ir[15:6] == 10'b0100_0110_11 && ir[5:3] != 3'b001 && ir[5:0] != 6'b111_101 && ir[5:0] != 6'b111_110 && ir[5:0] != 6'b111_111) ||
|
| 2176 |
|
|
ir[15:3] == 13'b0100_1110_0110_0 ||
|
| 2177 |
|
|
ir[15:3] == 13'b0100_1110_0110_1 ) && supervisor == 1'b0 ) ? { PRIVILEGE_VIOLATION_TRAP, UNUSED_MICROPC } :
|
| 2178 |
|
|
// ILLEGAL, illegal instruction
|
| 2179 |
|
|
( ir[15:0] == 16'b0100_1010_11_111100 ) ? { ILLEGAL_INSTRUCTION_TRAP, UNUSED_MICROPC } :
|
| 2180 |
|
|
// 1010 illegal instruction
|
| 2181 |
|
|
( ir[15:12] == 4'b1010 ) ? { ILLEGAL_1010_INSTRUCTION_TRAP, UNUSED_MICROPC } :
|
| 2182 |
|
|
// 1111 illegal instruction
|
| 2183 |
|
|
( ir[15:12] == 4'b1111 ) ? { ILLEGAL_1111_INSTRUCTION_TRAP, UNUSED_MICROPC } :
|
| 2184 |
|
|
|
| 2185 |
|
|
// instruction decoding
|
| 2186 |
|
|
|
| 2187 |
|
|
// ANDI,EORI,ORI,ADDI,SUBI
|
| 2188 |
|
|
( ir[15:12] == 4'b0000 && ir[11:9] != 3'b100 && ir[11:9] != 3'b110 && ir[11:9] != 3'b111 && ir[8] == 1'b0 &&
|
| 2189 |
|
|
(ir[7:6] == 2'b00 || ir[7:6] == 2'b01 || ir[7:6] == 2'b10) && ir[5:3] != 3'b001 &&
|
| 2190 |
|
|
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001)) &&
|
| 2191 |
|
|
ir[15:0] != 16'b0000_000_0_00_111100 && ir[15:0] != 16'b0000_000_0_01_111100 &&
|
| 2192 |
|
|
ir[15:0] != 16'b0000_001_0_00_111100 && ir[15:0] != 16'b0000_001_0_01_111100 &&
|
| 2193 |
|
|
ir[15:0] != 16'b0000_101_0_00_111100 && ir[15:0] != 16'b0000_101_0_01_111100 ) ? { NO_TRAP, `MICROPC_ANDI_EORI_ORI_ADDI_SUBI } :
|
| 2194 |
|
|
// ORI to CCR,ORI to SR,ANDI to CCR,ANDI to SR,EORI to CCR,EORI to SR
|
| 2195 |
|
|
( ir[15:0] == 16'b0000_000_0_00_111100 || ir[15:0] == 16'b0000_000_0_01_111100 ||
|
| 2196 |
|
|
ir[15:0] == 16'b0000_001_0_00_111100 || ir[15:0] == 16'b0000_001_0_01_111100 ||
|
| 2197 |
|
|
ir[15:0] == 16'b0000_101_0_00_111100 || ir[15:0] == 16'b0000_101_0_01_111100 ) ?
|
| 2198 |
|
|
{ NO_TRAP, `MICROPC_ORI_to_CCR_ORI_to_SR_ANDI_to_CCR_ANDI_to_SR_EORI_to_CCR_EORI_to_SR } :
|
| 2199 |
|
|
// BTST register
|
| 2200 |
|
|
( ir[15:12] == 4'b0000 && ir[8:6] == 3'b100 && ir[5:3] != 3'b001 &&
|
| 2201 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2202 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
|
| 2203 |
|
|
) ? { NO_TRAP, `MICROPC_BTST_register } :
|
| 2204 |
|
|
// MOVEP memory to register
|
| 2205 |
|
|
( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] == 3'b001 && ( ir[7:6] == 2'b00 || ir[7:6] == 2'b01 ) ) ?
|
| 2206 |
|
|
{ NO_TRAP, `MICROPC_MOVEP_memory_to_register } :
|
| 2207 |
|
|
// MOVEP register to memory
|
| 2208 |
|
|
( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] == 3'b001 && ( ir[7:6] == 2'b10 || ir[7:6] == 2'b11 ) ) ?
|
| 2209 |
|
|
{ NO_TRAP, `MICROPC_MOVEP_register_to_memory } :
|
| 2210 |
|
|
// BCHG,BCLR,BSET register
|
| 2211 |
|
|
( ir[15:12] == 4'b0000 && ir[8] == 1'b1 && ir[5:3] != 3'b001 && ir[8:6] != 3'b100 &&
|
| 2212 |
|
|
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
|
| 2213 |
|
|
) ? { NO_TRAP, `MICROPC_BCHG_BCLR_BSET_register } :
|
| 2214 |
|
|
// BTST immediate
|
| 2215 |
|
|
( ir[15:12] == 4'b0000 && ir[11:8] == 4'b1000 && ir[7:6] == 2'b00 && ir[5:3] != 3'b001 &&
|
| 2216 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2217 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
|
| 2218 |
|
|
) ? { NO_TRAP, `MICROPC_BTST_immediate } :
|
| 2219 |
|
|
// BCHG,BCLR,BSET immediate
|
| 2220 |
|
|
( ir[15:12] == 4'b0000 && ir[11:8] == 4'b1000 && ir[7:6] != 2'b00 && ir[5:3] != 3'b001 &&
|
| 2221 |
|
|
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
|
| 2222 |
|
|
) ? { NO_TRAP, `MICROPC_BCHG_BCLR_BSET_immediate } :
|
| 2223 |
|
|
// CMPI
|
| 2224 |
|
|
( ir[15:12] == 4'b0000 && ir[8] == 1'b0 && ir[11:9] == 3'b110 && ir[7:6] != 2'b11 && ir[5:3] != 3'b001 &&
|
| 2225 |
|
|
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
|
| 2226 |
|
|
) ? { NO_TRAP, `MICROPC_CMPI } :
|
| 2227 |
|
|
// MOVE
|
| 2228 |
|
|
( ir[15:14] == 2'b00 && ir[13:12] != 2'b00 && ir[8:6] != 3'b001 &&
|
| 2229 |
|
|
(ir[8:6] != 3'b111 || (ir[11:6] == 6'b000_111 || ir[11:6] == 6'b001_111)) &&
|
| 2230 |
|
|
(ir[13:12] != 2'b01 || ir[5:3] != 3'b001) &&
|
| 2231 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2232 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
|
| 2233 |
|
|
) ? { NO_TRAP, `MICROPC_MOVE } :
|
| 2234 |
|
|
// MOVEA
|
| 2235 |
|
|
( ir[15:14] == 2'b00 && (ir[13:12] == 2'b11 || ir[13:12] == 2'b10) && ir[8:6] == 3'b001 &&
|
| 2236 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2237 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
|
| 2238 |
|
|
) ? { NO_TRAP, `MICROPC_MOVEA } :
|
| 2239 |
|
|
// NEGX,CLR,NEG,NOT,NBCD
|
| 2240 |
|
|
( ir[15:12] == 4'b0100 && ir[5:3] != 3'b001 && (ir[5:3] != 3'b111 || ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001) &&
|
| 2241 |
|
|
( (ir[11:8] == 4'b0000 && ir[7:6] != 2'b11) || (ir[11:8] == 4'b0010 && ir[7:6] != 2'b11) ||
|
| 2242 |
|
|
(ir[11:8] == 4'b0100 && ir[7:6] != 2'b11) || (ir[11:8] == 4'b0110 && ir[7:6] != 2'b11) ||
|
| 2243 |
|
|
(ir[11:6] == 6'b1000_00)
|
| 2244 |
|
|
)
|
| 2245 |
|
|
) ? { NO_TRAP, `MICROPC_NEGX_CLR_NEG_NOT_NBCD } :
|
| 2246 |
|
|
// MOVE FROM SR
|
| 2247 |
|
|
( ir[15:6] == 10'b0100_0000_11 && ir[5:3] != 3'b001 && (ir[5:3] != 3'b111 || ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001)
|
| 2248 |
|
|
) ? { NO_TRAP, `MICROPC_MOVE_FROM_SR } :
|
| 2249 |
|
|
// CHK
|
| 2250 |
|
|
( ir[15:12] == 4'b0100 && ir[8:6] == 3'b110 && ir[5:3] != 3'b001 &&
|
| 2251 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2252 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
|
| 2253 |
|
|
) ? { NO_TRAP, `MICROPC_CHK } :
|
| 2254 |
|
|
// LEA
|
| 2255 |
|
|
( ir[15:12] == 4'b0100 && ir[8:6] == 3'b111 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
|
| 2256 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2257 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
|
| 2258 |
|
|
) ? { NO_TRAP, `MICROPC_LEA } :
|
| 2259 |
|
|
// MOVE TO CCR, MOVE TO SR
|
| 2260 |
|
|
( (ir[15:6] == 10'b0100_0100_11 || ir[15:6] == 10'b0100_0110_11) && ir[5:3] != 3'b001 &&
|
| 2261 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2262 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
|
| 2263 |
|
|
) ? { NO_TRAP, `MICROPC_MOVE_TO_CCR_MOVE_TO_SR } :
|
| 2264 |
|
|
// SWAP,EXT
|
| 2265 |
|
|
( ir[15:12] == 4'b0100 && (ir[11:3] == 9'b1000_01_000 || (ir[11:7] == 5'b1000_1 && ir[5:3] == 3'b000) ) ) ? { NO_TRAP, `MICROPC_SWAP_EXT } :
|
| 2266 |
|
|
// PEA
|
| 2267 |
|
|
( ir[15:6] == 10'b0100_1000_01 && ir[5:3] != 3'b000 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
|
| 2268 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2269 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
|
| 2270 |
|
|
) ? { NO_TRAP, `MICROPC_PEA } :
|
| 2271 |
|
|
// MOVEM register to memory, predecrement
|
| 2272 |
|
|
( ir[15:7] == 9'b0100_1000_1 && ir[5:3] == 3'b100 ) ? { NO_TRAP, `MICROPC_MOVEM_register_to_memory_predecrement } :
|
| 2273 |
|
|
// MOVEM register to memory, control
|
| 2274 |
|
|
( ir[15:7] == 9'b0100_1000_1 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
|
| 2275 |
|
|
(ir[5:3] != 3'b111 || ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001)
|
| 2276 |
|
|
) ? { NO_TRAP, `MICROPC_MOVEM_register_to_memory_control } :
|
| 2277 |
|
|
// TST
|
| 2278 |
|
|
( ir[15:8] == 8'b0100_1010 && ir[7:6] != 2'b11 && ir[5:3] != 3'b001 &&
|
| 2279 |
|
|
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
|
| 2280 |
|
|
) ? { NO_TRAP, `MICROPC_TST } :
|
| 2281 |
|
|
// TAS
|
| 2282 |
|
|
( ir[15:6] == 10'b0100_1010_11 && ir[5:3] != 3'b001 &&
|
| 2283 |
|
|
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
|
| 2284 |
|
|
) ? { NO_TRAP, `MICROPC_TAS } :
|
| 2285 |
|
|
// MOVEM memory to register
|
| 2286 |
|
|
( ir[15:7] == 9'b0100_1100_1 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b011 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
|
| 2287 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2288 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
|
| 2289 |
|
|
) ? { NO_TRAP, `MICROPC_MOVEM_memory_to_register } :
|
| 2290 |
|
|
// TRAP
|
| 2291 |
|
|
( ir[15:4] == 12'b0100_1110_0100 ) ? { NO_TRAP, `MICROPC_TRAP } :
|
| 2292 |
|
|
// LINK
|
| 2293 |
|
|
( ir[15:3] == 13'b0100_1110_0101_0 ) ? { NO_TRAP, `MICROPC_LINK } :
|
| 2294 |
|
|
// UNLK
|
| 2295 |
|
|
( ir[15:3] == 13'b0100_1110_0101_1 ) ? { NO_TRAP, `MICROPC_ULNK } :
|
| 2296 |
|
|
// MOVE USP to USP
|
| 2297 |
|
|
( ir[15:3] == 13'b0100_1110_0110_0 ) ? { NO_TRAP, `MICROPC_MOVE_USP_to_USP } :
|
| 2298 |
|
|
// MOVE USP to An
|
| 2299 |
|
|
( ir[15:3] == 13'b0100_1110_0110_1 ) ? { NO_TRAP, `MICROPC_MOVE_USP_to_An } :
|
| 2300 |
|
|
// RESET
|
| 2301 |
|
|
( ir[15:0] == 16'b0100_1110_0111_0000 ) ? { NO_TRAP, `MICROPC_RESET } :
|
| 2302 |
|
|
// NOP
|
| 2303 |
|
|
( ir[15:0] == 16'b0100_1110_0111_0001 ) ? { NO_TRAP, `MICROPC_NOP } :
|
| 2304 |
|
|
// STOP
|
| 2305 |
|
|
( ir[15:0] == 16'b0100_1110_0111_0010 ) ? { NO_TRAP, `MICROPC_STOP } :
|
| 2306 |
|
|
// RTE,RTR
|
| 2307 |
|
|
( ir[15:0] == 16'b0100_1110_0111_0011 || ir[15:0] == 16'b0100_1110_0111_0111 ) ? { NO_TRAP, `MICROPC_RTE_RTR } :
|
| 2308 |
|
|
// RTS
|
| 2309 |
|
|
( ir[15:0] == 16'b0100_1110_0111_0101 ) ? { NO_TRAP, `MICROPC_RTS } :
|
| 2310 |
|
|
// TRAPV
|
| 2311 |
|
|
( ir[15:0] == 16'b0100_1110_0111_0110 ) ? { NO_TRAP, `MICROPC_TRAPV } :
|
| 2312 |
|
|
// JSR
|
| 2313 |
|
|
( ir[15:6] == 10'b0100_1110_10 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
|
| 2314 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2315 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
|
| 2316 |
|
|
) ? { NO_TRAP, `MICROPC_JSR } :
|
| 2317 |
|
|
// JMP
|
| 2318 |
|
|
( ir[15:6] == 10'b0100_1110_11 && (ir[5:3] == 3'b010 || ir[5:3] == 3'b101 || ir[5:3] == 3'b110 || ir[5:3] == 3'b111) &&
|
| 2319 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2320 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011))
|
| 2321 |
|
|
) ? { NO_TRAP, `MICROPC_JMP } :
|
| 2322 |
|
|
// ADDQ,SUBQ not An
|
| 2323 |
|
|
( ir[15:12] == 4'b0101 && ir[7:6] != 2'b11 && ir[5:3] != 3'b001 &&
|
| 2324 |
|
|
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
|
| 2325 |
|
|
) ? { NO_TRAP, `MICROPC_ADDQ_SUBQ_not_An } :
|
| 2326 |
|
|
// ADDQ,SUBQ An
|
| 2327 |
|
|
( ir[15:12] == 4'b0101 && ir[7:6] != 2'b11 && ir[7:6] != 2'b00 && ir[5:3] == 3'b001 ) ? { NO_TRAP, `MICROPC_ADDQ_SUBQ_An } :
|
| 2328 |
|
|
// Scc
|
| 2329 |
|
|
( ir[15:12] == 4'b0101 && ir[7:6] == 2'b11 && ir[5:3] != 3'b001 &&
|
| 2330 |
|
|
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
|
| 2331 |
|
|
) ? { NO_TRAP, `MICROPC_Scc } :
|
| 2332 |
|
|
// DBcc
|
| 2333 |
|
|
( ir[15:12] == 4'b0101 && ir[7:6] == 2'b11 && ir[5:3] == 3'b001 ) ? { NO_TRAP, `MICROPC_DBcc } :
|
| 2334 |
|
|
// BSR
|
| 2335 |
|
|
( ir[15:12] == 4'b0110 && ir[11:8] == 4'b0001 ) ? { NO_TRAP, `MICROPC_BSR } :
|
| 2336 |
|
|
// Bcc,BRA
|
| 2337 |
|
|
( ir[15:12] == 4'b0110 && ir[11:8] != 4'b0001 ) ? { NO_TRAP, `MICROPC_Bcc_BRA } :
|
| 2338 |
|
|
// MOVEQ
|
| 2339 |
|
|
( ir[15:12] == 4'b0111 && ir[8] == 1'b0 ) ? { NO_TRAP, `MICROPC_MOVEQ } :
|
| 2340 |
|
|
// CMP
|
| 2341 |
|
|
( (ir[15:12] == 4'b1011) && (ir[8:6] == 3'b000 || ir[8:6] == 3'b001 || ir[8:6] == 3'b010) &&
|
| 2342 |
|
|
(ir[8:6] != 3'b000 || ir[5:3] != 3'b001) &&
|
| 2343 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2344 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
|
| 2345 |
|
|
) ? { NO_TRAP, `MICROPC_CMP } :
|
| 2346 |
|
|
// CMPA
|
| 2347 |
|
|
( (ir[15:12] == 4'b1011) && (ir[8:6] == 3'b011 || ir[8:6] == 3'b111) &&
|
| 2348 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2349 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
|
| 2350 |
|
|
) ? { NO_TRAP, `MICROPC_CMPA } :
|
| 2351 |
|
|
// CMPM
|
| 2352 |
|
|
( ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || ir[8:6] == 3'b101 || ir[8:6] == 3'b110) && ir[5:3] == 3'b001) ? { NO_TRAP, `MICROPC_CMPM } :
|
| 2353 |
|
|
// EOR
|
| 2354 |
|
|
( ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || ir[8:6] == 3'b101 || ir[8:6] == 3'b110) && ir[5:3] != 3'b001 &&
|
| 2355 |
|
|
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
|
| 2356 |
|
|
) ? { NO_TRAP, `MICROPC_EOR } :
|
| 2357 |
|
|
// ADD to mem,SUB to mem,AND to mem,OR to mem
|
| 2358 |
|
|
( (ir[15:12] == 4'b1101 || ir[15:12] == 4'b1001 || ir[15:12] == 4'b1100 || ir[15:12] == 4'b1000) &&
|
| 2359 |
|
|
(ir[8:4] == 5'b10001 || ir[8:4] == 5'b10010 || ir[8:4] == 5'b10011 ||
|
| 2360 |
|
|
ir[8:4] == 5'b10101 || ir[8:4] == 5'b10110 || ir[8:4] == 5'b10111 ||
|
| 2361 |
|
|
ir[8:4] == 5'b11001 || ir[8:4] == 5'b11010 || ir[8:4] == 5'b11011) &&
|
| 2362 |
|
|
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
|
| 2363 |
|
|
) ? { NO_TRAP, `MICROPC_ADD_to_mem_SUB_to_mem_AND_to_mem_OR_to_mem } :
|
| 2364 |
|
|
// ADD to Dn,SUB to Dn,AND to Dn,OR to Dn
|
| 2365 |
|
|
( (ir[15:12] == 4'b1101 || ir[15:12] == 4'b1001 || ir[15:12] == 4'b1100 || ir[15:12] == 4'b1000) &&
|
| 2366 |
|
|
(ir[8:6] == 3'b000 || ir[8:6] == 3'b001 || ir[8:6] == 3'b010) &&
|
| 2367 |
|
|
(ir[12] != 1'b1 || ir[8:6] != 3'b000 || ir[5:3] != 3'b001) && (ir[12] == 1'b1 || ir[5:3] != 3'b001) &&
|
| 2368 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2369 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
|
| 2370 |
|
|
) ? { NO_TRAP, `MICROPC_ADD_to_Dn_SUB_to_Dn_AND_to_Dn_OR_to_Dn } :
|
| 2371 |
|
|
// ADDA,SUBA
|
| 2372 |
|
|
( (ir[15:12] == 4'b1101 || ir[15:12] == 4'b1001) && (ir[8:6] == 3'b011 || ir[8:6] == 3'b111) &&
|
| 2373 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2374 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
|
| 2375 |
|
|
) ? { NO_TRAP, `MICROPC_ADDA_SUBA } :
|
| 2376 |
|
|
// ABCD,SBCD,ADDX,SUBX
|
| 2377 |
|
|
( ((ir[15:12] == 4'b1100 || ir[15:12] == 4'b1000) && ir[8:4] == 5'b10000) ||
|
| 2378 |
|
|
((ir[15:12] == 4'b1101 || ir[15:12] == 4'b1001) && (ir[8:4] == 5'b10000 || ir[8:4] == 5'b10100 || ir[8:4] == 5'b11000) ) ) ?
|
| 2379 |
|
|
{ NO_TRAP, `MICROPC_ABCD_SBCD_ADDX_SUBX } :
|
| 2380 |
|
|
// EXG
|
| 2381 |
|
|
( ir[15:12] == 4'b1100 && (ir[8:3] == 6'b101000 || ir[8:3] == 6'b101001 || ir[8:3] == 6'b110001) ) ? { NO_TRAP, `MICROPC_EXG } :
|
| 2382 |
|
|
// MULS,MULU,DIVS,DIVU
|
| 2383 |
|
|
( (ir[15:12] == 4'b1100 || ir[15:12] == 4'b1000) && ir[7:6] == 2'b11 && ir[5:3] != 3'b001 &&
|
| 2384 |
|
|
(ir[5:3] != 3'b111 ||
|
| 2385 |
|
|
(ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001 || ir[5:0] == 6'b111_010 || ir[5:0] == 6'b111_011 || ir[5:0] == 6'b111_100))
|
| 2386 |
|
|
) ? { NO_TRAP, `MICROPC_MULS_MULU_DIVS_DIVU } :
|
| 2387 |
|
|
// ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all memory
|
| 2388 |
|
|
( ir[15:12] == 4'b1110 && ir[11] == 1'b0 && ir[7:6] == 2'b11 && ir[5:3] != 3'b000 && ir[5:3] != 3'b001 &&
|
| 2389 |
|
|
(ir[5:3] != 3'b111 || (ir[5:0] == 6'b111_000 || ir[5:0] == 6'b111_001))
|
| 2390 |
|
|
) ? { NO_TRAP, `MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_memory } :
|
| 2391 |
|
|
// ASL,LSL,ROL,ROXL,ASR,LSR,ROR,ROXR all immediate/register
|
| 2392 |
|
|
( ir[15:12] == 4'b1110 && (ir[7:6] == 2'b00 || ir[7:6] == 2'b01 || ir[7:6] == 2'b10) ) ?
|
| 2393 |
|
|
{ NO_TRAP, `MICROPC_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_all_immediate_register } :
|
| 2394 |
|
|
|
| 2395 |
|
|
// else
|
| 2396 |
|
|
|
| 2397 |
|
|
{ ILLEGAL_INSTRUCTION_TRAP, UNUSED_MICROPC }
|
| 2398 |
|
|
;
|
| 2399 |
|
|
|
| 2400 |
|
|
// load ea
|
| 2401 |
|
|
assign load_ea =
|
| 2402 |
|
|
(
|
| 2403 |
|
|
(ea_type == `EA_TYPE_ALL && (ea_mod == 3'b000 || ea_mod == 3'b001 || (ea_mod == 3'b111 && ea_reg == 3'b100))) ||
|
| 2404 |
|
|
(ea_type == `EA_TYPE_DATAALTER && ea_mod == 3'b000) ||
|
| 2405 |
|
|
(ea_type == `EA_TYPE_DN_AN && (ea_mod == 3'b000 || ea_mod == 3'b001)) ||
|
| 2406 |
|
|
(ea_type == `EA_TYPE_DATA && (ea_mod == 3'b000 || (ea_mod == 3'b111 && ea_reg == 3'b100)))
|
| 2407 |
|
|
) ? 9'd0 // no ea needed
|
| 2408 |
|
|
:
|
| 2409 |
|
|
(ea_mod == 3'b010 && (
|
| 2410 |
|
|
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROLALTER_PREDEC ||
|
| 2411 |
|
|
ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_MEMORYALTER ||
|
| 2412 |
|
|
ea_type == `EA_TYPE_DATA
|
| 2413 |
|
|
)) ? `MICROPC_LOAD_EA_An // (An)
|
| 2414 |
|
|
:
|
| 2415 |
|
|
(ea_mod == 3'b011 && (
|
| 2416 |
|
|
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_MEMORYALTER ||
|
| 2417 |
|
|
ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_DATA
|
| 2418 |
|
|
)) ? `MICROPC_LOAD_EA_An_plus // (An)+
|
| 2419 |
|
|
:
|
| 2420 |
|
|
(ea_mod == 3'b100 && (
|
| 2421 |
|
|
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROLALTER_PREDEC || ea_type == `EA_TYPE_DATAALTER ||
|
| 2422 |
|
|
ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
|
| 2423 |
|
|
)) ? `MICROPC_LOAD_EA_minus_An // -(An)
|
| 2424 |
|
|
:
|
| 2425 |
|
|
(ea_mod == 3'b101 && (
|
| 2426 |
|
|
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROLALTER_PREDEC ||
|
| 2427 |
|
|
ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
|
| 2428 |
|
|
)) ? `MICROPC_LOAD_EA_d16_An // (d16, An)
|
| 2429 |
|
|
:
|
| 2430 |
|
|
(ea_mod == 3'b110 && (
|
| 2431 |
|
|
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROLALTER_PREDEC ||
|
| 2432 |
|
|
ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
|
| 2433 |
|
|
)) ? `MICROPC_LOAD_EA_d8_An_Xn // (d8, An, Xn)
|
| 2434 |
|
|
:
|
| 2435 |
|
|
(ea_mod == 3'b111 && ea_reg == 3'b000 && (
|
| 2436 |
|
|
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROLALTER_PREDEC ||
|
| 2437 |
|
|
ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
|
| 2438 |
|
|
)) ? `MICROPC_LOAD_EA_xxx_W // (xxx).W
|
| 2439 |
|
|
:
|
| 2440 |
|
|
(ea_mod == 3'b111 && ea_reg == 3'b001 && (
|
| 2441 |
|
|
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROLALTER_PREDEC ||
|
| 2442 |
|
|
ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
|
| 2443 |
|
|
)) ? `MICROPC_LOAD_EA_xxx_L // (xxx).L
|
| 2444 |
|
|
:
|
| 2445 |
|
|
(ea_mod == 3'b111 && ea_reg == 3'b010 && (
|
| 2446 |
|
|
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATA
|
| 2447 |
|
|
)) ? `MICROPC_LOAD_EA_d16_PC // (d16, PC)
|
| 2448 |
|
|
:
|
| 2449 |
|
|
(ea_mod == 3'b111 && ea_reg == 3'b011 && (
|
| 2450 |
|
|
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_CONTROL || ea_type == `EA_TYPE_DATA
|
| 2451 |
|
|
)) ? `MICROPC_LOAD_EA_d8_PC_Xn // (d8, PC, Xn)
|
| 2452 |
|
|
:
|
| 2453 |
|
|
`MICROPC_LOAD_EA_illegal_command // illegal command
|
| 2454 |
|
|
;
|
| 2455 |
|
|
|
| 2456 |
|
|
// perform ea read
|
| 2457 |
|
|
assign perform_ea_read =
|
| 2458 |
|
|
( ea_mod == 3'b000 && (ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_DN_AN ||
|
| 2459 |
|
|
ea_type == `EA_TYPE_DATA) ) ?
|
| 2460 |
|
|
`MICROPC_PERFORM_EA_READ_Dn :
|
| 2461 |
|
|
( ea_mod == 3'b001 && (ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_DN_AN) ) ? `MICROPC_PERFORM_EA_READ_An :
|
| 2462 |
|
|
( ea_mod == 3'b111 && ea_reg == 3'b100 && (ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_DATA) ) ?
|
| 2463 |
|
|
`MICROPC_PERFORM_EA_READ_imm :
|
| 2464 |
|
|
`MICROPC_PERFORM_EA_READ_memory
|
| 2465 |
|
|
;
|
| 2466 |
|
|
|
| 2467 |
|
|
// perform ea write
|
| 2468 |
|
|
assign perform_ea_write =
|
| 2469 |
|
|
( ea_mod == 3'b000 && (ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_DN_AN ||
|
| 2470 |
|
|
ea_type == `EA_TYPE_DATA) ) ?
|
| 2471 |
|
|
`MICROPC_PERFORM_EA_WRITE_Dn :
|
| 2472 |
|
|
( ea_mod == 3'b001 && (ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_DN_AN) ) ? `MICROPC_PERFORM_EA_WRITE_An :
|
| 2473 |
|
|
`MICROPC_PERFORM_EA_WRITE_memory
|
| 2474 |
|
|
;
|
| 2475 |
|
|
|
| 2476 |
|
|
// save ea
|
| 2477 |
|
|
assign save_ea =
|
| 2478 |
|
|
(ea_mod == 3'b011 && (
|
| 2479 |
|
|
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROL_POSTINC || ea_type == `EA_TYPE_MEMORYALTER ||
|
| 2480 |
|
|
ea_type == `EA_TYPE_DATAALTER || ea_type == `EA_TYPE_DATA
|
| 2481 |
|
|
)) ? `MICROPC_SAVE_EA_An_plus // (An)+
|
| 2482 |
|
|
:
|
| 2483 |
|
|
(ea_mod == 3'b100 && (
|
| 2484 |
|
|
ea_type == `EA_TYPE_ALL || ea_type == `EA_TYPE_CONTROLALTER_PREDEC || ea_type == `EA_TYPE_DATAALTER ||
|
| 2485 |
|
|
ea_type == `EA_TYPE_MEMORYALTER || ea_type == `EA_TYPE_DATA
|
| 2486 |
|
|
)) ? `MICROPC_SAVE_EA_minus_An // -(An)
|
| 2487 |
|
|
:
|
| 2488 |
|
|
9'd0 // no ea needed
|
| 2489 |
|
|
;
|
| 2490 |
|
|
|
| 2491 |
|
|
endmodule
|
| 2492 |
|
|
|
| 2493 |
|
|
/***********************************************************************************************************************
|
| 2494 |
|
|
* Condition
|
| 2495 |
|
|
**********************************************************************************************************************/
|
| 2496 |
|
|
|
| 2497 |
|
|
/*! \brief Condition tests.
|
| 2498 |
|
|
*
|
| 2499 |
|
|
* The condition module implements the condition tests of the MC68000. Its inputs are the condition codes
|
| 2500 |
|
|
* and the currently selected test. The output is binary: the test is true or false. The output of the condition module
|
| 2501 |
|
|
* is an input to the microcode_branch module, that decides which microcode word to execute next.
|
| 2502 |
|
|
*/
|
| 2503 |
|
|
module condition(
|
| 2504 |
|
|
input [3:0] cond,
|
| 2505 |
|
|
input [7:0] ccr,
|
| 2506 |
|
|
output condition
|
| 2507 |
|
|
);
|
| 2508 |
|
|
|
| 2509 |
|
|
wire C,V,Z,N;
|
| 2510 |
|
|
assign C = ccr[0];
|
| 2511 |
|
|
assign V = ccr[1];
|
| 2512 |
|
|
assign Z = ccr[2];
|
| 2513 |
|
|
assign N = ccr[3];
|
| 2514 |
|
|
|
| 2515 |
|
|
assign condition = (cond == 4'b0000) ? 1'b1 : // true
|
| 2516 |
|
|
(cond == 4'b0001) ? 1'b0 : // false
|
| 2517 |
|
|
(cond == 4'b0010) ? ~C & ~Z : // high
|
| 2518 |
|
|
(cond == 4'b0011) ? C | Z : // low or same
|
| 2519 |
|
|
(cond == 4'b0100) ? ~C : // carry clear
|
| 2520 |
|
|
(cond == 4'b0101) ? C : // carry set
|
| 2521 |
|
|
(cond == 4'b0110) ? ~Z : // not equal
|
| 2522 |
|
|
(cond == 4'b0111) ? Z : // equal
|
| 2523 |
|
|
(cond == 4'b1000) ? ~V : // overflow clear
|
| 2524 |
|
|
(cond == 4'b1001) ? V : // overflow set
|
| 2525 |
|
|
(cond == 4'b1010) ? ~N : // plus
|
| 2526 |
|
|
(cond == 4'b1011) ? N : // minus
|
| 2527 |
|
|
(cond == 4'b1100) ? (N & V) | (~N & ~V) : // greater or equal
|
| 2528 |
|
|
(cond == 4'b1101) ? (N & ~V) | (~N & V) : // less than
|
| 2529 |
|
|
(cond == 4'b1110) ? (N & V & ~Z) | (~N & ~V & ~Z) : // greater than
|
| 2530 |
|
|
(cond == 4'b1111) ? (Z) | (N & ~V) | (~N & V) : // less or equal
|
| 2531 |
|
|
1'b0;
|
| 2532 |
|
|
endmodule
|
| 2533 |
|
|
|
| 2534 |
|
|
/***********************************************************************************************************************
|
| 2535 |
|
|
* ALU
|
| 2536 |
|
|
**********************************************************************************************************************/
|
| 2537 |
|
|
|
| 2538 |
|
|
/*! \brief Arithmetic and Logic Unit.
|
| 2539 |
|
|
*
|
| 2540 |
|
|
* The alu module is responsible for performing all of the arithmetic and logic operations of the ao68000 processor.
|
| 2541 |
|
|
* It operates on two 32-bit registers: operand1 and operand2 from the registers module. The output is saved into
|
| 2542 |
|
|
* a result 32-bit register. This register is located in the alu module.
|
| 2543 |
|
|
*
|
| 2544 |
|
|
* The alu module also contains the status register (SR) with the condition code register. The microcode decides what
|
| 2545 |
|
|
* operation the alu performs.
|
| 2546 |
|
|
*/
|
| 2547 |
|
|
module alu(
|
| 2548 |
|
|
input clock,
|
| 2549 |
|
|
input reset_n,
|
| 2550 |
|
|
|
| 2551 |
|
|
// only zero bit
|
| 2552 |
|
|
input [31:0] address,
|
| 2553 |
|
|
// only ir[11:9] and ir[6]
|
| 2554 |
|
|
input [15:0] ir,
|
| 2555 |
|
|
// byte 2'b00, word 2'b01, long 2'b10
|
| 2556 |
|
|
input [1:0] size,
|
| 2557 |
|
|
|
| 2558 |
|
|
input [31:0] operand1,
|
| 2559 |
|
|
input [31:0] operand2,
|
| 2560 |
|
|
|
| 2561 |
|
|
input [2:0] interrupt_mask,
|
| 2562 |
|
|
input [4:0] alu_control,
|
| 2563 |
|
|
|
| 2564 |
|
|
output reg [15:0] sr,
|
| 2565 |
|
|
output reg [31:0] result,
|
| 2566 |
|
|
output reg [1:0] special = 2'b00
|
| 2567 |
|
|
);
|
| 2568 |
|
|
|
| 2569 |
|
|
wire [31:0] divu_quotient;
|
| 2570 |
|
|
wire [15:0] divu_remainder;
|
| 2571 |
|
|
wire [31:0] divs_quotient;
|
| 2572 |
|
|
wire [15:0] divs_remainder;
|
| 2573 |
|
|
wire [31:0] mulu_result;
|
| 2574 |
|
|
wire [31:0] muls_result;
|
| 2575 |
|
|
|
| 2576 |
|
|
//****************************************************** Altera-specific multiplication and division modules START
|
| 2577 |
|
|
/* Multiplication and division modules.
|
| 2578 |
|
|
*
|
| 2579 |
|
|
* Currently this module contains <em>lpm_divide</em> and <em>lpm_mult</em> instantiations
|
| 2580 |
|
|
* from Altera Megafunction/LPM library.
|
| 2581 |
|
|
*
|
| 2582 |
|
|
* There are separate modules for:
|
| 2583 |
|
|
* - unsigned multiplication,
|
| 2584 |
|
|
* - signed multiplication,
|
| 2585 |
|
|
* - unsigned division,
|
| 2586 |
|
|
* - singed division.
|
| 2587 |
|
|
*/
|
| 2588 |
|
|
|
| 2589 |
|
|
// DIVU: 32-bit operand1 unsigned / 16-bit operand2 unsigned = {16-bit remainer unsigned, 16-bit quotient unsigned}
|
| 2590 |
|
|
// DIVU: division by 0: trap, overflow when quotient > 16-bit signed integer, operands not affected
|
| 2591 |
|
|
lpm_divide divu_inst(
|
| 2592 |
|
|
.clock(clock),
|
| 2593 |
|
|
.numer(operand1[31:0]),
|
| 2594 |
|
|
.denom(operand2[15:0]),
|
| 2595 |
|
|
.quotient(divu_quotient),
|
| 2596 |
|
|
.remain(divu_remainder)
|
| 2597 |
|
|
);
|
| 2598 |
|
|
defparam
|
| 2599 |
|
|
divu_inst.lpm_widthn = 32,
|
| 2600 |
|
|
divu_inst.lpm_widthd = 16,
|
| 2601 |
|
|
divu_inst.lpm_nrepresentation = "UNSIGNED",
|
| 2602 |
|
|
divu_inst.lpm_drepresentation = "UNSIGNED",
|
| 2603 |
|
|
divu_inst.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
|
| 2604 |
|
|
divu_inst.lpm_pipeline = 30;
|
| 2605 |
|
|
|
| 2606 |
|
|
// DIVS: 32-bit operand1 signed / 16-bit operand2 signed = {16-bit remainer signed = sign of dividend, 16-bit quotient signed}
|
| 2607 |
|
|
// DIVS: division by 0: trap, overflow when quotient > 16-bit signed integer, operands not affected
|
| 2608 |
|
|
lpm_divide divs_inst(
|
| 2609 |
|
|
.clock(clock),
|
| 2610 |
|
|
.numer(operand1[31:0]),
|
| 2611 |
|
|
.denom(operand2[15:0]),
|
| 2612 |
|
|
.quotient(divs_quotient),
|
| 2613 |
|
|
.remain(divs_remainder)
|
| 2614 |
|
|
);
|
| 2615 |
|
|
defparam
|
| 2616 |
|
|
divs_inst.lpm_widthn = 32,
|
| 2617 |
|
|
divs_inst.lpm_widthd = 16,
|
| 2618 |
|
|
divs_inst.lpm_nrepresentation = "SIGNED",
|
| 2619 |
|
|
divs_inst.lpm_drepresentation = "SIGNED",
|
| 2620 |
|
|
divs_inst.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE",
|
| 2621 |
|
|
divs_inst.lpm_pipeline = 30;
|
| 2622 |
|
|
|
| 2623 |
|
|
// MULU: 16-bit operand1[15:0] unsigned * 16-bit operand2 unsigned = 32-bit result unsigned
|
| 2624 |
|
|
lpm_mult mulu_inst(
|
| 2625 |
|
|
.clock(clock),
|
| 2626 |
|
|
.dataa(operand1[15:0]),
|
| 2627 |
|
|
.datab(operand2[15:0]),
|
| 2628 |
|
|
.result(mulu_result)
|
| 2629 |
|
|
);
|
| 2630 |
|
|
defparam
|
| 2631 |
|
|
mulu_inst.lpm_widtha = 16,
|
| 2632 |
|
|
mulu_inst.lpm_widthb = 16,
|
| 2633 |
|
|
mulu_inst.lpm_widthp = 32,
|
| 2634 |
|
|
mulu_inst.lpm_representation = "UNSIGNED",
|
| 2635 |
|
|
mulu_inst.lpm_pipeline = 18;
|
| 2636 |
|
|
|
| 2637 |
|
|
// MULS: 16-bit operand1[15:0] signed * 16-bit operand2 signed = 32-bit result signed
|
| 2638 |
|
|
lpm_mult muls_inst(
|
| 2639 |
|
|
.clock(clock),
|
| 2640 |
|
|
.dataa(operand1[15:0]),
|
| 2641 |
|
|
.datab(operand2[15:0]),
|
| 2642 |
|
|
.result(muls_result)
|
| 2643 |
|
|
);
|
| 2644 |
|
|
defparam
|
| 2645 |
|
|
muls_inst.lpm_widtha = 16,
|
| 2646 |
|
|
muls_inst.lpm_widthb = 16,
|
| 2647 |
|
|
muls_inst.lpm_widthp = 32,
|
| 2648 |
|
|
muls_inst.lpm_representation = "SIGNED",
|
| 2649 |
|
|
muls_inst.lpm_pipeline = 18;
|
| 2650 |
|
|
//****************************************************** Altera-specific multiplication and division modules END
|
| 2651 |
|
|
|
| 2652 |
|
|
// ALU internal defines
|
| 2653 |
|
|
`define Sm ( (size == 2'b00) ? operand2[7] : (size == 2'b01) ? operand2[15] : operand2[31])
|
| 2654 |
|
|
|
| 2655 |
|
|
`define Dm ( (size == 2'b00) ? operand1[7] : (size == 2'b01) ? operand1[15] : operand1[31])
|
| 2656 |
|
|
|
| 2657 |
|
|
`define Rm ( (size == 2'b00) ? result[7] : (size == 2'b01) ? result[15] : result[31])
|
| 2658 |
|
|
|
| 2659 |
|
|
`define Z ( (size == 2'b00) ? (result[7:0] == 8'b0) : (size == 2'b01) ? (result[15:0] == 16'b0) : (result[31:0] == 32'b0))
|
| 2660 |
|
|
|
| 2661 |
|
|
// ALU operations
|
| 2662 |
|
|
|
| 2663 |
|
|
reg [2:0] interrupt_mask_copy;
|
| 2664 |
|
|
reg was_interrupt;
|
| 2665 |
|
|
|
| 2666 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 2667 |
|
|
if(reset_n == 1'b0) begin
|
| 2668 |
|
|
sr <= { 1'b0, 1'b0, 1'b1, 2'b0, 3'b111, 8'b0 };
|
| 2669 |
|
|
result <= 32'd0;
|
| 2670 |
|
|
special <= 2'b0;
|
| 2671 |
|
|
interrupt_mask_copy <= 3'b0;
|
| 2672 |
|
|
was_interrupt <= 1'b0;
|
| 2673 |
|
|
end
|
| 2674 |
|
|
else begin
|
| 2675 |
|
|
case(alu_control)
|
| 2676 |
|
|
`ALU_SR_SET_INTERRUPT: begin
|
| 2677 |
|
|
interrupt_mask_copy <= interrupt_mask[2:0];
|
| 2678 |
|
|
was_interrupt <= 1'b1;
|
| 2679 |
|
|
end
|
| 2680 |
|
|
|
| 2681 |
|
|
`ALU_SR_SET_TRAP: begin
|
| 2682 |
|
|
if(was_interrupt == 1'b1) begin
|
| 2683 |
|
|
sr <= { 1'b0, sr[14], 1'b1, sr[12:11], interrupt_mask_copy[2:0], sr[7:0] };
|
| 2684 |
|
|
end
|
| 2685 |
|
|
else begin
|
| 2686 |
|
|
sr <= { 1'b0, sr[14], 1'b1, sr[12:0] };
|
| 2687 |
|
|
end
|
| 2688 |
|
|
was_interrupt <= 1'b0;
|
| 2689 |
|
|
end
|
| 2690 |
|
|
|
| 2691 |
|
|
`ALU_MOVEP_M2R_1: begin
|
| 2692 |
|
|
if(ir[6] == 1'b1) result[31:24] <= operand1[7:0];
|
| 2693 |
|
|
else result[15:8] <= operand1[7:0];
|
| 2694 |
|
|
//CCR: no change
|
| 2695 |
|
|
end
|
| 2696 |
|
|
`ALU_MOVEP_M2R_2: begin
|
| 2697 |
|
|
if(ir[6] == 1'b1) result[23:16] <= operand1[7:0];
|
| 2698 |
|
|
else result[7:0] <= operand1[7:0];
|
| 2699 |
|
|
//CCR: no change
|
| 2700 |
|
|
end
|
| 2701 |
|
|
`ALU_MOVEP_M2R_3: begin
|
| 2702 |
|
|
if(ir[6] == 1'b1) result[15:8] <= operand1[7:0];
|
| 2703 |
|
|
//CCR: no change
|
| 2704 |
|
|
end
|
| 2705 |
|
|
`ALU_MOVEP_M2R_4: begin
|
| 2706 |
|
|
if(ir[6] == 1'b1) result[7:0] <= operand1[7:0];
|
| 2707 |
|
|
//CCR: no change
|
| 2708 |
|
|
end
|
| 2709 |
|
|
|
| 2710 |
|
|
|
| 2711 |
|
|
`ALU_MOVEP_R2M_1: begin
|
| 2712 |
|
|
if(ir[6] == 1'b1) result[7:0] <= operand1[31:24];
|
| 2713 |
|
|
else result[7:0] <= operand1[15:8];
|
| 2714 |
|
|
// CCR: no change
|
| 2715 |
|
|
end
|
| 2716 |
|
|
`ALU_MOVEP_R2M_2: begin
|
| 2717 |
|
|
if(ir[6] == 1'b1) result[7:0] <= operand1[23:16];
|
| 2718 |
|
|
else result[7:0] <= operand1[7:0];
|
| 2719 |
|
|
// CCR: no change
|
| 2720 |
|
|
end
|
| 2721 |
|
|
`ALU_MOVEP_R2M_3: begin
|
| 2722 |
|
|
result[7:0] <= operand1[15:8];
|
| 2723 |
|
|
// CCR: no change
|
| 2724 |
|
|
end
|
| 2725 |
|
|
`ALU_MOVEP_R2M_4: begin
|
| 2726 |
|
|
result[7:0] <= operand1[7:0];
|
| 2727 |
|
|
// CCR: no change
|
| 2728 |
|
|
end
|
| 2729 |
|
|
|
| 2730 |
|
|
|
| 2731 |
|
|
|
| 2732 |
|
|
`ALU_SIGN_EXTEND: begin
|
| 2733 |
|
|
// move operand1 with sign-extension to result
|
| 2734 |
|
|
if(size == 2'b01) begin
|
| 2735 |
|
|
result <= { {16{operand1[15]}}, operand1[15:0] };
|
| 2736 |
|
|
end
|
| 2737 |
|
|
else begin
|
| 2738 |
|
|
result <= operand1;
|
| 2739 |
|
|
end
|
| 2740 |
|
|
// CCR: no change
|
| 2741 |
|
|
end
|
| 2742 |
|
|
|
| 2743 |
|
|
`ALU_ARITHMETIC_LOGIC: begin
|
| 2744 |
|
|
|
| 2745 |
|
|
// OR,OR to mem,OR to Dn
|
| 2746 |
|
|
if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b000) ||
|
| 2747 |
|
|
(ir[15:12] == 4'b1000)
|
| 2748 |
|
|
) result[31:0] = operand1[31:0] | operand2[31:0];
|
| 2749 |
|
|
// AND,AND to mem,AND to Dn
|
| 2750 |
|
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b001) ||
|
| 2751 |
|
|
(ir[15:12] == 4'b1100)
|
| 2752 |
|
|
) result[31:0] = operand1[31:0] & operand2[31:0];
|
| 2753 |
|
|
// EORI,EOR
|
| 2754 |
|
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b101) ||
|
| 2755 |
|
|
(ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || ir[8:6] == 3'b101 || ir[8:6] == 3'b110) && ir[5:3] != 3'b001)
|
| 2756 |
|
|
) result[31:0] = operand1[31:0] ^ operand2[31:0];
|
| 2757 |
|
|
// ADD,ADD to mem,ADD to Dn,ADDQ
|
| 2758 |
|
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b011) ||
|
| 2759 |
|
|
(ir[15:12] == 4'b1101) ||
|
| 2760 |
|
|
(ir[15:12] == 4'b0101 && ir[8] == 1'b0)
|
| 2761 |
|
|
) result[31:0] = operand1[31:0] + operand2[31:0];
|
| 2762 |
|
|
// SUBI,CMPI,CMPM,SUB to mem,SUB to Dn,CMP,SUBQ
|
| 2763 |
|
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b010) ||
|
| 2764 |
|
|
(ir[15:12] == 4'b0000 && ir[11:9] == 3'b110) ||
|
| 2765 |
|
|
(ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || ir[8:6] == 3'b101 || ir[8:6] == 3'b110) && ir[5:3] == 3'b001) ||
|
| 2766 |
|
|
(ir[15:12] == 4'b1001) ||
|
| 2767 |
|
|
(ir[15:12] == 4'b1011 && (ir[8:6] == 3'b000 || ir[8:6] == 3'b001 || ir[8:6] == 3'b010)) ||
|
| 2768 |
|
|
(ir[15:12] == 4'b0101 && ir[8] == 1'b1)
|
| 2769 |
|
|
) result[31:0] = operand1[31:0] - operand2[31:0];
|
| 2770 |
|
|
|
| 2771 |
|
|
// Z
|
| 2772 |
|
|
sr[2] <= `Z;
|
| 2773 |
|
|
// N
|
| 2774 |
|
|
sr[3] <= `Rm;
|
| 2775 |
|
|
|
| 2776 |
|
|
// CMPI,CMPM,CMP
|
| 2777 |
|
|
if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b110) ||
|
| 2778 |
|
|
(ir[15:12] == 4'b1011 && (ir[8:6] == 3'b100 || ir[8:6] == 3'b101 || ir[8:6] == 3'b110) && ir[5:3] == 3'b001) ||
|
| 2779 |
|
|
(ir[15:12] == 4'b1011 && (ir[8:6] == 3'b000 || ir[8:6] == 3'b001 || ir[8:6] == 3'b010))
|
| 2780 |
|
|
) begin
|
| 2781 |
|
|
// C,V
|
| 2782 |
|
|
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
|
| 2783 |
|
|
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
|
| 2784 |
|
|
// X not affected
|
| 2785 |
|
|
end
|
| 2786 |
|
|
// ADDI,ADD to mem,ADD to Dn,ADDQ
|
| 2787 |
|
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b011) ||
|
| 2788 |
|
|
(ir[15:12] == 4'b1101) ||
|
| 2789 |
|
|
(ir[15:12] == 4'b0101 && ir[8] == 1'b0)
|
| 2790 |
|
|
) begin
|
| 2791 |
|
|
// C,X,V
|
| 2792 |
|
|
sr[0] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm);
|
| 2793 |
|
|
sr[4] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm); //=ccr[0];
|
| 2794 |
|
|
sr[1] <= (`Sm & `Dm & ~`Rm) | (~`Sm & ~`Dm & `Rm);
|
| 2795 |
|
|
end
|
| 2796 |
|
|
// SUBI,SUB to mem,SUB to Dn,SUBQ
|
| 2797 |
|
|
else if( (ir[15:12] == 4'b0000 && ir[11:9] == 3'b010) ||
|
| 2798 |
|
|
(ir[15:12] == 4'b1001) ||
|
| 2799 |
|
|
(ir[15:12] == 4'b0101 && ir[8] == 1'b1)
|
| 2800 |
|
|
) begin
|
| 2801 |
|
|
// C,X,V
|
| 2802 |
|
|
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
|
| 2803 |
|
|
sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];
|
| 2804 |
|
|
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
|
| 2805 |
|
|
end
|
| 2806 |
|
|
// ANDI,EORI,ORI,EOR,OR to mem,AND to mem,OR to Dn,AND to Dn
|
| 2807 |
|
|
else begin
|
| 2808 |
|
|
// C,V
|
| 2809 |
|
|
sr[0] <= 1'b0;
|
| 2810 |
|
|
sr[1] <= 1'b0;
|
| 2811 |
|
|
// X not affected
|
| 2812 |
|
|
end
|
| 2813 |
|
|
end
|
| 2814 |
|
|
|
| 2815 |
|
|
`ALU_ABCD_SBCD_ADDX_SUBX: begin // 259 LE
|
| 2816 |
|
|
// ABCD
|
| 2817 |
|
|
if( ir[14:12] == 3'b100 ) begin
|
| 2818 |
|
|
result[13:8] = {1'b0, operand1[3:0]} + {1'b0, operand2[3:0]} + {4'b0, sr[4]};
|
| 2819 |
|
|
result[19:14] = {1'b0, operand1[7:4]} + {1'b0, operand2[7:4]};
|
| 2820 |
|
|
|
| 2821 |
|
|
result[31:23] = operand1[7:0] + operand2[7:0] + {7'b0, sr[4]};
|
| 2822 |
|
|
|
| 2823 |
|
|
result[13:8] = (result[13:8] > 6'd9) ? (result[13:8] + 6'd6) : result[13:8];
|
| 2824 |
|
|
result[19:14] = (result[13:8] > 6'h1F) ? (result[19:14] + 6'd2) :
|
| 2825 |
|
|
(result[13:8] > 6'h0F) ? (result[19:14] + 6'd1) :
|
| 2826 |
|
|
result[19:14];
|
| 2827 |
|
|
result[19:14] = (result[19:14] > 6'd9) ? (result[19:14] + 6'd6) : result[19:14];
|
| 2828 |
|
|
|
| 2829 |
|
|
result[7:4] = result[17:14];
|
| 2830 |
|
|
result[3:0] = result[11:8];
|
| 2831 |
|
|
|
| 2832 |
|
|
// C
|
| 2833 |
|
|
sr[0] <= (result[19:14] > 6'd9) ? 1'b1 : 1'b0;
|
| 2834 |
|
|
// X = C
|
| 2835 |
|
|
sr[4] <= (result[19:14] > 6'd9) ? 1'b1 : 1'b0;
|
| 2836 |
|
|
|
| 2837 |
|
|
// V
|
| 2838 |
|
|
sr[1] <= (result[30] == 1'b0 && result[7] == 1'b1) ? 1'b1 : 1'b0;
|
| 2839 |
|
|
end
|
| 2840 |
|
|
// SBCD
|
| 2841 |
|
|
else if( ir[14:12] == 3'b000 ) begin
|
| 2842 |
|
|
|
| 2843 |
|
|
result[13:8] = 6'd32 + {2'b0, operand1[3:0]} - {2'b0, operand2[3:0]} - {5'b0, sr[4]};
|
| 2844 |
|
|
result[19:14] = 6'd32 + {2'b0, operand1[7:4]} - {2'b0, operand2[7:4]};
|
| 2845 |
|
|
|
| 2846 |
|
|
result[31:23] = operand1[7:0] - operand2[7:0] - {7'b0, sr[4]};
|
| 2847 |
|
|
|
| 2848 |
|
|
result[13:8] = (result[13:8] < 6'd32) ? (result[13:8] - 6'd6) : result[13:8];
|
| 2849 |
|
|
result[19:14] = (result[13:8] < 6'd16) ? (result[19:14] - 6'd2) :
|
| 2850 |
|
|
(result[13:8] < 6'd32) ? (result[19:14] - 6'd1) :
|
| 2851 |
|
|
result[19:14];
|
| 2852 |
|
|
result[19:14] = (result[19:14] < 6'd32 && result[31] == 1'b1) ? (result[19:14] - 6'd6) : result[19:14];
|
| 2853 |
|
|
|
| 2854 |
|
|
result[7:4] = result[17:14];
|
| 2855 |
|
|
result[3:0] = result[11:8];
|
| 2856 |
|
|
|
| 2857 |
|
|
// C
|
| 2858 |
|
|
sr[0] <= (result[19:14] < 6'd32) ? 1'b1 : 1'b0;
|
| 2859 |
|
|
// X = C
|
| 2860 |
|
|
sr[4] <= (result[19:14] < 6'd32) ? 1'b1 : 1'b0;
|
| 2861 |
|
|
|
| 2862 |
|
|
// V
|
| 2863 |
|
|
sr[1] <= (result[30] == 1'b1 && result[7] == 1'b0) ? 1'b1 : 1'b0;
|
| 2864 |
|
|
end
|
| 2865 |
|
|
// ADDX
|
| 2866 |
|
|
else if( ir[14:12] == 3'b101 ) result[31:0] = operand1[31:0] + operand2[31:0] + sr[4];
|
| 2867 |
|
|
// SUBX
|
| 2868 |
|
|
else if( ir[14:12] == 3'b001 ) result[31:0] = operand1[31:0] - operand2[31:0] - sr[4];
|
| 2869 |
|
|
|
| 2870 |
|
|
// Z
|
| 2871 |
|
|
sr[2] <= sr[2] & `Z;
|
| 2872 |
|
|
// N
|
| 2873 |
|
|
sr[3] <= `Rm;
|
| 2874 |
|
|
|
| 2875 |
|
|
// ADDX
|
| 2876 |
|
|
if(ir[14:12] == 3'b101 ) begin
|
| 2877 |
|
|
// C,X,V
|
| 2878 |
|
|
sr[0] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm);
|
| 2879 |
|
|
sr[4] <= (`Sm & `Dm) | (~`Rm & `Dm) | (`Sm & ~`Rm); //=ccr[0];
|
| 2880 |
|
|
sr[1] <= (`Sm & `Dm & ~`Rm) | (~`Sm & ~`Dm & `Rm);
|
| 2881 |
|
|
end
|
| 2882 |
|
|
// SUBX
|
| 2883 |
|
|
else if(ir[14:12] == 3'b001 ) begin
|
| 2884 |
|
|
// C,X,V
|
| 2885 |
|
|
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
|
| 2886 |
|
|
sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];
|
| 2887 |
|
|
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
|
| 2888 |
|
|
end
|
| 2889 |
|
|
end
|
| 2890 |
|
|
|
| 2891 |
|
|
`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR_prepare: begin
|
| 2892 |
|
|
|
| 2893 |
|
|
if(size == 2'b00) result[7:0] = operand1[7:0];
|
| 2894 |
|
|
else if(size == 2'b01) result[15:0] = operand1[15:0];
|
| 2895 |
|
|
else if(size == 2'b10) result[31:0] = operand1[31:0];
|
| 2896 |
|
|
|
| 2897 |
|
|
// X for ASL
|
| 2898 |
|
|
//if(operand2[5:0] > 6'b0 && ir[8] == 1'b1 && ((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) ) begin
|
| 2899 |
|
|
// X set to Dm
|
| 2900 |
|
|
// sr[4] <= `Dm;
|
| 2901 |
|
|
//end
|
| 2902 |
|
|
// else X not affected
|
| 2903 |
|
|
|
| 2904 |
|
|
// V cleared
|
| 2905 |
|
|
sr[1] <= 1'b0;
|
| 2906 |
|
|
// C for ROXL,ROXR: set to X
|
| 2907 |
|
|
if( (ir[7:6] == 2'b11 && ir[10:9] == 2'b10) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b10) ) begin
|
| 2908 |
|
|
sr[0] <= sr[4];
|
| 2909 |
|
|
end
|
| 2910 |
|
|
else begin
|
| 2911 |
|
|
// C cleared
|
| 2912 |
|
|
sr[0] <= 1'b0;
|
| 2913 |
|
|
end
|
| 2914 |
|
|
|
| 2915 |
|
|
// N set
|
| 2916 |
|
|
sr[3] <= `Rm;
|
| 2917 |
|
|
// Z set
|
| 2918 |
|
|
sr[2] <= `Z;
|
| 2919 |
|
|
end
|
| 2920 |
|
|
|
| 2921 |
|
|
`ALU_ASL_LSL_ROL_ROXL_ASR_LSR_ROR_ROXR: begin
|
| 2922 |
|
|
|
| 2923 |
|
|
// ASL
|
| 2924 |
|
|
if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) && ir[8] == 1'b1) begin
|
| 2925 |
|
|
result[31:0] = {operand1[30:0], 1'b0};
|
| 2926 |
|
|
|
| 2927 |
|
|
sr[1] <= (sr[1] == 1'b0)? (`Rm != `Dm) : 1'b1; // V
|
| 2928 |
|
|
sr[0] <= `Dm; // C
|
| 2929 |
|
|
sr[4] <= `Dm; // X
|
| 2930 |
|
|
end
|
| 2931 |
|
|
// LSL
|
| 2932 |
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b01) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b01)) && ir[8] == 1'b1) begin
|
| 2933 |
|
|
result[31:0] = {operand1[30:0], 1'b0};
|
| 2934 |
|
|
|
| 2935 |
|
|
sr[1] <= 1'b0; // V
|
| 2936 |
|
|
sr[0] <= `Dm; // C
|
| 2937 |
|
|
sr[4] <= `Dm; // X
|
| 2938 |
|
|
end
|
| 2939 |
|
|
// ROL
|
| 2940 |
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b11) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b11)) && ir[8] == 1'b1) begin
|
| 2941 |
|
|
result[31:0] = {operand1[30:0], `Dm};
|
| 2942 |
|
|
|
| 2943 |
|
|
sr[1] <= 1'b0; // V
|
| 2944 |
|
|
sr[0] <= `Dm; // C
|
| 2945 |
|
|
// X not affected
|
| 2946 |
|
|
end
|
| 2947 |
|
|
// ROXL
|
| 2948 |
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b10) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b10)) && ir[8] == 1'b1) begin
|
| 2949 |
|
|
result[31:0] = {operand1[30:0], sr[4]};
|
| 2950 |
|
|
|
| 2951 |
|
|
sr[1] <= 1'b0; // V
|
| 2952 |
|
|
sr[0] <= `Dm; // C
|
| 2953 |
|
|
sr[4] <= `Dm; // X
|
| 2954 |
|
|
end
|
| 2955 |
|
|
// ASR
|
| 2956 |
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b00) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b00)) && ir[8] == 1'b0) begin
|
| 2957 |
|
|
if(size == 2'b00) result[7:0] = { operand1[7], operand1[7:1] };
|
| 2958 |
|
|
else if(size == 2'b01) result[15:0] = { operand1[15], operand1[15:1] };
|
| 2959 |
|
|
else if(size == 2'b10) result[31:0] = { operand1[31], operand1[31:1] };
|
| 2960 |
|
|
|
| 2961 |
|
|
sr[1] <= 1'b0; // V
|
| 2962 |
|
|
sr[0] <= operand1[0]; // C
|
| 2963 |
|
|
sr[4] <= operand1[0]; // X
|
| 2964 |
|
|
end
|
| 2965 |
|
|
// LSR
|
| 2966 |
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b01) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b01)) && ir[8] == 1'b0) begin
|
| 2967 |
|
|
if(size == 2'b00) result[7:0] = { 1'b0, operand1[7:1] };
|
| 2968 |
|
|
else if(size == 2'b01) result[15:0] = { 1'b0, operand1[15:1] };
|
| 2969 |
|
|
else if(size == 2'b10) result[31:0] = { 1'b0, operand1[31:1] };
|
| 2970 |
|
|
|
| 2971 |
|
|
sr[1] <= 1'b0; // V
|
| 2972 |
|
|
sr[0] <= operand1[0]; // C
|
| 2973 |
|
|
sr[4] <= operand1[0]; // X
|
| 2974 |
|
|
end
|
| 2975 |
|
|
// ROR
|
| 2976 |
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b11) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b11)) && ir[8] == 1'b0) begin
|
| 2977 |
|
|
if(size == 2'b00) result[7:0] = { operand1[0], operand1[7:1] };
|
| 2978 |
|
|
else if(size == 2'b01) result[15:0] = { operand1[0], operand1[15:1] };
|
| 2979 |
|
|
else if(size == 2'b10) result[31:0] = { operand1[0], operand1[31:1] };
|
| 2980 |
|
|
|
| 2981 |
|
|
sr[1] <= 1'b0; // V
|
| 2982 |
|
|
sr[0] <= operand1[0]; // C
|
| 2983 |
|
|
// X not affected
|
| 2984 |
|
|
end
|
| 2985 |
|
|
// ROXR
|
| 2986 |
|
|
else if( ((ir[7:6] == 2'b11 && ir[10:9] == 2'b10) || (ir[7:6] != 2'b11 && ir[4:3] == 2'b10)) && ir[8] == 1'b0) begin
|
| 2987 |
|
|
if(size == 2'b00) result[7:0] = {sr[4], operand1[7:1]};
|
| 2988 |
|
|
else if(size == 2'b01) result[15:0] = {sr[4], operand1[15:1]};
|
| 2989 |
|
|
else if(size == 2'b10) result[31:0] = {sr[4], operand1[31:1]};
|
| 2990 |
|
|
|
| 2991 |
|
|
sr[1] <= 1'b0; // V
|
| 2992 |
|
|
sr[0] <= operand1[0]; // C
|
| 2993 |
|
|
sr[4] <= operand1[0]; // X
|
| 2994 |
|
|
end
|
| 2995 |
|
|
|
| 2996 |
|
|
// N set
|
| 2997 |
|
|
sr[3] <= `Rm;
|
| 2998 |
|
|
// Z set
|
| 2999 |
|
|
sr[2] <= `Z;
|
| 3000 |
|
|
end
|
| 3001 |
|
|
|
| 3002 |
|
|
`ALU_MOVE: begin
|
| 3003 |
|
|
result = operand1;
|
| 3004 |
|
|
|
| 3005 |
|
|
// X not affected
|
| 3006 |
|
|
// C cleared
|
| 3007 |
|
|
sr[0] <= 1'b0;
|
| 3008 |
|
|
// V cleared
|
| 3009 |
|
|
sr[1] <= 1'b0;
|
| 3010 |
|
|
|
| 3011 |
|
|
// N set
|
| 3012 |
|
|
sr[3] <= `Rm;
|
| 3013 |
|
|
// Z set
|
| 3014 |
|
|
sr[2] <= `Z;
|
| 3015 |
|
|
end
|
| 3016 |
|
|
|
| 3017 |
|
|
`ALU_ADDA_SUBA_CMPA_ADDQ_SUBQ: begin
|
| 3018 |
|
|
// ADDA: 1101
|
| 3019 |
|
|
// CMPA: 1011
|
| 3020 |
|
|
// SUBA: 1001
|
| 3021 |
|
|
// ADDQ,SUBQ: 0101 xxx0,1
|
| 3022 |
|
|
// operation requires that operand2 was sign extended
|
| 3023 |
|
|
|
| 3024 |
|
|
// ADDA,ADDQ
|
| 3025 |
|
|
if( ir[15:12] == 4'b1101 || (ir[15:12] == 4'b0101 && ir[8] == 1'b0) )
|
| 3026 |
|
|
result[31:0] = operand1[31:0] + operand2[31:0];
|
| 3027 |
|
|
// SUBA,CMPA,SUBQ
|
| 3028 |
|
|
else if( ir[15:12] == 4'b1001 || ir[15:12] == 4'b1011 || (ir[15:12] == 4'b0101 && ir[8] == 1'b1) )
|
| 3029 |
|
|
result[31:0] = operand1[31:0] - operand2[31:0];
|
| 3030 |
|
|
|
| 3031 |
|
|
// for CMPA
|
| 3032 |
|
|
if( ir[15:12] == 4'b1011 ) begin
|
| 3033 |
|
|
// Z
|
| 3034 |
|
|
sr[2] <= `Z;
|
| 3035 |
|
|
// N
|
| 3036 |
|
|
sr[3] <= `Rm;
|
| 3037 |
|
|
|
| 3038 |
|
|
// C,V
|
| 3039 |
|
|
sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
|
| 3040 |
|
|
sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
|
| 3041 |
|
|
// X not affected
|
| 3042 |
|
|
end
|
| 3043 |
|
|
// for ADDA,SUBA,ADDQ,SUBQ: ccr not affected
|
| 3044 |
|
|
end
|
| 3045 |
|
|
|
| 3046 |
|
|
`ALU_CHK: begin
|
| 3047 |
|
|
result[15:0] = operand1[15:0] - operand2[15:0];
|
| 3048 |
|
|
|
| 3049 |
|
|
// undocumented behavior: Z flag, see 68knotes.txt
|
| 3050 |
|
|
//sr[2] <= (operand1[15:0] == 16'b0) ? 1'b1 : 1'b0;
|
| 3051 |
|
|
// undocumented behavior: C,V flags, see 68knotes.txt
|
| 3052 |
|
|
//sr[0] <= 1'b0;
|
| 3053 |
|
|
//sr[1] <= 1'b0;
|
| 3054 |
|
|
|
| 3055 |
|
|
// C,X,V
|
| 3056 |
|
|
// sr[0] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm);
|
| 3057 |
|
|
// sr[4] <= (`Sm & ~`Dm) | (`Rm & ~`Dm) | (`Sm & `Rm); //=ccr[0];
|
| 3058 |
|
|
// sr[1] <= (~`Sm & `Dm & ~`Rm) | (`Sm & ~`Dm & `Rm);
|
| 3059 |
|
|
// +: 0-1, 0-0=0, 1-1=0
|
| 3060 |
|
|
// -: 0-0=1, 1-0, 1-1=1
|
| 3061 |
|
|
// operand1 - operand2 > 0
|
| 3062 |
|
|
if( operand1[15:0] != operand2[15:0] && ((~`Dm & `Sm) | (~`Dm & ~`Sm & ~`Rm) | (`Dm & `Sm & ~`Rm)) == 1'b1 ) begin
|
| 3063 |
|
|
// clear N
|
| 3064 |
|
|
sr[3] <= 1'b0;
|
| 3065 |
|
|
special <= 2'b01;
|
| 3066 |
|
|
end
|
| 3067 |
|
|
// operand1 < 0
|
| 3068 |
|
|
else if( operand1[15] == 1'b1 ) begin
|
| 3069 |
|
|
// set N
|
| 3070 |
|
|
sr[3] <= 1'b1;
|
| 3071 |
|
|
special <= 2'b01;
|
| 3072 |
|
|
end
|
| 3073 |
|
|
// no trap
|
| 3074 |
|
|
else begin
|
| 3075 |
|
|
// N undefined: not affected
|
| 3076 |
|
|
special <= 2'b00;
|
| 3077 |
|
|
end
|
| 3078 |
|
|
|
| 3079 |
|
|
// X not affected
|
| 3080 |
|
|
end
|
| 3081 |
|
|
|
| 3082 |
|
|
`ALU_MULS_MULU_DIVS_DIVU: begin // 2206 LE, 106 MHz
|
| 3083 |
|
|
|
| 3084 |
|
|
// division by 0
|
| 3085 |
|
|
if( ir[15:12] == 4'b1000 && operand2[15:0] == 16'b0 ) begin
|
| 3086 |
|
|
// X not affected
|
| 3087 |
|
|
// C cleared
|
| 3088 |
|
|
sr[0] <= 1'b0;
|
| 3089 |
|
|
// V,Z,N undefined: cleared
|
| 3090 |
|
|
sr[1] <= 1'b0;
|
| 3091 |
|
|
sr[2] <= 1'b0;
|
| 3092 |
|
|
sr[3] <= 1'b0;
|
| 3093 |
|
|
|
| 3094 |
|
|
// set trap
|
| 3095 |
|
|
special <= 2'b01;
|
| 3096 |
|
|
end
|
| 3097 |
|
|
// division overflow: divu, divs
|
| 3098 |
|
|
else if( ((ir[15:12] == 4'b1000 && ir[8] == 1'b0) && (divu_quotient[31:16] != 16'd0)) ||
|
| 3099 |
|
|
((ir[15:12] == 4'b1000 && ir[8] == 1'b1) && (divs_quotient[31:16] != {16{divs_quotient[15]}}))
|
| 3100 |
|
|
) begin
|
| 3101 |
|
|
// X not affected
|
| 3102 |
|
|
// C cleared
|
| 3103 |
|
|
sr[0] <= 1'b0;
|
| 3104 |
|
|
// V set
|
| 3105 |
|
|
sr[1] <= 1'b1;
|
| 3106 |
|
|
// Z,N undefined: cleared and set
|
| 3107 |
|
|
sr[2] <= 1'b0;
|
| 3108 |
|
|
sr[3] <= 1'b1;
|
| 3109 |
|
|
|
| 3110 |
|
|
// set trap
|
| 3111 |
|
|
special <= 2'b10;
|
| 3112 |
|
|
end
|
| 3113 |
|
|
// division
|
| 3114 |
|
|
else if( ir[15:12] == 4'b1000 ) begin
|
| 3115 |
|
|
result[31:0] <= (ir[8] == 1'b0)? {divu_remainder[15:0], divu_quotient[15:0]} : {divs_remainder[15:0], divs_quotient[15:0]};
|
| 3116 |
|
|
|
| 3117 |
|
|
// X not affected
|
| 3118 |
|
|
// C cleared
|
| 3119 |
|
|
sr[0] <= 1'b0;
|
| 3120 |
|
|
// V cleared
|
| 3121 |
|
|
sr[1] <= 1'b0;
|
| 3122 |
|
|
// Z
|
| 3123 |
|
|
sr[2] <= (ir[8] == 1'b0)? (divu_quotient[15:0] == 16'b0) : (divs_quotient[15:0] == 16'b0);
|
| 3124 |
|
|
// N
|
| 3125 |
|
|
sr[3] <= (ir[8] == 1'b0)? (divu_quotient[15] == 1'b1) : (divs_quotient[15] == 1'b1);
|
| 3126 |
|
|
|
| 3127 |
|
|
// set trap
|
| 3128 |
|
|
special <= 2'b00;
|
| 3129 |
|
|
end
|
| 3130 |
|
|
// multiplication
|
| 3131 |
|
|
else if( ir[15:12] == 4'b1100 ) begin
|
| 3132 |
|
|
result[31:0] <= (ir[8] == 1'b0)? mulu_result[31:0] : muls_result[31:0];
|
| 3133 |
|
|
|
| 3134 |
|
|
// X not affected
|
| 3135 |
|
|
// C cleared
|
| 3136 |
|
|
sr[0] <= 1'b0;
|
| 3137 |
|
|
// V cleared
|
| 3138 |
|
|
sr[1] <= 1'b0;
|
| 3139 |
|
|
// Z
|
| 3140 |
|
|
sr[2] <= (ir[8] == 1'b0)? (mulu_result[31:0] == 32'b0) : (muls_result[31:0] == 32'b0);
|
| 3141 |
|
|
// N
|
| 3142 |
|
|
sr[3] <= (ir[8] == 1'b0)? (mulu_result[31] == 1'b1) : (muls_result[31] == 1'b1);
|
| 3143 |
|
|
|
| 3144 |
|
|
// set trap
|
| 3145 |
|
|
special <= 2'b00;
|
| 3146 |
|
|
end
|
| 3147 |
|
|
end
|
| 3148 |
|
|
|
| 3149 |
|
|
|
| 3150 |
|
|
`ALU_BCHG_BCLR_BSET_BTST: begin // 97 LE
|
| 3151 |
|
|
// byte
|
| 3152 |
|
|
if( ir[5:3] != 3'b000 ) begin
|
| 3153 |
|
|
sr[2] <= ~(operand1[ operand2[2:0] ]);
|
| 3154 |
|
|
result = operand1;
|
| 3155 |
|
|
result[ operand2[2:0] ] = (ir[7:6] == 2'b01) ? ~(operand1[ operand2[2:0] ]) : (ir[7:6] == 2'b10) ? 1'b0 : 1'b1;
|
| 3156 |
|
|
end
|
| 3157 |
|
|
// long
|
| 3158 |
|
|
else if( ir[5:3] == 3'b000 ) begin
|
| 3159 |
|
|
sr[2] <= ~(operand1[ operand2[4:0] ]);
|
| 3160 |
|
|
result = operand1;
|
| 3161 |
|
|
result[ operand2[4:0] ] = (ir[7:6] == 2'b01) ? ~(operand1[ operand2[4:0] ]) : (ir[7:6] == 2'b10) ? 1'b0 : 1'b1;
|
| 3162 |
|
|
end
|
| 3163 |
|
|
|
| 3164 |
|
|
// C,V,N,X not affected
|
| 3165 |
|
|
end
|
| 3166 |
|
|
|
| 3167 |
|
|
`ALU_TAS: begin
|
| 3168 |
|
|
result[7:0] <= { 1'b1, operand1[6:0] };
|
| 3169 |
|
|
|
| 3170 |
|
|
// X not affected
|
| 3171 |
|
|
// C cleared
|
| 3172 |
|
|
sr[0] <= 1'b0;
|
| 3173 |
|
|
// V cleared
|
| 3174 |
|
|
sr[1] <= 1'b0;
|
| 3175 |
|
|
|
| 3176 |
|
|
// N set
|
| 3177 |
|
|
sr[3] <= (operand1[7] == 1'b1);
|
| 3178 |
|
|
// Z set
|
| 3179 |
|
|
sr[2] <= (operand1[7:0] == 8'b0);
|
| 3180 |
|
|
end
|
| 3181 |
|
|
|
| 3182 |
|
|
|
| 3183 |
|
|
`ALU_NEGX_CLR_NEG_NOT_NBCD_SWAP_EXT: begin
|
| 3184 |
|
|
// NEGX
|
| 3185 |
|
|
if( ir[11:8] == 4'b0000 ) result = 32'b0 - operand1[31:0] - sr[4];
|
| 3186 |
|
|
// CLR
|
| 3187 |
|
|
else if( ir[11:8] == 4'b0010 ) result = 32'b0;
|
| 3188 |
|
|
// NEG
|
| 3189 |
|
|
else if( ir[11:8] == 4'b0100 ) result = 32'b0 - operand1[31:0];
|
| 3190 |
|
|
// NOT
|
| 3191 |
|
|
else if( ir[11:8] == 4'b0110 ) result = ~operand1[31:0];
|
| 3192 |
|
|
// NBCD
|
| 3193 |
|
|
else if( ir[11:6] == 6'b1000_00 ) begin
|
| 3194 |
|
|
|
| 3195 |
|
|
result[3:0] = 5'd25 - operand1[3:0];
|
| 3196 |
|
|
result[7:4] = (operand1[3:0] > 4'd9) ? (5'd24 - operand1[7:4]) : (5'd25 - operand1[7:4]);
|
| 3197 |
|
|
|
| 3198 |
|
|
if(sr[4] == 1'b0 && result[3:0] == 4'd9 && result[7:4] == 4'd9) begin
|
| 3199 |
|
|
result[3:0] = 4'd0;
|
| 3200 |
|
|
result[7:4] = 4'd0;
|
| 3201 |
|
|
end
|
| 3202 |
|
|
else if(sr[4] == 1'b0 && (result[3:0] == 4'd9 || result[3:0] == 4'd15)) begin
|
| 3203 |
|
|
result[3:0] = 4'd0;
|
| 3204 |
|
|
result[7:4] = result[7:4] + 4'd1;
|
| 3205 |
|
|
end
|
| 3206 |
|
|
else if(sr[4] == 1'b0) begin
|
| 3207 |
|
|
result[3:0] = result[3:0] + 4'd1;
|
| 3208 |
|
|
end
|
| 3209 |
|
|
|
| 3210 |
|
|
//V undefined: unchanged
|
| 3211 |
|
|
//Z
|
| 3212 |
|
|
sr[2] <= sr[2] & `Z;
|
| 3213 |
|
|
//C,X
|
| 3214 |
|
|
sr[0] <= (operand1[7:0] == 8'd0 && sr[4] == 1'b0) ? 1'b0 : 1'b1;
|
| 3215 |
|
|
sr[4] <= (operand1[7:0] == 8'd0 && sr[4] == 1'b0) ? 1'b0 : 1'b1; //=C
|
| 3216 |
|
|
end
|
| 3217 |
|
|
// SWAP
|
| 3218 |
|
|
else if( ir[11:6] == 6'b1000_01 ) result = { operand1[15:0], operand1[31:16] };
|
| 3219 |
|
|
// EXT byte to word
|
| 3220 |
|
|
else if( ir[11:6] == 6'b1000_10 ) result = { result[31:16], {8{operand1[7]}}, operand1[7:0] };
|
| 3221 |
|
|
// EXT word to long
|
| 3222 |
|
|
else if( ir[11:6] == 6'b1000_11 ) result = { {16{operand1[15]}}, operand1[15:0] };
|
| 3223 |
|
|
|
| 3224 |
|
|
// N set if negative else clear
|
| 3225 |
|
|
sr[3] <= `Rm;
|
| 3226 |
|
|
|
| 3227 |
|
|
// CLR,NOT,SWAP,EXT
|
| 3228 |
|
|
if( ir[11:8] == 4'b0010 || ir[11:8] == 4'b0110 || ir[11:6] == 6'b1000_01 || ir[11:7] == 5'b1000_1 ) begin
|
| 3229 |
|
|
// X not affected
|
| 3230 |
|
|
// C,V cleared
|
| 3231 |
|
|
sr[0] <= 1'b0;
|
| 3232 |
|
|
sr[1] <= 1'b0;
|
| 3233 |
|
|
// Z set
|
| 3234 |
|
|
sr[2] <= `Z;
|
| 3235 |
|
|
end
|
| 3236 |
|
|
// NEGX
|
| 3237 |
|
|
else if( ir[11:8] == 4'b0000 ) begin
|
| 3238 |
|
|
// C set if borrow
|
| 3239 |
|
|
sr[0] <= `Dm | `Rm;
|
| 3240 |
|
|
// X=C
|
| 3241 |
|
|
sr[4] <= `Dm | `Rm;
|
| 3242 |
|
|
// V set if overflow
|
| 3243 |
|
|
sr[1] <= `Dm & `Rm;
|
| 3244 |
|
|
// Z cleared if nonzero else unchanged
|
| 3245 |
|
|
sr[2] <= sr[2] & `Z;
|
| 3246 |
|
|
end
|
| 3247 |
|
|
// NEG
|
| 3248 |
|
|
else if( ir[11:8] == 4'b0100 ) begin
|
| 3249 |
|
|
// C clear if zero else set
|
| 3250 |
|
|
sr[0] <= `Dm | `Rm;
|
| 3251 |
|
|
// X=C
|
| 3252 |
|
|
sr[4] <= `Dm | `Rm;
|
| 3253 |
|
|
// V set if overflow
|
| 3254 |
|
|
sr[1] <= `Dm & `Rm;
|
| 3255 |
|
|
// Z set if zero else clear
|
| 3256 |
|
|
sr[2] <= `Z;
|
| 3257 |
|
|
end
|
| 3258 |
|
|
end
|
| 3259 |
|
|
|
| 3260 |
|
|
|
| 3261 |
|
|
`ALU_SIMPLE_LONG_ADD: begin
|
| 3262 |
|
|
result <= operand1[31:0] + operand2[31:0];
|
| 3263 |
|
|
|
| 3264 |
|
|
// CCR not affected
|
| 3265 |
|
|
end
|
| 3266 |
|
|
|
| 3267 |
|
|
`ALU_SIMPLE_LONG_SUB: begin
|
| 3268 |
|
|
result <= operand1[31:0] - operand2[31:0];
|
| 3269 |
|
|
|
| 3270 |
|
|
// CCR not affected
|
| 3271 |
|
|
end
|
| 3272 |
|
|
|
| 3273 |
|
|
`ALU_MOVE_TO_CCR_SR_RTE_RTR_STOP_LOGIC_TO_CCR_SR: begin
|
| 3274 |
|
|
|
| 3275 |
|
|
// MOVE TO SR,RTE,STOP,ORI to SR,ANDI to SR,EORI to SR
|
| 3276 |
|
|
if( ir[15:8] == 8'b0100_0110 || ir[15:0] == 16'b0100_1110_0111_0011 || ir[15:0] == 16'b0100_1110_0111_0010 ||
|
| 3277 |
|
|
ir[15:0] == 16'b0000_000_0_01_111100 || ir[15:0] == 16'b0000_001_0_01_111100 || ir[15:0] == 16'b0000_101_0_01_111100
|
| 3278 |
|
|
) sr <= { operand1[15], 1'b0, operand1[13], 2'b0, operand1[10:8], 3'b0, operand1[4:0] };
|
| 3279 |
|
|
// MOVE TO CCR,RTR,ORI to CCR,ANDI to CCR,EORI to CCR
|
| 3280 |
|
|
else if( ir[15:8] == 8'b0100_0100 || ir[15:0] == 16'b0100_1110_0111_0111 ||
|
| 3281 |
|
|
ir[15:0] == 16'b0000_000_0_00_111100 || ir[15:0] == 16'b0000_001_0_00_111100 || ir[15:0] == 16'b0000_101_0_00_111100
|
| 3282 |
|
|
) sr <= { sr[15:8], 3'b0, operand1[4:0] };
|
| 3283 |
|
|
end
|
| 3284 |
|
|
|
| 3285 |
|
|
`ALU_SIMPLE_MOVE: begin
|
| 3286 |
|
|
result <= operand1;
|
| 3287 |
|
|
|
| 3288 |
|
|
// CCR not affected
|
| 3289 |
|
|
end
|
| 3290 |
|
|
|
| 3291 |
|
|
`ALU_LINK_MOVE: begin
|
| 3292 |
|
|
if(ir[3:0] == 3'b111) begin
|
| 3293 |
|
|
result <= operand1 - 32'd4;
|
| 3294 |
|
|
end
|
| 3295 |
|
|
else begin
|
| 3296 |
|
|
result <= operand1;
|
| 3297 |
|
|
end
|
| 3298 |
|
|
|
| 3299 |
|
|
// CCR not affected
|
| 3300 |
|
|
end
|
| 3301 |
|
|
|
| 3302 |
|
|
endcase
|
| 3303 |
|
|
end
|
| 3304 |
|
|
end
|
| 3305 |
|
|
|
| 3306 |
|
|
endmodule
|
| 3307 |
|
|
|
| 3308 |
|
|
/***********************************************************************************************************************
|
| 3309 |
|
|
* Microcode branch
|
| 3310 |
|
|
**********************************************************************************************************************/
|
| 3311 |
|
|
|
| 3312 |
|
|
/*! \brief Select the next microcode word to execute.
|
| 3313 |
|
|
*
|
| 3314 |
|
|
* The microcode_branch module is responsible for selecting the next microcode word to execute. This decision is based
|
| 3315 |
|
|
* on the value of the current microcode word, the value of the interrupt privilege level, the state of the current
|
| 3316 |
|
|
* bus cycle and other internal signals.
|
| 3317 |
|
|
*
|
| 3318 |
|
|
* The microcode_branch module implements a simple stack for the microcode addresses. This makes it possible to call
|
| 3319 |
|
|
* subroutines inside the microcode.
|
| 3320 |
|
|
*/
|
| 3321 |
|
|
module microcode_branch(
|
| 3322 |
|
|
input clock,
|
| 3323 |
|
|
input reset_n,
|
| 3324 |
|
|
|
| 3325 |
|
|
input [4:0] movem_loop,
|
| 3326 |
|
|
input [15:0] movem_reg,
|
| 3327 |
|
|
input [31:0] operand2,
|
| 3328 |
|
|
input [1:0] special,
|
| 3329 |
|
|
input condition,
|
| 3330 |
|
|
input [31:0] result,
|
| 3331 |
|
|
input overflow,
|
| 3332 |
|
|
input stop_flag,
|
| 3333 |
|
|
input [15:0] ir,
|
| 3334 |
|
|
input [7:0] decoder_trap,
|
| 3335 |
|
|
input trace_flag,
|
| 3336 |
|
|
input group_0_flag,
|
| 3337 |
|
|
input [2:0] interrupt_mask,
|
| 3338 |
|
|
|
| 3339 |
|
|
input [8:0] load_ea,
|
| 3340 |
|
|
input [8:0] perform_ea_read,
|
| 3341 |
|
|
input [8:0] perform_ea_write,
|
| 3342 |
|
|
input [8:0] save_ea,
|
| 3343 |
|
|
input [8:0] decoder_micropc,
|
| 3344 |
|
|
|
| 3345 |
|
|
input prefetch_ir_valid_32,
|
| 3346 |
|
|
input prefetch_ir_valid,
|
| 3347 |
|
|
input jmp_address_trap,
|
| 3348 |
|
|
input jmp_bus_trap,
|
| 3349 |
|
|
input finished,
|
| 3350 |
|
|
|
| 3351 |
|
|
input [3:0] branch_control,
|
| 3352 |
|
|
input [3:0] branch_offset,
|
| 3353 |
|
|
output [8:0] micro_pc
|
| 3354 |
|
|
);
|
| 3355 |
|
|
|
| 3356 |
|
|
reg [8:0] micro_pc_0 = 9'd0;
|
| 3357 |
|
|
reg [8:0] micro_pc_1;
|
| 3358 |
|
|
reg [8:0] micro_pc_2;
|
| 3359 |
|
|
reg [8:0] micro_pc_3;
|
| 3360 |
|
|
|
| 3361 |
|
|
assign micro_pc =
|
| 3362 |
|
|
(reset_n == 1'b0) ? 9'd0 :
|
| 3363 |
|
|
(jmp_address_trap == 1'b1 || jmp_bus_trap == 1'b1) ? `MICROPC_ADDRESS_BUS_TRAP :
|
| 3364 |
|
|
( (branch_control == `BRANCH_movem_loop && movem_loop == 5'b10000) ||
|
| 3365 |
|
|
(branch_control == `BRANCH_movem_reg && movem_reg[0] == 0) ||
|
| 3366 |
|
|
(branch_control == `BRANCH_operand2 && operand2[5:0] == 6'b0) ||
|
| 3367 |
|
|
(branch_control == `BRANCH_special_01 && special != 2'b01) ||
|
| 3368 |
|
|
(branch_control == `BRANCH_special_10 && special == 2'b10) ||
|
| 3369 |
|
|
(branch_control == `BRANCH_condition_0 && condition == 1'b0) ||
|
| 3370 |
|
|
(branch_control == `BRANCH_condition_1 && condition == 1'b1) ||
|
| 3371 |
|
|
(branch_control == `BRANCH_result && result[15:0] == 16'hFFFF) ||
|
| 3372 |
|
|
(branch_control == `BRANCH_V && overflow == 1'b0) ||
|
| 3373 |
|
|
(branch_control == `BRANCH_movep_16 && ir[6] == 1'b0) ||
|
| 3374 |
|
|
(branch_control == `BRANCH_stop_flag_wait_ir_decode && stop_flag == 1'b1) ||
|
| 3375 |
|
|
(branch_control == `BRANCH_ir && ir[7:0] != 8'b0) ||
|
| 3376 |
|
|
(branch_control == `BRANCH_trace_flag_and_interrupt && trace_flag == 1'b0 && interrupt_mask != 3'b000) ||
|
| 3377 |
|
|
(branch_control == `BRANCH_group_0_flag && group_0_flag == 1'b0)
|
| 3378 |
|
|
) ? micro_pc_0 + { 5'd0, branch_offset } :
|
| 3379 |
|
|
(branch_control == `BRANCH_stop_flag_wait_ir_decode && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0) ? decoder_micropc :
|
| 3380 |
|
|
(branch_control == `BRANCH_trace_flag_and_interrupt && trace_flag == 1'b0 && interrupt_mask == 3'b000) ? `MICROPC_MAIN_LOOP :
|
| 3381 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_jump_to_main_loop) ? `MICROPC_MAIN_LOOP :
|
| 3382 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_load_ea && load_ea != 9'd0) ? load_ea :
|
| 3383 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_perform_ea_read) ? perform_ea_read :
|
| 3384 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_perform_ea_write) ? perform_ea_write :
|
| 3385 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_save_ea && save_ea != 9'd0) ? save_ea :
|
| 3386 |
|
|
|
| 3387 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_read && load_ea != 9'd0) ? load_ea :
|
| 3388 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_read && load_ea == 9'd0) ? perform_ea_read :
|
| 3389 |
|
|
|
| 3390 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_write) ? perform_ea_write :
|
| 3391 |
|
|
|
| 3392 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_call_trap) ? `MICROPC_TRAP_ENTRY :
|
| 3393 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_return) ? micro_pc_1 :
|
| 3394 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_interrupt_mask && interrupt_mask == 3'b000) ? `MICROPC_MAIN_LOOP :
|
| 3395 |
|
|
( (branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_wait_finished && finished == 1'b0) ||
|
| 3396 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_wait_prefetch_valid && prefetch_ir_valid == 1'b0) ||
|
| 3397 |
|
|
(branch_control == `BRANCH_procedure && branch_offset == `PROCEDURE_wait_prefetch_valid_32 && prefetch_ir_valid_32 == 1'b0) ||
|
| 3398 |
|
|
(branch_control == `BRANCH_stop_flag_wait_ir_decode && prefetch_ir_valid == 1'b0)
|
| 3399 |
|
|
) ? micro_pc_0 :
|
| 3400 |
|
|
micro_pc_0 + 9'd1
|
| 3401 |
|
|
;
|
| 3402 |
|
|
|
| 3403 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 3404 |
|
|
if(reset_n == 1'b0) micro_pc_0 <= 9'd0;
|
| 3405 |
|
|
else micro_pc_0 <= micro_pc;
|
| 3406 |
|
|
end
|
| 3407 |
|
|
|
| 3408 |
|
|
always @(posedge clock or negedge reset_n) begin
|
| 3409 |
|
|
if(reset_n == 1'b0) begin
|
| 3410 |
|
|
micro_pc_1 <= 9'd0;
|
| 3411 |
|
|
micro_pc_2 <= 9'd0;
|
| 3412 |
|
|
micro_pc_3 <= 9'd0;
|
| 3413 |
|
|
end
|
| 3414 |
|
|
else if(branch_control == `BRANCH_stop_flag_wait_ir_decode && prefetch_ir_valid == 1'b1 && decoder_trap == 8'd0)
|
| 3415 |
|
|
begin
|
| 3416 |
|
|
micro_pc_1 <= micro_pc_0 + { 5'd0, branch_offset };
|
| 3417 |
|
|
micro_pc_2 <= micro_pc_1;
|
| 3418 |
|
|
micro_pc_3 <= micro_pc_2;
|
| 3419 |
|
|
end
|
| 3420 |
|
|
else if(branch_control == `BRANCH_procedure) begin
|
| 3421 |
|
|
if(branch_offset == `PROCEDURE_call_read && load_ea != 9'd0) begin
|
| 3422 |
|
|
micro_pc_1 <= perform_ea_read;
|
| 3423 |
|
|
micro_pc_2 <= micro_pc_0 + 9'd1;
|
| 3424 |
|
|
micro_pc_3 <= micro_pc_1;
|
| 3425 |
|
|
end
|
| 3426 |
|
|
else if(branch_offset == `PROCEDURE_call_read && load_ea == 9'd0) begin
|
| 3427 |
|
|
micro_pc_1 <= micro_pc_0 + 9'd1;
|
| 3428 |
|
|
micro_pc_2 <= micro_pc_1;
|
| 3429 |
|
|
micro_pc_3 <= micro_pc_2;
|
| 3430 |
|
|
end
|
| 3431 |
|
|
else if(branch_offset == `PROCEDURE_call_write && save_ea != 9'd0) begin
|
| 3432 |
|
|
micro_pc_1 <= save_ea;
|
| 3433 |
|
|
micro_pc_2 <= micro_pc_1;
|
| 3434 |
|
|
micro_pc_3 <= micro_pc_2;
|
| 3435 |
|
|
end
|
| 3436 |
|
|
else if((branch_offset == `PROCEDURE_call_load_ea && load_ea != 9'd0) ||
|
| 3437 |
|
|
(branch_offset == `PROCEDURE_call_perform_ea_read) ||
|
| 3438 |
|
|
(branch_offset == `PROCEDURE_call_perform_ea_write) ||
|
| 3439 |
|
|
(branch_offset == `PROCEDURE_call_save_ea && save_ea != 9'd0) ||
|
| 3440 |
|
|
(branch_offset == `PROCEDURE_call_trap) )
|
| 3441 |
|
|
begin
|
| 3442 |
|
|
micro_pc_1 <= micro_pc_0 + 9'd1;
|
| 3443 |
|
|
micro_pc_2 <= micro_pc_1;
|
| 3444 |
|
|
micro_pc_3 <= micro_pc_2;
|
| 3445 |
|
|
end
|
| 3446 |
|
|
else if(branch_offset == `PROCEDURE_return) begin
|
| 3447 |
|
|
micro_pc_1 <= micro_pc_2;
|
| 3448 |
|
|
micro_pc_2 <= micro_pc_3;
|
| 3449 |
|
|
micro_pc_3 <= 9'd0;
|
| 3450 |
|
|
end
|
| 3451 |
|
|
else if(branch_offset == `PROCEDURE_push_micropc) begin
|
| 3452 |
|
|
micro_pc_1 <= micro_pc_0;
|
| 3453 |
|
|
micro_pc_2 <= micro_pc_1;
|
| 3454 |
|
|
micro_pc_3 <= micro_pc_2;
|
| 3455 |
|
|
end
|
| 3456 |
|
|
else if(branch_offset == `PROCEDURE_pop_micropc) begin
|
| 3457 |
|
|
micro_pc_1 <= micro_pc_2;
|
| 3458 |
|
|
micro_pc_2 <= micro_pc_3;
|
| 3459 |
|
|
micro_pc_3 <= 9'd0;
|
| 3460 |
|
|
end
|
| 3461 |
|
|
end
|
| 3462 |
|
|
end
|
| 3463 |
|
|
|
| 3464 |
|
|
endmodule
|
