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[/] [ao68000/] [trunk/] [tests/] [soc_for_linux_on_terasic_de2_70/] [verilog/] [early_boot.v] - Blame information for rev 12

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1 12 alfik 
/*
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 * Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without modification, are
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 * permitted provided that the following conditions are met:
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 *
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 *  1. Redistributions of source code must retain the above copyright notice, this list of
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 *     conditions and the following disclaimer.
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 *
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 *  2. Redistributions in binary form must reproduce the above copyright notice, this list
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 *     of conditions and the following disclaimer in the documentation and/or other materials
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 *     provided with the distribution.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
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 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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module early_boot(
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        input CLK_I,
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        input RST_I,
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        output reg CYC_O,
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        output reg [31:0] DAT_O,
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        output reg STB_O,
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        output reg WE_O,
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        output reg [31:2] ADR_O,
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        output [3:0] SEL_O,
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        input [31:0] DAT_I,
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        input ACK_I,
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        input ERR_I,
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        input RTY_I,
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        //****************** OTHER
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        //finished loading
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        output loading_finished_o
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);
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assign SEL_O = 4'b1111;
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assign loading_finished_o = (state == S_FINISHED) ? 1'b1 : 1'b0;
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reg [3:0] state;
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reg [9:0] wait_counter;
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parameter [3:0]
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        S_CHECK_STATUS          = 4'd0,
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        S_CHECK_STATUS_2        = 4'd1,
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        S_CHECK_STATUS_3        = 4'd2,
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        S_SET_SIZE                      = 4'd3,
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        S_SET_SIZE_2            = 4'd4,
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        S_SET_CONTROL           = 4'd5,
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        S_SET_CONTROL_2         = 4'd6,
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        S_CHECK_FINISHED        = 4'd7,
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        S_CHECK_FINISHED_2      = 4'd8,
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        S_CHECK_FINISHED_3      = 4'd9,
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        S_FINISHED                      = 4'd10;
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always @(posedge CLK_I) begin
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        if(RST_I == 1'b1) begin
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                CYC_O <= 1'b0;
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                DAT_O <= 32'd0;
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                STB_O <= 1'b0;
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                WE_O <= 1'b0;
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                ADR_O <= 30'd0;
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                state <= S_CHECK_STATUS;
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                wait_counter <= 10'd0;
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        end
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        else if(state == S_CHECK_STATUS) begin
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                CYC_O <= 1'b1;
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                DAT_O <= 32'd0;
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                STB_O <= 1'b1;
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                WE_O <= 1'b0;
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                ADR_O <= 30'h30000000;
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                state <= S_CHECK_STATUS_2;
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        end
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        else if(state == S_CHECK_STATUS_2) begin
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                if(ACK_I == 1'b1) begin
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                        CYC_O <= 1'b0;
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                        STB_O <= 1'b0;
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                        if(DAT_I == 32'd2) begin
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                                state <= S_SET_SIZE;
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                        end
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                        else begin
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                                state <= S_CHECK_STATUS_3;
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                        end
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                end
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        end
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        else if(state == S_CHECK_STATUS_3) begin
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                if(wait_counter == 10'd1023) begin
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                        wait_counter <= 10'd0;
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                        state <= S_CHECK_STATUS;
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                end
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                else wait_counter <= wait_counter + 10'd1;
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        end
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        else if(state == S_SET_SIZE) begin
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                CYC_O <= 1'b1;
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                DAT_O <= 32'd2048;
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                STB_O <= 1'b1;
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                WE_O <= 1'b1;
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                ADR_O <= 30'h30000002;
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                state <= S_SET_SIZE_2;
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        end
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        else if(state == S_SET_SIZE_2) begin
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                if(ACK_I == 1'b1) begin
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                        CYC_O <= 1'b0;
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                        STB_O <= 1'b0;
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                        state <= S_SET_CONTROL;
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                end
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        end
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        else if(state == S_SET_CONTROL) begin
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                CYC_O <= 1'b1;
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                DAT_O <= 32'd2;
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                STB_O <= 1'b1;
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                WE_O <= 1'b1;
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                ADR_O <= 30'h30000003;
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                state <= S_SET_CONTROL_2;
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        end
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        else if(state == S_SET_CONTROL_2) begin
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                if(ACK_I == 1'b1) begin
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                        CYC_O <= 1'b0;
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                        STB_O <= 1'b0;
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                        state <= S_CHECK_FINISHED;
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                end
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        end
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        else if(state == S_CHECK_FINISHED) begin
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                CYC_O <= 1'b1;
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                DAT_O <= 32'd0;
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                STB_O <= 1'b1;
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                WE_O <= 1'b0;
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                ADR_O <= 30'h30000000;
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                state <= S_CHECK_FINISHED_2;
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        end
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        else if(state == S_CHECK_FINISHED_2) begin
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                if(ACK_I == 1'b1) begin
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                        CYC_O <= 1'b0;
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                        STB_O <= 1'b0;
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                        if(DAT_I == 32'd2) begin //idle
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                                state <= S_FINISHED;
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                        end
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                        else begin
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                                state <= S_CHECK_FINISHED_3;
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                        end
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                end
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        end
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        else if(state == S_CHECK_FINISHED_3) begin
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                if(wait_counter == 10'd1023) begin
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                        wait_counter <= 10'd0;
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                        state <= S_CHECK_FINISHED;
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                end
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                else wait_counter <= wait_counter + 10'd1;
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        end
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        else if(state == S_FINISHED) begin
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        end
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end
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endmodule
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