| 1 |
12 |
alfik |
/*
|
| 2 |
|
|
* Copyright 2010, Aleksander Osman, alfik@poczta.fm. All rights reserved.
|
| 3 |
|
|
*
|
| 4 |
|
|
* Redistribution and use in source and binary forms, with or without modification, are
|
| 5 |
|
|
* permitted provided that the following conditions are met:
|
| 6 |
|
|
*
|
| 7 |
|
|
* 1. Redistributions of source code must retain the above copyright notice, this list of
|
| 8 |
|
|
* conditions and the following disclaimer.
|
| 9 |
|
|
*
|
| 10 |
|
|
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
|
| 11 |
|
|
* of conditions and the following disclaimer in the documentation and/or other materials
|
| 12 |
|
|
* provided with the distribution.
|
| 13 |
|
|
*
|
| 14 |
|
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
|
| 15 |
|
|
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
|
| 16 |
|
|
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
|
| 17 |
|
|
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
| 18 |
|
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
| 19 |
|
|
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
| 20 |
|
|
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
|
| 21 |
|
|
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
| 22 |
|
|
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
| 23 |
|
|
*/
|
| 24 |
|
|
|
| 25 |
|
|
module serial_txd(
|
| 26 |
|
|
input CLK_I,
|
| 27 |
|
|
input RST_I,
|
| 28 |
|
|
|
| 29 |
|
|
//slave
|
| 30 |
|
|
input [7:0] DAT_I,
|
| 31 |
|
|
output reg ACK_O,
|
| 32 |
|
|
|
| 33 |
|
|
input CYC_I,
|
| 34 |
|
|
input STB_I,
|
| 35 |
|
|
input WE_I,
|
| 36 |
|
|
|
| 37 |
|
|
//serial output
|
| 38 |
|
|
input uart_rxd,
|
| 39 |
|
|
input uart_rts,
|
| 40 |
|
|
output reg uart_txd,
|
| 41 |
|
|
output uart_cts
|
| 42 |
|
|
);
|
| 43 |
|
|
|
| 44 |
|
|
assign uart_cts = uart_rts;
|
| 45 |
|
|
|
| 46 |
|
|
reg [12:0] counter;
|
| 47 |
|
|
|
| 48 |
|
|
always @(posedge CLK_I) begin
|
| 49 |
|
|
if(RST_I == 1'b1) begin
|
| 50 |
|
|
ACK_O <= 1'b0;
|
| 51 |
|
|
uart_txd <= 1'b1;
|
| 52 |
|
|
counter <= 13'd0;
|
| 53 |
|
|
end
|
| 54 |
|
|
|
| 55 |
|
|
else if(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 && ACK_O == 1'b0) begin
|
| 56 |
|
|
if(counter < 13'd8191) counter <= counter + 13'd1;
|
| 57 |
|
|
|
| 58 |
|
|
if(counter < 434*1) uart_txd <= 1'b0;
|
| 59 |
|
|
else if(counter < 434*2) uart_txd <= DAT_I[0];
|
| 60 |
|
|
else if(counter < 434*3) uart_txd <= DAT_I[1];
|
| 61 |
|
|
else if(counter < 434*4) uart_txd <= DAT_I[2];
|
| 62 |
|
|
else if(counter < 434*5) uart_txd <= DAT_I[3];
|
| 63 |
|
|
else if(counter < 434*6) uart_txd <= DAT_I[4];
|
| 64 |
|
|
else if(counter < 434*7) uart_txd <= DAT_I[5];
|
| 65 |
|
|
else if(counter < 434*8) uart_txd <= DAT_I[6];
|
| 66 |
|
|
else if(counter < 434*9) uart_txd <= DAT_I[7];
|
| 67 |
|
|
else if(counter < 434*10) uart_txd <= 1'b1;
|
| 68 |
|
|
else begin
|
| 69 |
|
|
uart_txd <= 1'b1;
|
| 70 |
|
|
ACK_O <= 1'b1;
|
| 71 |
|
|
end
|
| 72 |
|
|
end
|
| 73 |
|
|
else begin
|
| 74 |
|
|
ACK_O <= 1'b0;
|
| 75 |
|
|
uart_txd <= 1'b1;
|
| 76 |
|
|
counter <= 13'd0;
|
| 77 |
|
|
end
|
| 78 |
|
|
end
|
| 79 |
|
|
|
| 80 |
|
|
endmodule
|
| 81 |
|
|
|
