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<a href="#Inputs">Inputs</a> &#124;
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<a href="#Outputs">Outputs</a> &#124;
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<a href="#Signals">Signals</a> &#124;
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<a href="#Module Instances">Module Instances</a> &#124;
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<a href="#Always Constructs">Always Constructs</a>  </div>
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<h1>memory_registers Module Reference</h1>  </div>
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<!-- doxytag: class="memory_registers" -->
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<p>Contains the microcode ROM and D0-D7, A0-A7 registers.
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<a href="#_details">More...</a></p>
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Inheritance diagram for memory_registers:<!-- endSectionHeader --></div>
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<table class="memberdecls">
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<tr><td colspan="2"><h2><a name="Always Constructs"></a>
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Always Constructs</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a09281e3224878c570c81844785844fe0">ALWAYS_29</a>&#160;</td><td class="memItemRight" valign="bottom"><b> ( <b><b><a class="el" href="classmemory__registers.html#a30d6f9a116a35132d3ae1ac844480c7f">clock</a></b> <span class="vhdlchar"> </span></b> , <b><b><a class="el" href="classmemory__registers.html#a0070367d69af978092b5cd0b60dec77b">reset_n</a></b> <span class="vhdlchar"> </span></b> )</b></td></tr>
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<tr><td colspan="2"><h2><a name="Inputs"></a>
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Inputs</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a30d6f9a116a35132d3ae1ac844480c7f">clock</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a0070367d69af978092b5cd0b60dec77b">reset_n</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#af3fdc1a826e2d4992fc50550160eed52">An_address</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a05d2b0cd0706cfcb62674e59ed049b22">An_input</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#abfa12b67b2dfb6da21584304919f0a15">An_write_enable</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a55db549a365e2da7b32c589888f22c1f">Dn_address</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a70e26deed20065da35879d3ce4a7f06e">Dn_input</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a515d2e4fc82f04802e46d5eae5d0f0f5">Dn_write_enable</a> &#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a7e475d550020f2ef86841dd171ddf94e">Dn_size</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">1</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a242c22630fbc44df8a129350db77b3d0">micro_pc</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><h2><a name="Outputs"></a>
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Outputs</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#afe969a18dcdd487deeedc9f9146ef8c9">An_output</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a3380b9a07ee51a05b97308d5a7257972">usp</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a224aca31f9e8189294f9072ee0fc015a">Dn_output</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><a class="el" href="classmemory__registers.html#a9f8c0a5b5adedad8f2f3f503cb5510f6">micro_data</a> &#160;</td><td class="memItemRight" valign="bottom"><b><span class="vhdlchar">[</span><span class="vhdldigit">87</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b>  </td></tr>
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<tr><td colspan="2"><h2><a name="Module Instances"></a>
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Module Instances</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram::an_ram_inst</a>  </b>&#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">altsyncram::dn_ram_inst</a>  </b>&#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram::micro_rom_inst</a>  </b>&#160;</td><td class="memItemRight" valign="bottom"></td></tr>
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<tr><td colspan="2"><h2><a name="Signals"></a>
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Signals</h2></td></tr>
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 <tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#acfe7cd131da7ea586dcb50bea9457678">An_ram_write_enable</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#a162864c7253e9c74e47b2822eacde9d4">An_ram_output</a> </td></tr>
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<tr><td class="memItemLeft" align="right" valign="top"><b><span class="vhdlkeyword">wire</span><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="classmemory__registers.html#a3ab032d1bc007200d49892a2ab390732">dn_byteena</a> </td></tr>
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</table>
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<hr/><a name="_details"></a><h2>Detailed Description</h2>
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<p>Contains the microcode ROM and D0-D7, A0-A7 registers. </p>
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<p>The <a class="el" href="classmemory__registers.html" title="Contains the microcode ROM and D0-D7, A0-A7 registers.">memory_registers</a> module contains:</p>
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<ul>
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<li>data and address registers (D0-D7, A0-A7) implemented as an on-chip RAM.</li>
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<li>the microcode implemented as an on-chip ROM.</li>
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</ul>
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<p>Currently this module contains <em>altsyncram</em> instantiations from Altera Megafunction/LPM library. </p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02043">2043</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/><h2>Member Function Documentation</h2>
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<a class="anchor" id="a09281e3224878c570c81844785844fe0"></a><!-- doxytag: member="memory_registers::ALWAYS_29" ref="a09281e3224878c570c81844785844fe0" args="clock, reset_n" -->
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          <td class="memname"><b><span class="vhdlchar"> </span></b>ALWAYS_29          <td></td>
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          <td class="paramtype">(<span class="keywordtype"></span> <b><b><a class="el" href="classmemory__registers.html#a30d6f9a116a35132d3ae1ac844480c7f">clock</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> , </td>
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          <td class="paramtype"><span class="keywordtype"></span> <b><b><a class="el" href="classmemory__registers.html#a0070367d69af978092b5cd0b60dec77b">reset_n</a></b> <span class="vhdlchar"> </span></b>  <em><span class="vhdlkeyword"></span></em> ) </td>
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<code> [Always Construct]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02076">2076</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/><h2>Member Data Documentation</h2>
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<a class="anchor" id="a30d6f9a116a35132d3ae1ac844480c7f"></a><!-- doxytag: member="memory_registers::clock" ref="a30d6f9a116a35132d3ae1ac844480c7f" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a30d6f9a116a35132d3ae1ac844480c7f">clock</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02044">2044</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a0070367d69af978092b5cd0b60dec77b">reset_n</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#af3fdc1a826e2d4992fc50550160eed52">An_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">3</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02048">2048</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02049">2049</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02050">2050</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="afe969a18dcdd487deeedc9f9146ef8c9"></a><!-- doxytag: member="memory_registers::An_output" ref="afe969a18dcdd487deeedc9f9146ef8c9" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#afe969a18dcdd487deeedc9f9146ef8c9">An_output</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02051">2051</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a3380b9a07ee51a05b97308d5a7257972">usp</a></span> <b><span class="vhdlkeyword">reg</span><span class="vhdlchar">[</span><span class="vhdldigit">31</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Output]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02053">2053</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a55db549a365e2da7b32c589888f22c1f">Dn_address</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">2</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02055">2055</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02056">2056</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a515d2e4fc82f04802e46d5eae5d0f0f5">Dn_write_enable</a></span> <b><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02057">2057</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02059">2059</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02060">2060</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a242c22630fbc44df8a129350db77b3d0">micro_pc</a></span> <b><span class="vhdlchar">[</span><span class="vhdldigit">8</span><span class="vhdlchar">:</span><span class="vhdldigit">0</span><span class="vhdlchar">]</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Input]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02062">2062</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02063">2063</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02066">2066</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a162864c7253e9c74e47b2822eacde9d4"></a><!-- doxytag: member="memory_registers::An_ram_output" ref="a162864c7253e9c74e47b2822eacde9d4" args="wire[31:0]" -->
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02068">2068</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a3ab032d1bc007200d49892a2ab390732"></a><!-- doxytag: member="memory_registers::dn_byteena" ref="a3ab032d1bc007200d49892a2ab390732" args="wire[3:0]" -->
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02071">2071</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<a class="anchor" id="a892186b1bfe856b1ddaf1d8b3a448f50"></a><!-- doxytag: member="memory_registers::altsyncram" ref="a892186b1bfe856b1ddaf1d8b3a448f50" args="" -->
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a892186b1bfe856b1ddaf1d8b3a448f50">altsyncram</a></span> <b><span class="vhdlchar">an_ram_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02082">2082</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#a5b0f1fb5a259a06899ac6ac3b52835e0">altsyncram</a></span> <b><span class="vhdlchar">dn_ram_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02098">2098</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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          <td class="memname"><span class="stringliteral"><a class="el" href="classmemory__registers.html#afc54073a43b749eb1f1376c4b31cd1e3">altsyncram</a></span> <b><span class="vhdlchar">micro_rom_inst</span><span class="vhdlchar"> </span></b> <b><span class="vhdlchar"> </span></b> <code> [Module Instance]</code></td>
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<p>Definition at line <a class="el" href="ao68000_8v_source.html#l02114">2114</a> of file <a class="el" href="ao68000_8v_source.html">ao68000.v</a>.</p>
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<hr/>The documentation for this class was generated from the following file:<ul>
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<li><a class="el" href="ao68000_8v_source.html">ao68000.v</a></li>
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</ul>
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<hr class="footer"/><address class="footer"><small>Generated on Mon Dec 20 2010 21:20:20 for aoOCS by&#160;
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
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