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<h1>vga_eth_capture.v</h1>  </div>
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<div class="contents">
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<a href="vga__eth__capture_8v.html">Go to the documentation of this file.</a><div class="fragment"><pre class="fragment"><a name="l00001"></a>00001  <span class="keyword">/*</span>
32
<a name="l00002"></a>00002 <span class="keyword">Send UDP packet:</span>
33
<a name="l00003"></a>00003 <span class="keyword">ethernet</span>
34
<a name="l00004"></a>00004 <span class="keyword">    dest mac(6), src mac(6), type(2 = 0x0800 IPv4)</span>
35
<a name="l00005"></a>00005 <span class="keyword">ip</span>
36
<a name="l00006"></a>00006 <span class="keyword">    version,header([1] = 0x45), tos([1] = 0x00), length([2] = 4*5 + 4*2 + len = 990 = 0x03DE)</span>
37
<a name="l00007"></a>00007 <span class="keyword">    id([2] = 0x0000), flags,offset([2] = 0x40, 0x00)</span>
38
<a name="l00008"></a>00008 <span class="keyword">    ttl([1] = 0x0F), protocol([1] = 0x11), header checksum([2] = 0)</span>
39
<a name="l00009"></a>00009 <span class="keyword">    source ip([4])</span>
40
<a name="l00010"></a>00010 <span class="keyword">    dest ip([4])</span>
41
<a name="l00011"></a>00011 <span class="keyword">udp</span>
42
<a name="l00012"></a>00012 <span class="keyword">    source port([2]), dest port([2])</span>
43
<a name="l00013"></a>00013 <span class="keyword">    length([2] = 8 + len = 970 = 0x03CA), checksum([2] = 0)</span>
44
<a name="l00014"></a>00014 <span class="keyword">data</span>
45
<a name="l00015"></a>00015 <span class="keyword">    (len = line num(2) + line(640*12/8 = 960) = 962)</span>
46
<a name="l00016"></a>00016 <span class="keyword"></span>
47
<a name="l00017"></a>00017 <span class="keyword">--full ethernet packet len = 990 + 14 = 1004 = 0x03EC</span>
48
<a name="l00018"></a>00018 <span class="keyword"></span>
49
<a name="l00019"></a>00019 <span class="keyword">DM9000A control to send:</span>
50
<a name="l00020"></a>00020 <span class="keyword">    set IMR(FFh = 0x80)</span>
51
<a name="l00021"></a>00021 <span class="keyword">    </span>
52
<a name="l00022"></a>00022 <span class="keyword">    set checksum reg (31h = 0x05)</span>
53
<a name="l00023"></a>00023 <span class="keyword">    </span>
54
<a name="l00024"></a>00024 <span class="keyword">    set early transmit (30h = 0x83) ? threshold 75%</span>
55
<a name="l00025"></a>00025 <span class="keyword">    </span>
56
<a name="l00026"></a>00026 <span class="keyword">    power-up PHY (1Fh = 0x00)</span>
57
<a name="l00027"></a>00027 <span class="keyword">    </span>
58
<a name="l00028"></a>00028 <span class="keyword">    dummy MWCDM ?</span>
59
<a name="l00029"></a>00029 <span class="keyword">    </span>
60
<a name="l00030"></a>00030 <span class="keyword">    DO</span>
61
<a name="l00031"></a>00031 <span class="keyword">    </span>
62
<a name="l00032"></a>00032 <span class="keyword">        packet I</span>
63
<a name="l00033"></a>00033 <span class="keyword">        set MWCMD(F8h = 16-bit data) </span>
64
<a name="l00034"></a>00034 <span class="keyword">        </span>
65
<a name="l00035"></a>00035 <span class="keyword">        wait for packet II</span>
66
<a name="l00036"></a>00036 <span class="keyword">        read TX(02h bit 0 == 0)</span>
67
<a name="l00037"></a>00037 <span class="keyword">        </span>
68
<a name="l00038"></a>00038 <span class="keyword">        set TXPLL(FCh = low byte)</span>
69
<a name="l00039"></a>00039 <span class="keyword">        set TXPLH(FDh = high byte)</span>
70
<a name="l00040"></a>00040 <span class="keyword">        </span>
71
<a name="l00041"></a>00041 <span class="keyword">        write TX(02h 0x01)</span>
72
<a name="l00042"></a>00042 <span class="keyword">        </span>
73
<a name="l00043"></a>00043 <span class="keyword">        packet II</span>
74
<a name="l00044"></a>00044 <span class="keyword">        set MWCMD(F8h = 16-bit data) </span>
75
<a name="l00045"></a>00045 <span class="keyword">        </span>
76
<a name="l00046"></a>00046 <span class="keyword">        wait for packet I</span>
77
<a name="l00047"></a>00047 <span class="keyword">        read TX(02h bit 0 == 0)</span>
78
<a name="l00048"></a>00048 <span class="keyword">        </span>
79
<a name="l00049"></a>00049 <span class="keyword">        set TXPLL(FCh = low byte)</span>
80
<a name="l00050"></a>00050 <span class="keyword">        set TXPLH(FDh = high byte)</span>
81
<a name="l00051"></a>00051 <span class="keyword">        </span>
82
<a name="l00052"></a>00052 <span class="keyword">        write TX(02h 0x01)</span>
83
<a name="l00053"></a>00053 <span class="keyword">    </span>
84
<a name="l00054"></a>00054 <span class="keyword">    LOOP</span>
85
<a name="l00055"></a>00055 <span class="keyword">    </span>
86
<a name="l00056"></a>00056 <span class="keyword">*/</span>
87
<a name="l00057"></a>00057
88
<a name="l00058"></a><a class="code" href="classvga__capture.html">00058</a> <span class="vhdlkeyword">module</span> <a class="code" href="classvga__capture.html">vga_capture</a>(
89
<a name="l00059"></a><a class="code" href="classvga__capture.html#a07e2196b812ab052f8f340e6037c8a0d">00059</a>     <span class="vhdlkeyword">input</span> <a class="code" href="classvga__capture.html#a07e2196b812ab052f8f340e6037c8a0d">clk_30</a>,
90
<a name="l00060"></a><a class="code" href="classvga__capture.html#a780377927ae758cb7b049d3965f384da">00060</a>     <span class="vhdlkeyword">input</span> <a class="code" href="classvga__capture.html#a780377927ae758cb7b049d3965f384da">clk_25</a>,
91
<a name="l00061"></a><a class="code" href="classvga__capture.html#a2ac949110c87f316dae9a7f6f92124e1">00061</a>     <span class="vhdlkeyword">input</span> <a class="code" href="classvga__capture.html#a2ac949110c87f316dae9a7f6f92124e1">reset_n</a>,
92
<a name="l00062"></a>00062
93
<a name="l00063"></a>00063     <span class="keyword">// vga read burst</span>
94
<a name="l00064"></a><a class="code" href="classvga__capture.html#a82931d3c79277785124b41359211a1a7">00064</a>     <span class="vhdlkeyword">input</span> [<span class="vhdllogic">9</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#a82931d3c79277785124b41359211a1a7">vga_r</a>,
95
<a name="l00065"></a><a class="code" href="classvga__capture.html#a545541c9a7091b81dedb286674b278d3">00065</a>     <span class="vhdlkeyword">input</span> [<span class="vhdllogic">9</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#a545541c9a7091b81dedb286674b278d3">vga_g</a>,
96
<a name="l00066"></a><a class="code" href="classvga__capture.html#afc0c214510eef283465543353a7c5d8a">00066</a>     <span class="vhdlkeyword">input</span> [<span class="vhdllogic">9</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#afc0c214510eef283465543353a7c5d8a">vga_b</a>,
97
<a name="l00067"></a><a class="code" href="classvga__capture.html#add39a9ff1b902cca9334d1d8dd6d5d6b">00067</a>     <span class="vhdlkeyword">input</span> <a class="code" href="classvga__capture.html#add39a9ff1b902cca9334d1d8dd6d5d6b">display_valid</a>,
98
<a name="l00068"></a>00068
99
<a name="l00069"></a>00069     <span class="keyword">// DM9000A ethernet</span>
100
<a name="l00070"></a><a class="code" href="classvga__capture.html#a9fe89eca5989b273b280cef581de0c3f">00070</a>     <span class="vhdlkeyword">output</span> <a class="code" href="classvga__capture.html#a9fe89eca5989b273b280cef581de0c3f">enet_clk_25</a>,
101
<a name="l00071"></a><a class="code" href="classvga__capture.html#a9a14ae3a9434a532621625bab3b0b9a1">00071</a>     <span class="vhdlkeyword">output</span> <a class="code" href="classvga__capture.html#a9a14ae3a9434a532621625bab3b0b9a1">enet_reset_n</a>,
102
<a name="l00072"></a><a class="code" href="classvga__capture.html#a4ce7dfcd51f6fafa6f68c4451f701d0c">00072</a>     <span class="vhdlkeyword">output</span> <a class="code" href="classvga__capture.html#a4ce7dfcd51f6fafa6f68c4451f701d0c">enet_cs_n</a>,
103
<a name="l00073"></a><a class="code" href="classvga__capture.html#a8827ab14734cae8463730d5dc460454f">00073</a>     <span class="vhdlkeyword">input</span> <a class="code" href="classvga__capture.html#a8827ab14734cae8463730d5dc460454f">enet_irq</a>,
104
<a name="l00074"></a>00074
105
<a name="l00075"></a><a class="code" href="classvga__capture.html#afdb7af2d1042c612676529bdcd68a05c">00075</a>     <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classvga__capture.html#afdb7af2d1042c612676529bdcd68a05c">enet_ior_n</a>,
106
<a name="l00076"></a><a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">00076</a>     <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a>,
107
<a name="l00077"></a><a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">00077</a>     <span class="vhdlkeyword">output</span> <span class="vhdlkeyword">reg</span> <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a>,
108
<a name="l00078"></a><a class="code" href="classvga__capture.html#a415a70b3d7198d3282610022751de6d8">00078</a>     <span class="vhdlkeyword">inout</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#a415a70b3d7198d3282610022751de6d8">enet_data</a>
109
<a name="l00079"></a>00079 );
110
<a name="l00080"></a>00080 <span class="vhdlkeyword">assign</span> <a class="code" href="classvga__capture.html#a9fe89eca5989b273b280cef581de0c3f">enet_clk_25</a>  = <a class="code" href="classvga__capture.html#a780377927ae758cb7b049d3965f384da">clk_25</a>;
111
<a name="l00081"></a>00081 <span class="vhdlkeyword">assign</span> <a class="code" href="classvga__capture.html#a9a14ae3a9434a532621625bab3b0b9a1">enet_reset_n</a> = <a class="code" href="classvga__capture.html#a2ac949110c87f316dae9a7f6f92124e1">reset_n</a>;
112
<a name="l00082"></a>00082 <span class="vhdlkeyword">assign</span> <a class="code" href="classvga__capture.html#a4ce7dfcd51f6fafa6f68c4451f701d0c">enet_cs_n</a>    = <span class="vhdllogic">1&#39;b0</span>;
113
<a name="l00083"></a>00083
114
<a name="l00084"></a><a class="code" href="classvga__capture.html#a9b7fb3d3f6c622692e3d5b65e050753a">00084</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classvga__capture.html#a9b7fb3d3f6c622692e3d5b65e050753a">tx_active</a>;
115
<a name="l00085"></a>00085
116
<a name="l00086"></a><a class="code" href="classvga__capture.html#a5803d9b80a06d8486e2af6b362cc6177">00086</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classvga__capture.html#a5803d9b80a06d8486e2af6b362cc6177">enet_data_oe</a>;
117
<a name="l00087"></a><a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">00087</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a>;
118
<a name="l00088"></a>00088 <span class="vhdlkeyword">assign</span> <a class="code" href="classvga__capture.html#a415a70b3d7198d3282610022751de6d8">enet_data</a> = (<a class="code" href="classvga__capture.html#a5803d9b80a06d8486e2af6b362cc6177">enet_data_oe</a> == <span class="vhdllogic">1&#39;b1</span>)? <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> : <span class="vhdllogic">16&#39;bZ</span>;
119
<a name="l00089"></a>00089
120
<a name="l00090"></a>00090 <span class="keyword">//************ packet Ethernet and IP/UDP header contents ROM</span>
121
<a name="l00091"></a><a class="code" href="classvga__capture.html#aae9a3f0658faf4cab77fd197c1a30ba2">00091</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">5</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#aae9a3f0658faf4cab77fd197c1a30ba2">ram_addr</a>;
122
<a name="l00092"></a><a class="code" href="classvga__capture.html#a6ca923ab0b43c63a36795c06a7ed7cbb">00092</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#a6ca923ab0b43c63a36795c06a7ed7cbb">ram_q</a>;
123
<a name="l00093"></a>00093
124
<a name="l00094"></a><a class="code" href="classvga__capture.html#a3305dae46003d5c68ca0e917b94aaf4c">00094</a> <a class="code" href="classvga__capture.html#a3305dae46003d5c68ca0e917b94aaf4c">altsyncram</a> <span class="vhdlchar">ethernet_ram_inst</span>(
125
<a name="l00095"></a>00095     .<span class="vhdlchar">clock0</span>(<a class="code" href="classvga__capture.html#a07e2196b812ab052f8f340e6037c8a0d">clk_30</a>),
126
<a name="l00096"></a>00096     .<span class="vhdlchar">address_a</span>(<a class="code" href="classvga__capture.html#aae9a3f0658faf4cab77fd197c1a30ba2">ram_addr</a>),
127
<a name="l00097"></a>00097     .<span class="vhdlchar">q_a</span>(<a class="code" href="classvga__capture.html#a6ca923ab0b43c63a36795c06a7ed7cbb">ram_q</a>)
128
<a name="l00098"></a>00098 );
129
<a name="l00099"></a>00099 <span class="vhdlkeyword">defparam</span>
130
<a name="l00100"></a>00100     <span class="vhdlchar">ethernet_ram_inst</span>.<span class="vhdlchar">operation_mode</span> = <span class="keyword">&quot;ROM&quot;</span>,
131
<a name="l00101"></a>00101     <span class="vhdlchar">ethernet_ram_inst</span>.<span class="vhdlchar">width_a</span> = <span class="vhdllogic">16</span>,
132
<a name="l00102"></a>00102     <span class="vhdlchar">ethernet_ram_inst</span>.<span class="vhdlchar">widthad_a</span> = <span class="vhdllogic">6</span>,
133
<a name="l00103"></a>00103     <span class="vhdlchar">ethernet_ram_inst</span>.<span class="vhdlchar">init_file</span> = <span class="keyword">&quot;vga_eth_capture.mif&quot;</span>;
134
<a name="l00104"></a>00104
135
<a name="l00105"></a>00105 <span class="keyword">//************ vga burst fifo</span>
136
<a name="l00106"></a><a class="code" href="classvga__capture.html#a2e2d5d858bb65882da803f77dc3ad9f9">00106</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">8</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#a2e2d5d858bb65882da803f77dc3ad9f9">vga_line_number</a>;
137
<a name="l00107"></a><a class="code" href="classvga__capture.html#aa0ae37b440563a3cba5857c19c0fc321">00107</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classvga__capture.html#aa0ae37b440563a3cba5857c19c0fc321">last_display_valid</a>;
138
<a name="l00108"></a><a class="code" href="classvga__capture.html#ad88aa1faaf9b0297ceb79675416672f3">00108</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#ad88aa1faaf9b0297ceb79675416672f3">select_line</a>;
139
<a name="l00109"></a><a class="code" href="classvga__capture.html#a1fa79ccb8d20e6a1d404dc7033536572">00109</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classvga__capture.html#a1fa79ccb8d20e6a1d404dc7033536572">block_wrreq</a>;
140
<a name="l00110"></a><a class="code" href="classvga__capture.html#a0cd5229f9236bafdc60cd75f2836d688">00110</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classvga__capture.html#a07e2196b812ab052f8f340e6037c8a0d">clk_30</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classvga__capture.html#a2ac949110c87f316dae9a7f6f92124e1">reset_n</a>) <span class="vhdlkeyword">begin</span>
141
<a name="l00111"></a>00111     <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#a2ac949110c87f316dae9a7f6f92124e1">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>) <span class="vhdlkeyword">begin</span>
142
<a name="l00112"></a>00112         <a class="code" href="classvga__capture.html#a2e2d5d858bb65882da803f77dc3ad9f9">vga_line_number</a> &lt;= <span class="vhdllogic">9&#39;d0</span>;
143
<a name="l00113"></a>00113         <a class="code" href="classvga__capture.html#aa0ae37b440563a3cba5857c19c0fc321">last_display_valid</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
144
<a name="l00114"></a>00114         <a class="code" href="classvga__capture.html#ad88aa1faaf9b0297ceb79675416672f3">select_line</a> &lt;= <span class="vhdllogic">2&#39;d0</span>;
145
<a name="l00115"></a>00115         <a class="code" href="classvga__capture.html#a1fa79ccb8d20e6a1d404dc7033536572">block_wrreq</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
146
<a name="l00116"></a>00116     <span class="vhdlkeyword">end</span>
147
<a name="l00117"></a>00117     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">begin</span>
148
<a name="l00118"></a>00118         <a class="code" href="classvga__capture.html#aa0ae37b440563a3cba5857c19c0fc321">last_display_valid</a> &lt;= <a class="code" href="classvga__capture.html#add39a9ff1b902cca9334d1d8dd6d5d6b">display_valid</a>;
149
<a name="l00119"></a>00119
150
<a name="l00120"></a>00120         <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#aad57b6fecebd4e7aec75f433507b55cd">fifo_empty</a> == <span class="vhdllogic">1&#39;b0</span> &amp;&amp; <a class="code" href="classvga__capture.html#aa0ae37b440563a3cba5857c19c0fc321">last_display_valid</a> == <span class="vhdllogic">1&#39;b0</span> &amp;&amp; <a class="code" href="classvga__capture.html#add39a9ff1b902cca9334d1d8dd6d5d6b">display_valid</a> == <span class="vhdllogic">1&#39;b1</span>)   <a class="code" href="classvga__capture.html#a1fa79ccb8d20e6a1d404dc7033536572">block_wrreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
151
<a name="l00121"></a>00121         <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#add39a9ff1b902cca9334d1d8dd6d5d6b">display_valid</a> == <span class="vhdllogic">1&#39;b0</span>)                                                  <a class="code" href="classvga__capture.html#a1fa79ccb8d20e6a1d404dc7033536572">block_wrreq</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
152
<a name="l00122"></a>00122
153
<a name="l00123"></a>00123         <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#add39a9ff1b902cca9334d1d8dd6d5d6b">display_valid</a> == <span class="vhdllogic">1&#39;b0</span> &amp;&amp; <a class="code" href="classvga__capture.html#aa0ae37b440563a3cba5857c19c0fc321">last_display_valid</a> == <span class="vhdllogic">1&#39;b1</span>) <span class="vhdlkeyword">begin</span>
154
<a name="l00124"></a>00124             <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#a2e2d5d858bb65882da803f77dc3ad9f9">vga_line_number</a> == <span class="vhdllogic">9&#39;d479</span>)   <a class="code" href="classvga__capture.html#a2e2d5d858bb65882da803f77dc3ad9f9">vga_line_number</a> &lt;= <span class="vhdllogic">9&#39;d0</span>;
155
<a name="l00125"></a>00125             <span class="vhdlkeyword">else</span>                            <a class="code" href="classvga__capture.html#a2e2d5d858bb65882da803f77dc3ad9f9">vga_line_number</a> &lt;= <a class="code" href="classvga__capture.html#a2e2d5d858bb65882da803f77dc3ad9f9">vga_line_number</a> + <span class="vhdllogic">9&#39;d1</span>;
156
<a name="l00126"></a>00126         <span class="vhdlkeyword">end</span>
157
<a name="l00127"></a>00127
158
<a name="l00128"></a>00128         <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#add39a9ff1b902cca9334d1d8dd6d5d6b">display_valid</a> == <span class="vhdllogic">1&#39;b0</span> &amp;&amp; <a class="code" href="classvga__capture.html#aa0ae37b440563a3cba5857c19c0fc321">last_display_valid</a> == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <a class="code" href="classvga__capture.html#a2e2d5d858bb65882da803f77dc3ad9f9">vga_line_number</a> == <span class="vhdllogic">9&#39;d479</span>) <a class="code" href="classvga__capture.html#ad88aa1faaf9b0297ceb79675416672f3">select_line</a> &lt;= <a class="code" href="classvga__capture.html#ad88aa1faaf9b0297ceb79675416672f3">select_line</a> + <span class="vhdllogic">2&#39;d1</span>;
159
<a name="l00129"></a>00129     <span class="vhdlkeyword">end</span>
160
<a name="l00130"></a>00130 <span class="vhdlkeyword">end</span>
161
<a name="l00131"></a>00131
162
<a name="l00132"></a><a class="code" href="classvga__capture.html#a88684f24ada2cd371386e6f600aa08d8">00132</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classvga__capture.html#a88684f24ada2cd371386e6f600aa08d8">fifo_wrreq</a> = (<a class="code" href="classvga__capture.html#aad57b6fecebd4e7aec75f433507b55cd">fifo_empty</a> == <span class="vhdllogic">1&#39;b1</span> || <a class="code" href="classvga__capture.html#aa0ae37b440563a3cba5857c19c0fc321">last_display_valid</a> == <span class="vhdllogic">1&#39;b1</span>) &amp;&amp; <a class="code" href="classvga__capture.html#a1fa79ccb8d20e6a1d404dc7033536572">block_wrreq</a> == <span class="vhdllogic">1&#39;b0</span> &amp;&amp; <a class="code" href="classvga__capture.html#add39a9ff1b902cca9334d1d8dd6d5d6b">display_valid</a> == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <a class="code" href="classvga__capture.html#ad88aa1faaf9b0297ceb79675416672f3">select_line</a> == <a class="code" href="classvga__capture.html#a2e2d5d858bb65882da803f77dc3ad9f9">vga_line_number</a>[<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>];
163
<a name="l00133"></a><a class="code" href="classvga__capture.html#a7923eccb18a807d0dd25fc649fc315f3">00133</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classvga__capture.html#a7923eccb18a807d0dd25fc649fc315f3">start_load</a> = <a class="code" href="classvga__capture.html#aad57b6fecebd4e7aec75f433507b55cd">fifo_empty</a> == <span class="vhdllogic">1&#39;b0</span>;
164
<a name="l00134"></a>00134
165
<a name="l00135"></a><a class="code" href="classvga__capture.html#aad57b6fecebd4e7aec75f433507b55cd">00135</a> <span class="vhdlkeyword">wire</span> <a class="code" href="classvga__capture.html#aad57b6fecebd4e7aec75f433507b55cd">fifo_empty</a>;
166
<a name="l00136"></a><a class="code" href="classvga__capture.html#af60734bc0dd9ee6c76a6ad073a2922c0">00136</a> <span class="vhdlkeyword">wire</span> [<span class="vhdllogic">11</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#af60734bc0dd9ee6c76a6ad073a2922c0">fifo_q</a>;
167
<a name="l00137"></a>00137
168
<a name="l00138"></a><a class="code" href="classvga__capture.html#a59768c08add982f9d20148482217c411">00138</a> <a class="code" href="classvga__capture.html#a59768c08add982f9d20148482217c411">scfifo</a> <span class="vhdlchar">vga_fifo_inst</span>(
169
<a name="l00139"></a>00139     .<span class="vhdlchar">clock</span>(<a class="code" href="classvga__capture.html#a07e2196b812ab052f8f340e6037c8a0d">clk_30</a>),
170
<a name="l00140"></a>00140     .<span class="vhdlchar">data</span>( { <a class="code" href="classvga__capture.html#a82931d3c79277785124b41359211a1a7">vga_r</a>[<span class="vhdllogic">9</span>:<span class="vhdllogic">6</span>], <a class="code" href="classvga__capture.html#a545541c9a7091b81dedb286674b278d3">vga_g</a>[<span class="vhdllogic">9</span>:<span class="vhdllogic">6</span>], <a class="code" href="classvga__capture.html#afc0c214510eef283465543353a7c5d8a">vga_b</a>[<span class="vhdllogic">9</span>:<span class="vhdllogic">6</span>] } ),
171
<a name="l00141"></a>00141     .<span class="vhdlchar">wrreq</span>(<a class="code" href="classvga__capture.html#a88684f24ada2cd371386e6f600aa08d8">fifo_wrreq</a>),
172
<a name="l00142"></a>00142     .<span class="vhdlchar">rdreq</span>(<a class="code" href="classvga__capture.html#a175510c6d10d0a359dc13b81334bb11f">fifo_rdreq</a>),
173
<a name="l00143"></a>00143
174
<a name="l00144"></a>00144     .<span class="vhdlchar">empty</span>(<a class="code" href="classvga__capture.html#aad57b6fecebd4e7aec75f433507b55cd">fifo_empty</a>),
175
<a name="l00145"></a>00145     .<span class="vhdlchar">q</span>(<a class="code" href="classvga__capture.html#af60734bc0dd9ee6c76a6ad073a2922c0">fifo_q</a>)
176
<a name="l00146"></a>00146 );
177
<a name="l00147"></a>00147 <span class="vhdlkeyword">defparam</span>
178
<a name="l00148"></a>00148     <span class="vhdlchar">vga_fifo_inst</span>.<span class="vhdlchar">lpm_width</span> = <span class="vhdllogic">12</span>,
179
<a name="l00149"></a>00149     <span class="vhdlchar">vga_fifo_inst</span>.<span class="vhdlchar">lpm_numwords</span> = <span class="vhdllogic">1024</span>;
180
<a name="l00150"></a>00150
181
<a name="l00151"></a><a class="code" href="classvga__capture.html#a175510c6d10d0a359dc13b81334bb11f">00151</a> <span class="vhdlkeyword">reg</span> <a class="code" href="classvga__capture.html#a175510c6d10d0a359dc13b81334bb11f">fifo_rdreq</a>;
182
<a name="l00152"></a><a class="code" href="classvga__capture.html#ace8b499e7026ba90ce684a7b596409a3">00152</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">1</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#ace8b499e7026ba90ce684a7b596409a3">fifo_rd_cnt</a>;
183
<a name="l00153"></a><a class="code" href="classvga__capture.html#a8094baf5a487d00c87e5abaf86e3ebb6">00153</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">11</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#a8094baf5a487d00c87e5abaf86e3ebb6">last_fifo_q</a>;
184
<a name="l00154"></a>00154
185
<a name="l00155"></a>00155 <span class="keyword">//************</span>
186
<a name="l00156"></a>00156
187
<a name="l00157"></a><a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">00157</a> <span class="vhdlkeyword">reg</span> [<span class="vhdllogic">15</span>:<span class="vhdllogic">0</span>] <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a>;
188
<a name="l00158"></a><a class="code" href="classvga__capture.html#af0c7c40cb7c77b8c759687d6362a7e17">00158</a> <span class="vhdlkeyword">always</span> @(<span class="vhdlkeyword">posedge</span> <a class="code" href="classvga__capture.html#a07e2196b812ab052f8f340e6037c8a0d">clk_30</a> <span class="vhdlkeyword">or</span> <span class="vhdlkeyword">negedge</span> <a class="code" href="classvga__capture.html#a2ac949110c87f316dae9a7f6f92124e1">reset_n</a>) <span class="vhdlkeyword">begin</span>
189
<a name="l00159"></a>00159     <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#a2ac949110c87f316dae9a7f6f92124e1">reset_n</a> == <span class="vhdllogic">1&#39;b0</span>) <span class="vhdlkeyword">begin</span>
190
<a name="l00160"></a>00160         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a>   &lt;= <span class="vhdllogic">16&#39;d0</span>;
191
<a name="l00161"></a>00161         <a class="code" href="classvga__capture.html#a9b7fb3d3f6c622692e3d5b65e050753a">tx_active</a>       &lt;= <span class="vhdllogic">1&#39;b0</span>;
192
<a name="l00162"></a>00162
193
<a name="l00163"></a>00163         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a>      &lt;= <span class="vhdllogic">1&#39;b1</span>;
194
<a name="l00164"></a>00164         <a class="code" href="classvga__capture.html#afdb7af2d1042c612676529bdcd68a05c">enet_ior_n</a>      &lt;= <span class="vhdllogic">1&#39;b1</span>;
195
<a name="l00165"></a>00165         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a>        &lt;= <span class="vhdllogic">1&#39;b0</span>;        <span class="keyword">// low: INDEX, high: DATA</span>
196
<a name="l00166"></a>00166         <a class="code" href="classvga__capture.html#a5803d9b80a06d8486e2af6b362cc6177">enet_data_oe</a>    &lt;= <span class="vhdllogic">1&#39;b0</span>;
197
<a name="l00167"></a>00167         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a>   &lt;= <span class="vhdllogic">16&#39;d0</span>;
198
<a name="l00168"></a>00168
199
<a name="l00169"></a>00169         <a class="code" href="classvga__capture.html#aae9a3f0658faf4cab77fd197c1a30ba2">ram_addr</a>        &lt;= <span class="vhdllogic">6&#39;d0</span>;
200
<a name="l00170"></a>00170
201
<a name="l00171"></a>00171         <a class="code" href="classvga__capture.html#a175510c6d10d0a359dc13b81334bb11f">fifo_rdreq</a>      &lt;= <span class="vhdllogic">1&#39;b0</span>;
202
<a name="l00172"></a>00172         <a class="code" href="classvga__capture.html#ace8b499e7026ba90ce684a7b596409a3">fifo_rd_cnt</a>     &lt;= <span class="vhdllogic">2&#39;d0</span>;
203
<a name="l00173"></a>00173         <a class="code" href="classvga__capture.html#a8094baf5a487d00c87e5abaf86e3ebb6">last_fifo_q</a>     &lt;= <span class="vhdllogic">12&#39;d0</span>;
204
<a name="l00174"></a>00174     <span class="vhdlkeyword">end</span>
205
<a name="l00175"></a>00175     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d50000</span>) <span class="vhdlkeyword">begin</span>
206
<a name="l00176"></a>00176         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
207
<a name="l00177"></a>00177         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
208
<a name="l00178"></a>00178         <a class="code" href="classvga__capture.html#a5803d9b80a06d8486e2af6b362cc6177">enet_data_oe</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
209
<a name="l00179"></a>00179         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;hFF</span> }; <span class="keyword">// set IMR(FFh = 0x80)</span>
210
<a name="l00180"></a>00180
211
<a name="l00181"></a>00181         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
212
<a name="l00182"></a>00182     <span class="vhdlkeyword">end</span>
213
<a name="l00183"></a>00183     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d50002</span>) <span class="vhdlkeyword">begin</span>
214
<a name="l00184"></a>00184         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
215
<a name="l00185"></a>00185         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
216
<a name="l00186"></a>00186         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h80</span> };
217
<a name="l00187"></a>00187
218
<a name="l00188"></a>00188         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
219
<a name="l00189"></a>00189     <span class="vhdlkeyword">end</span>
220
<a name="l00190"></a>00190     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d50005</span>) <span class="vhdlkeyword">begin</span>
221
<a name="l00191"></a>00191         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
222
<a name="l00192"></a>00192         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
223
<a name="l00193"></a>00193         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h1F</span> }; <span class="keyword">// power-up PHY (1Fh = 0x00)</span>
224
<a name="l00194"></a>00194
225
<a name="l00195"></a>00195         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
226
<a name="l00196"></a>00196     <span class="vhdlkeyword">end</span>
227
<a name="l00197"></a>00197     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d50007</span>) <span class="vhdlkeyword">begin</span>
228
<a name="l00198"></a>00198         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
229
<a name="l00199"></a>00199         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
230
<a name="l00200"></a>00200         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h00</span> };
231
<a name="l00201"></a>00201
232
<a name="l00202"></a>00202         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
233
<a name="l00203"></a>00203     <span class="vhdlkeyword">end</span>
234
<a name="l00204"></a>00204
235
<a name="l00205"></a>00205     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d50010</span>) <span class="vhdlkeyword">begin</span>
236
<a name="l00206"></a>00206         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
237
<a name="l00207"></a>00207         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
238
<a name="l00208"></a>00208         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h31</span> }; <span class="keyword">// set checksum reg (31h = 0x05)</span>
239
<a name="l00209"></a>00209
240
<a name="l00210"></a>00210         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
241
<a name="l00211"></a>00211     <span class="vhdlkeyword">end</span>
242
<a name="l00212"></a>00212     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d50012</span>) <span class="vhdlkeyword">begin</span>
243
<a name="l00213"></a>00213         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
244
<a name="l00214"></a>00214         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
245
<a name="l00215"></a>00215         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h05</span> };
246
<a name="l00216"></a>00216
247
<a name="l00217"></a>00217         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
248
<a name="l00218"></a>00218     <span class="vhdlkeyword">end</span>
249
<a name="l00219"></a>00219
250
<a name="l00220"></a>00220
251
<a name="l00221"></a>00221     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d50018</span>) <span class="vhdlkeyword">begin</span>
252
<a name="l00222"></a>00222         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
253
<a name="l00223"></a>00223         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
254
<a name="l00224"></a>00224         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;hF8</span> }; <span class="keyword">// set MWCMD(F8h = 16-bit data) </span>
255
<a name="l00225"></a>00225
256
<a name="l00226"></a>00226         <a class="code" href="classvga__capture.html#aae9a3f0658faf4cab77fd197c1a30ba2">ram_addr</a> &lt;= <span class="vhdllogic">6&#39;d0</span>;
257
<a name="l00227"></a>00227         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
258
<a name="l00228"></a>00228     <span class="vhdlkeyword">end</span>
259
<a name="l00229"></a>00229     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &gt;= <span class="vhdllogic">16&#39;d50020</span> &amp;&amp; <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d50060</span> &amp;&amp; <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b0</span>) <span class="vhdlkeyword">begin</span>
260
<a name="l00230"></a>00230         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
261
<a name="l00231"></a>00231         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
262
<a name="l00232"></a>00232         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= <a class="code" href="classvga__capture.html#a6ca923ab0b43c63a36795c06a7ed7cbb">ram_q</a>;
263
<a name="l00233"></a>00233
264
<a name="l00234"></a>00234         <a class="code" href="classvga__capture.html#aae9a3f0658faf4cab77fd197c1a30ba2">ram_addr</a> &lt;= <a class="code" href="classvga__capture.html#aae9a3f0658faf4cab77fd197c1a30ba2">ram_addr</a> + <span class="vhdllogic">6&#39;d1</span>;
265
<a name="l00235"></a>00235         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
266
<a name="l00236"></a>00236     <span class="vhdlkeyword">end</span>
267
<a name="l00237"></a>00237     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d50062</span>) <span class="vhdlkeyword">begin</span>
268
<a name="l00238"></a>00238         <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#a7923eccb18a807d0dd25fc649fc315f3">start_load</a> == <span class="vhdllogic">1&#39;b1</span>) <span class="vhdlkeyword">begin</span>
269
<a name="l00239"></a>00239             <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
270
<a name="l00240"></a>00240             <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
271
<a name="l00241"></a>00241             <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">7&#39;d0</span>, <a class="code" href="classvga__capture.html#a2e2d5d858bb65882da803f77dc3ad9f9">vga_line_number</a> };
272
<a name="l00242"></a>00242
273
<a name="l00243"></a>00243             <a class="code" href="classvga__capture.html#a175510c6d10d0a359dc13b81334bb11f">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
274
<a name="l00244"></a>00244             <a class="code" href="classvga__capture.html#ace8b499e7026ba90ce684a7b596409a3">fifo_rd_cnt</a> &lt;= <span class="vhdllogic">2&#39;d0</span>;
275
<a name="l00245"></a>00245             <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
276
<a name="l00246"></a>00246         <span class="vhdlkeyword">end</span>
277
<a name="l00247"></a>00247     <span class="vhdlkeyword">end</span>
278
<a name="l00248"></a>00248     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d50063</span>) <span class="vhdlkeyword">begin</span>
279
<a name="l00249"></a>00249         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
280
<a name="l00250"></a>00250         <a class="code" href="classvga__capture.html#a175510c6d10d0a359dc13b81334bb11f">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
281
<a name="l00251"></a>00251         <a class="code" href="classvga__capture.html#a8094baf5a487d00c87e5abaf86e3ebb6">last_fifo_q</a> &lt;= <a class="code" href="classvga__capture.html#af60734bc0dd9ee6c76a6ad073a2922c0">fifo_q</a>;
282
<a name="l00252"></a>00252         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
283
<a name="l00253"></a>00253     <span class="vhdlkeyword">end</span>
284
<a name="l00254"></a>00254
285
<a name="l00255"></a>00255
286
<a name="l00256"></a>00256     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &gt;= <span class="vhdllogic">16&#39;d50064</span> &amp;&amp; <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d51022</span> &amp;&amp; <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b0</span>) <span class="vhdlkeyword">begin</span>
287
<a name="l00257"></a>00257         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
288
<a name="l00258"></a>00258         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
289
<a name="l00259"></a>00259
290
<a name="l00260"></a>00260         <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#ace8b499e7026ba90ce684a7b596409a3">fifo_rd_cnt</a> == <span class="vhdllogic">2&#39;d0</span>)     <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <a class="code" href="classvga__capture.html#af60734bc0dd9ee6c76a6ad073a2922c0">fifo_q</a>[<span class="vhdllogic">3</span>:<span class="vhdllogic">0</span>], <a class="code" href="classvga__capture.html#a8094baf5a487d00c87e5abaf86e3ebb6">last_fifo_q</a> };
291
<a name="l00261"></a>00261         <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#ace8b499e7026ba90ce684a7b596409a3">fifo_rd_cnt</a> == <span class="vhdllogic">2&#39;d1</span>)<a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <a class="code" href="classvga__capture.html#af60734bc0dd9ee6c76a6ad073a2922c0">fifo_q</a>[<span class="vhdllogic">7</span>:<span class="vhdllogic">0</span>], <a class="code" href="classvga__capture.html#a8094baf5a487d00c87e5abaf86e3ebb6">last_fifo_q</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">4</span>] };
292
<a name="l00262"></a>00262         <span class="vhdlkeyword">else</span>                        <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <a class="code" href="classvga__capture.html#af60734bc0dd9ee6c76a6ad073a2922c0">fifo_q</a>, <a class="code" href="classvga__capture.html#a8094baf5a487d00c87e5abaf86e3ebb6">last_fifo_q</a>[<span class="vhdllogic">11</span>:<span class="vhdllogic">8</span>] };
293
<a name="l00263"></a>00263
294
<a name="l00264"></a>00264         <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#ace8b499e7026ba90ce684a7b596409a3">fifo_rd_cnt</a> == <span class="vhdllogic">2&#39;d2</span>) <a class="code" href="classvga__capture.html#a175510c6d10d0a359dc13b81334bb11f">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
295
<a name="l00265"></a>00265         <span class="vhdlkeyword">else</span>                    <a class="code" href="classvga__capture.html#a175510c6d10d0a359dc13b81334bb11f">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
296
<a name="l00266"></a>00266
297
<a name="l00267"></a>00267         <a class="code" href="classvga__capture.html#ace8b499e7026ba90ce684a7b596409a3">fifo_rd_cnt</a> &lt;= <a class="code" href="classvga__capture.html#ace8b499e7026ba90ce684a7b596409a3">fifo_rd_cnt</a> + <span class="vhdllogic">2&#39;d1</span>;
298
<a name="l00268"></a>00268         <a class="code" href="classvga__capture.html#a8094baf5a487d00c87e5abaf86e3ebb6">last_fifo_q</a> &lt;= <a class="code" href="classvga__capture.html#af60734bc0dd9ee6c76a6ad073a2922c0">fifo_q</a>;
299
<a name="l00269"></a>00269
300
<a name="l00270"></a>00270         <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d51022</span>)  <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d60016</span> - <span class="vhdllogic">16&#39;d1</span>;
301
<a name="l00271"></a>00271         <span class="vhdlkeyword">else</span>                            <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
302
<a name="l00272"></a>00272     <span class="vhdlkeyword">end</span>
303
<a name="l00273"></a>00273     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &gt;= <span class="vhdllogic">16&#39;d50064</span> &amp;&amp; <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d51022</span> &amp;&amp; <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b1</span> &amp;&amp; <a class="code" href="classvga__capture.html#ace8b499e7026ba90ce684a7b596409a3">fifo_rd_cnt</a> == <span class="vhdllogic">2&#39;d3</span>) <span class="vhdlkeyword">begin</span>
304
<a name="l00274"></a>00274         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
305
<a name="l00275"></a>00275         <a class="code" href="classvga__capture.html#a175510c6d10d0a359dc13b81334bb11f">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
306
<a name="l00276"></a>00276         <a class="code" href="classvga__capture.html#a8094baf5a487d00c87e5abaf86e3ebb6">last_fifo_q</a> &lt;= <a class="code" href="classvga__capture.html#af60734bc0dd9ee6c76a6ad073a2922c0">fifo_q</a>;
307
<a name="l00277"></a>00277         <a class="code" href="classvga__capture.html#ace8b499e7026ba90ce684a7b596409a3">fifo_rd_cnt</a> &lt;= <span class="vhdllogic">2&#39;d0</span>;
308
<a name="l00278"></a>00278         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
309
<a name="l00279"></a>00279     <span class="vhdlkeyword">end</span>
310
<a name="l00280"></a>00280     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &gt;= <span class="vhdllogic">16&#39;d50064</span> &amp;&amp; <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d51022</span> &amp;&amp; <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a>[<span class="vhdllogic">0</span>] == <span class="vhdllogic">1&#39;b1</span>) <span class="vhdlkeyword">begin</span>
311
<a name="l00281"></a>00281         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
312
<a name="l00282"></a>00282         <a class="code" href="classvga__capture.html#a175510c6d10d0a359dc13b81334bb11f">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
313
<a name="l00283"></a>00283         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
314
<a name="l00284"></a>00284     <span class="vhdlkeyword">end</span>
315
<a name="l00285"></a>00285
316
<a name="l00286"></a>00286
317
<a name="l00287"></a>00287     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d60016</span>) <span class="vhdlkeyword">begin</span>
318
<a name="l00288"></a>00288         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
319
<a name="l00289"></a>00289         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
320
<a name="l00290"></a>00290         <a class="code" href="classvga__capture.html#a5803d9b80a06d8486e2af6b362cc6177">enet_data_oe</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
321
<a name="l00291"></a>00291         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h02</span> }; <span class="keyword">// read TX(02h bit 0 == 0)</span>
322
<a name="l00292"></a>00292
323
<a name="l00293"></a>00293         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
324
<a name="l00294"></a>00294     <span class="vhdlkeyword">end</span>
325
<a name="l00295"></a>00295     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d60018</span>) <span class="vhdlkeyword">begin</span>
326
<a name="l00296"></a>00296         <a class="code" href="classvga__capture.html#afdb7af2d1042c612676529bdcd68a05c">enet_ior_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
327
<a name="l00297"></a>00297         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
328
<a name="l00298"></a>00298         <a class="code" href="classvga__capture.html#a5803d9b80a06d8486e2af6b362cc6177">enet_data_oe</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
329
<a name="l00299"></a>00299
330
<a name="l00300"></a>00300         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
331
<a name="l00301"></a>00301     <span class="vhdlkeyword">end</span>
332
<a name="l00302"></a>00302     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d60020</span>) <span class="vhdlkeyword">begin</span>
333
<a name="l00303"></a>00303         <a class="code" href="classvga__capture.html#afdb7af2d1042c612676529bdcd68a05c">enet_ior_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
334
<a name="l00304"></a>00304         <a class="code" href="classvga__capture.html#a9b7fb3d3f6c622692e3d5b65e050753a">tx_active</a> &lt;= <a class="code" href="classvga__capture.html#a415a70b3d7198d3282610022751de6d8">enet_data</a>[<span class="vhdllogic">0</span>];
335
<a name="l00305"></a>00305
336
<a name="l00306"></a>00306         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
337
<a name="l00307"></a>00307     <span class="vhdlkeyword">end</span>
338
<a name="l00308"></a>00308     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d60022</span>) <span class="vhdlkeyword">begin</span>
339
<a name="l00309"></a>00309         <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#a9b7fb3d3f6c622692e3d5b65e050753a">tx_active</a> == <span class="vhdllogic">1&#39;b0</span>)   <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d60118</span>;
340
<a name="l00310"></a>00310         <span class="vhdlkeyword">else</span>                    <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d60016</span>;
341
<a name="l00311"></a>00311     <span class="vhdlkeyword">end</span>
342
<a name="l00312"></a>00312
343
<a name="l00313"></a>00313     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d60118</span>) <span class="vhdlkeyword">begin</span>
344
<a name="l00314"></a>00314         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
345
<a name="l00315"></a>00315         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
346
<a name="l00316"></a>00316         <a class="code" href="classvga__capture.html#a5803d9b80a06d8486e2af6b362cc6177">enet_data_oe</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
347
<a name="l00317"></a>00317         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;hFC</span> }; <span class="keyword">// set TXPLL(FCh = low byte)</span>
348
<a name="l00318"></a>00318
349
<a name="l00319"></a>00319         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
350
<a name="l00320"></a>00320     <span class="vhdlkeyword">end</span>
351
<a name="l00321"></a>00321     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d60120</span>) <span class="vhdlkeyword">begin</span>
352
<a name="l00322"></a>00322         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
353
<a name="l00323"></a>00323         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
354
<a name="l00324"></a>00324         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;h00</span>, <span class="vhdllogic">8&#39;hEC</span> };
355
<a name="l00325"></a>00325
356
<a name="l00326"></a>00326         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
357
<a name="l00327"></a>00327     <span class="vhdlkeyword">end</span>
358
<a name="l00328"></a>00328
359
<a name="l00329"></a>00329     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d60123</span>) <span class="vhdlkeyword">begin</span>
360
<a name="l00330"></a>00330         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
361
<a name="l00331"></a>00331         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
362
<a name="l00332"></a>00332         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;hFD</span> }; <span class="keyword">// set TXPLH(FDh = high byte)</span>
363
<a name="l00333"></a>00333
364
<a name="l00334"></a>00334         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
365
<a name="l00335"></a>00335     <span class="vhdlkeyword">end</span>
366
<a name="l00336"></a>00336     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d60125</span>) <span class="vhdlkeyword">begin</span>
367
<a name="l00337"></a>00337         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
368
<a name="l00338"></a>00338         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
369
<a name="l00339"></a>00339         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;h00</span>, <span class="vhdllogic">8&#39;h03</span> };
370
<a name="l00340"></a>00340
371
<a name="l00341"></a>00341         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
372
<a name="l00342"></a>00342     <span class="vhdlkeyword">end</span>
373
<a name="l00343"></a>00343
374
<a name="l00344"></a>00344     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d60128</span>) <span class="vhdlkeyword">begin</span>
375
<a name="l00345"></a>00345         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
376
<a name="l00346"></a>00346         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
377
<a name="l00347"></a>00347         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;d0</span>, <span class="vhdllogic">8&#39;h02</span> }; <span class="keyword">// write TX(02h = 0x01)</span>
378
<a name="l00348"></a>00348
379
<a name="l00349"></a>00349         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
380
<a name="l00350"></a>00350     <span class="vhdlkeyword">end</span>
381
<a name="l00351"></a>00351     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d60130</span>) <span class="vhdlkeyword">begin</span>
382
<a name="l00352"></a>00352         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
383
<a name="l00353"></a>00353         <a class="code" href="classvga__capture.html#a7c8b996d7a08a3fb7b63f0667a7e12ef">enet_cmd</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
384
<a name="l00354"></a>00354         <a class="code" href="classvga__capture.html#ad5deabd97e23df6cb94a55be33a5e13d">enet_data_out</a> &lt;= { <span class="vhdllogic">8&#39;h00</span>, <span class="vhdllogic">8&#39;h01</span> };
385
<a name="l00355"></a>00355
386
<a name="l00356"></a>00356         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
387
<a name="l00357"></a>00357     <span class="vhdlkeyword">end</span>
388
<a name="l00358"></a>00358
389
<a name="l00359"></a>00359     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> == <span class="vhdllogic">16&#39;d60132</span>) <span class="vhdlkeyword">begin</span>
390
<a name="l00360"></a>00360          <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d50018</span>;
391
<a name="l00361"></a>00361     <span class="vhdlkeyword">end</span>
392
<a name="l00362"></a>00362
393
<a name="l00363"></a>00363     <span class="vhdlkeyword">else</span> <span class="vhdlkeyword">if</span>(<a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <span class="vhdllogic">16&#39;d60132</span>) <span class="vhdlkeyword">begin</span>
394
<a name="l00364"></a>00364         <a class="code" href="classvga__capture.html#ad93acbeb04b4866cbe168acea048fc00">enet_iow_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
395
<a name="l00365"></a>00365         <a class="code" href="classvga__capture.html#afdb7af2d1042c612676529bdcd68a05c">enet_ior_n</a> &lt;= <span class="vhdllogic">1&#39;b1</span>;
396
<a name="l00366"></a>00366         <a class="code" href="classvga__capture.html#a175510c6d10d0a359dc13b81334bb11f">fifo_rdreq</a> &lt;= <span class="vhdllogic">1&#39;b0</span>;
397
<a name="l00367"></a>00367         <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> &lt;= <a class="code" href="classvga__capture.html#afd0d6bf88f5d0192aea0a9e15469b823">state_counter</a> + <span class="vhdllogic">16&#39;d1</span>;
398
<a name="l00368"></a>00368     <span class="vhdlkeyword">end</span>
399
<a name="l00369"></a>00369
400
<a name="l00370"></a>00370 <span class="vhdlkeyword">end</span>
401
<a name="l00371"></a>00371
402
<a name="l00372"></a>00372 <span class="vhdlkeyword">endmodule</span>
403
</pre></div></div>
404
</div>
405
<hr class="footer"/><address class="footer"><small>Generated on Sat Dec 18 2010 22:33:58 for aoOCS by&#160;
406
<a href="http://www.doxygen.org/index.html">
407
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.7.2 </small></address>
408
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409
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