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[/] [aoocs/] [trunk/] [tests/] [ssram_test/] [ssram_test.v] - Blame information for rev 2

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module ssram_test(
        input clk,
        input reset_n,
 
        // ssram
        output reg [18:0] ssram_address,
        output reg ssram_oe_n,
        output reg ssram_writeen_n,
        output reg [3:0] ssram_byteen_n,
        output ssram_adsp_n,
        output ssram_clk,
        output ssram_globalw_n,
        output reg ssram_advance_n,
        output reg ssram_adsc_n,
        output ssram_ce1_n,
        output ssram_ce2,
        output ssram_ce3_n,
        inout [35:0] ssram_data,
 
        output [7:0] debug
);
 
assign debug = { 3'd0, state };
 
assign ssram_clk = clk;
assign ssram_globalw_n = 1'b1;
assign ssram_adsp_n = 1'b1;
assign ssram_ce1_n = 1'b0;
assign ssram_ce2 = 1'b1;
assign ssram_ce3_n = 1'b0;
 
reg ssram_data_oe;
reg [35:0] ssram_data_reg;
assign ssram_data = (ssram_data_oe == 1'b1) ? ssram_data_reg : 36'bZ;
 
reg [4:0] state;
parameter [4:0]
        S_IDLE = 5'd0,
        S_W1 = 5'd1,
        S_W2 = 5'd2,
        S_W3 = 5'd3,
        S_W4 = 5'd4,
        S_W5 = 5'd5,
        S_W6 = 5'd6,
        S_IDLE2 = 5'd7,
        S_R1 = 5'd8,
        S_R2 = 5'd9,
        S_R3 = 5'd10,
        S_R4 = 5'd11,
        S_R5 = 5'd12,
        S_R6 = 5'd13,
        S_R7 = 5'd14,
        S_R8 = 5'd15,
        S_R9 = 5'd16,
        S_IDLE3 = 5'd17,
        S_IDLE4 = 5'd18;
 
altsyncram debug_ram_inst(
        .clock0(clk),
 
        .address_a({3'b0, state}),
        .wren_a(state < 5'd17),
        .data_a(ssram_data),
        .q_a()
);
defparam
    debug_ram_inst.operation_mode = "SINGLE_PORT",
    debug_ram_inst.width_a = 36,
    debug_ram_inst.widthad_a = 8,
    debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=vgadeb";
 
 
always @(posedge clk or negedge reset_n) begin
        if(reset_n == 1'b0) begin
                ssram_address <= 19'd0;
                ssram_adsc_n <= 1'b1;
                ssram_advance_n <= 1'b1;
                ssram_data_reg <= 36'd0;
                ssram_data_oe <= 1'b0;
                ssram_oe_n <= 1'b1;
                ssram_writeen_n <= 1'b1;
                ssram_byteen_n <= 4'b1111;
 
                state <= S_IDLE;
        end
        else begin
                case(state)
                        S_IDLE: begin
                                ssram_address <= 19'd0;
                                ssram_adsc_n <= 1'b1;
                                ssram_advance_n <= 1'b1;
                                ssram_data_reg <= 36'd0;
                                ssram_data_oe <= 1'b0;
                                ssram_oe_n <= 1'b1;
                                ssram_writeen_n <= 1'b1;
                                ssram_byteen_n <= 4'b1111;
 
                                state <= S_R1;
                        end
                        S_W1: begin
                                // address, byte enables and write enables output
                                ssram_address <= 19'h23600;
                                ssram_adsc_n <= 1'b0;
                                ssram_advance_n <= 1'b1;
                                ssram_data_reg <= { 4'b0, 32'hC1000008 };
                                ssram_data_oe <= 1'b1;
                                ssram_oe_n <= 1'b1;
                                ssram_writeen_n <= 1'b0;
                                ssram_byteen_n <= 4'b0000;
 
                                state <= S_W2;
                        end
                        S_W2: begin
                                ssram_adsc_n <= 1'b1;
                                ssram_advance_n <= 1'b0;
                                ssram_data_reg <= { 4'b0, 32'hC2000007 };
 
                                state <= S_W3;
                        end
                        S_W3: begin
                                ssram_data_reg <= { 4'b0, 32'hC3000006 };
 
                                state <= S_W4;
                        end
                        S_W4: begin
                                ssram_data_reg <= { 4'b0, 32'hC4000005 };
 
                                state <= S_W5;
                        end
                        S_W5: begin
                                ssram_address <= 19'h23604;
                                ssram_adsc_n <= 1'b0;
                                ssram_advance_n <= 1'b1;
                                ssram_data_reg <= { 4'b0, 32'hC5000004 };
 
                                state <= S_W6;
                        end
                        S_W6: begin
                                ssram_adsc_n <= 1'b1;
                                ssram_advance_n <= 1'b0;
                                ssram_data_reg <= { 4'b0, 32'hC6000003 };
 
                                state <= S_IDLE2;
                        end
 
                        S_IDLE2: begin
                                ssram_address <= 19'd0;
                                ssram_adsc_n <= 1'b1;
                                ssram_advance_n <= 1'b1;
                                ssram_data_reg <= 32'd0;
                                ssram_data_oe <= 1'b0;
                                ssram_oe_n <= 1'b1;
                                ssram_writeen_n <= 1'b1;
                                ssram_byteen_n <= 4'b1111;
 
                                state <= S_R1;
                        end
                        S_R1: begin
                                // address and byte enables output
                                ssram_address <= 19'h2D800; //19'd0;
                                ssram_adsc_n <= 1'b0;
                                ssram_advance_n <= 1'b1;
                                ssram_data_reg <= 32'd0;
                                ssram_data_oe <= 1'b0;
                                ssram_oe_n <= 1'b1;
                                ssram_writeen_n <= 1'b1;
                                ssram_byteen_n <= 4'b0000;
 
                                state <= S_R2;
                        end
                        S_R2: begin
                                // address and byte enables latched
                                ssram_adsc_n <= 1'b1;
                                ssram_advance_n <= 1'b0;
 
                                state <= S_R3;
                        end
                        S_R3: begin
                                // output enable output
                                ssram_oe_n <= 1'b0;
 
                                state <= S_R4;
                        end
                        S_R4: begin
                                // save data output
                                //if(ssram_data[31:0] == { 4'b0, 32'hC1000000 })
                                        state <= S_R5;
                                //else
                                //      state <= S_IDLE4;
                        end
                        S_R5: begin
                                ssram_address <= 19'h2D804;//19'd4;
                                ssram_adsc_n <= 1'b0;
                                ssram_advance_n <= 1'b1;
 
                                //if(ssram_data[31:0] == { 4'b0, 32'hC2000000 })
                                        state <= S_R6;
                                //else
                                //      state <= S_IDLE4;
                        end
                        S_R6: begin
                                ssram_adsc_n <= 1'b1;
                                ssram_advance_n <= 1'b0;
 
                                //if(ssram_data[31:0] == { 4'b0, 32'hC3000000 })
                                        state <= S_R7;
                                //else
                                //      state <= S_IDLE4;
                        end
                        S_R7: begin
                                //if(ssram_data[31:0] == { 4'b0, 32'hC4000000 })
                                        state <= S_R8;
                                //else
                                //      state <= S_IDLE4;
                        end
                        S_R8: begin
                                //if(ssram_data[31:0] == { 4'b0, 32'hC5000000 })
                                        state <= S_R9;//S_IDLE3;
                                //else
                                //      state <= S_IDLE4;
                        end
                        S_R9: begin
                                state <= S_IDLE3;
                        end
                        S_IDLE3: begin
                                ssram_address <= 19'd0;
                                ssram_adsc_n <= 1'b1;
                                ssram_advance_n <= 1'b1;
                                ssram_data_reg <= 32'd0;
                                ssram_data_oe <= 1'b0;
                                ssram_oe_n <= 1'b1;
                                ssram_writeen_n <= 1'b1;
                                ssram_byteen_n <= 4'b1111;
                        end
                        S_IDLE4: begin
                                ssram_address <= 19'd0;
                                ssram_adsc_n <= 1'b1;
                                ssram_advance_n <= 1'b1;
                                ssram_data_reg <= 32'd0;
                                ssram_data_oe <= 1'b0;
                                ssram_oe_n <= 1'b1;
                                ssram_writeen_n <= 1'b1;
                                ssram_byteen_n <= 4'b1111;
                        end
                endcase
        end
end
 
endmodule
 
 
/*
// TEST: with static adsc_n and adsp_n -> can not write 2-burst
module ssram_test(
        input clk,
        input reset_n,
 
        // ssram
        output reg [18:0] ssram_address,
        output reg ssram_oe_n,
        output reg ssram_writeen_n,
        output reg [3:0] ssram_byteen_n,
        output ssram_adsp_n,
        output ssram_clk,
        output ssram_globalw_n,
        output ssram_advance_n,
        output ssram_adsc_n,
        output ssram_ce1_n,
        output ssram_ce2,
        output ssram_ce3_n,
        inout [35:0] ssram_data,
 
        output [7:0] debug
);
 
assign debug = DAT_I[31:24];
 
assign ssram_clk = clk;
assign ssram_globalw_n = 1'b1;
assign ssram_adsp_n = 1'b1;
assign ssram_ce1_n = 1'b0;
assign ssram_ce2 = 1'b1;
assign ssram_ce3_n = 1'b0;
assign ssram_advance_n = 1'b1;
assign ssram_adsc_n = 1'b1;
 
reg ssram_data_oe;
reg [35:0] ssram_data_reg;
assign ssram_data = (ssram_data_oe == 1'b1) ? ssram_data_reg : 36'bZ;
 
reg [31:0] DAT_I;
 
reg [3:0] state;
parameter [3:0]
        S_IDLE = 4'd0,
        S_W1 = 4'd1,
        S_W2 = 4'd2,
        S_W3 = 4'd3,
        S_W4 = 4'd4,
        S_W5 = 4'd5,
        S_IDLE2 = 4'd6,
        S_R1 = 4'd7,
        S_R2 = 4'd8,
        S_R3 = 4'd9,
        S_R4 = 4'd10,
        S_IDLE3 = 4'd11;
 
        always @(posedge clk or negedge reset_n) begin
        if(reset_n == 1'b0) begin
                ssram_address <= 19'd0;
                ssram_data_reg <= 36'd0;
                ssram_data_oe <= 1'b0;
                ssram_oe_n <= 1'b1;
                ssram_writeen_n <= 1'b1;
                ssram_byteen_n <= 4'b1111;
 
                DAT_I <= 32'd0;
                state <= S_IDLE;
        end
        else begin
                case(state)
                        S_IDLE: begin
                                ssram_address <= 19'd0;
                                ssram_data_reg <= 36'd0;
                                ssram_data_oe <= 1'b0;
                                ssram_oe_n <= 1'b1;
                                ssram_writeen_n <= 1'b1;
                                ssram_byteen_n <= 4'b1111;
 
                                state <= S_W1;
                        end
                        S_W1: begin
                                // address, byte enables and write enables output
                                ssram_address <= 19'd0;
                                ssram_data_reg <= 36'd0;
                                ssram_data_oe <= 1'b0;
                                ssram_oe_n <= 1'b1;
                                ssram_writeen_n <= 1'b0;
                                ssram_byteen_n <= 4'b0000;
 
                                state <= S_W2;
                        end
                        S_W2: begin
                                // address, byte enables and write enables latched
                                ssram_data_reg <= { 4'b0, 32'h71000000 };
                                ssram_data_oe <= 1'b1;
 
                                ssram_address <= 19'd1;
 
                                state <= S_W3;
                        end
                        S_W3: begin
                                state <= S_W4;
                        end
                        S_W4: begin
                                ssram_data_reg <= { 4'b0, 32'h72000000 };
 
                                state <= S_IDLE2;
                        end
 
                        S_IDLE2: begin
                                ssram_address <= 19'd0;
                                ssram_data_reg <= 32'd0;
                                ssram_data_oe <= 1'b0;
                                ssram_oe_n <= 1'b1;
                                ssram_writeen_n <= 1'b1;
                                ssram_byteen_n <= 4'b1111;
 
                                state <= S_R1;
                        end
                        S_R1: begin
                                // address and byte enables output
                                ssram_address <= 19'd0;
                                ssram_data_reg <= 32'd0;
                                ssram_data_oe <= 1'b0;
                                ssram_oe_n <= 1'b1;
                                ssram_writeen_n <= 1'b1;
                                ssram_byteen_n <= 4'b0000;
 
                                state <= S_R2;
                        end
                        S_R2: begin
                                // address and byte enables latched
                                state <= S_R3;
                        end
                        S_R3: begin
                                // output enable output
                                ssram_oe_n <= 1'b0;
 
                                state <= S_R4;
                        end
                        S_R4: begin
                                // save data output
                                DAT_I <= ssram_data[31:0];
 
                                state <= S_IDLE3;
                        end
                        S_IDLE3: begin
                                ssram_address <= 19'd0;
                                ssram_data_reg <= 32'd0;
                                ssram_data_oe <= 1'b0;
                                ssram_oe_n <= 1'b1;
                                ssram_writeen_n <= 1'b1;
                                ssram_byteen_n <= 4'b1111;
                        end
                endcase
        end
end
 
endmodule
*/

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[/] [aoocs/] [trunk/] [tests/] [ssram_test/] [ssram_test.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	alfik	`module ssram_test(`
2			`input clk,`
3			`input reset_n,`
4
5			`// ssram`
6			`output reg [18:0] ssram_address,`
7			`output reg ssram_oe_n,`
8			`output reg ssram_writeen_n,`
9			`output reg [3:0] ssram_byteen_n,`
10			`output ssram_adsp_n,`
11			`output ssram_clk,`
12			`output ssram_globalw_n,`
13			`output reg ssram_advance_n,`
14			`output reg ssram_adsc_n,`
15			`output ssram_ce1_n,`
16			`output ssram_ce2,`
17			`output ssram_ce3_n,`
18			`inout [35:0] ssram_data,`
19
20			`output [7:0] debug`
21			`);`
22
23			`assign debug = { 3'd0, state };`
24
25			`assign ssram_clk = clk;`
26			`assign ssram_globalw_n = 1'b1;`
27			`assign ssram_adsp_n = 1'b1;`
28			`assign ssram_ce1_n = 1'b0;`
29			`assign ssram_ce2 = 1'b1;`
30			`assign ssram_ce3_n = 1'b0;`
31
32			`reg ssram_data_oe;`
33			`reg [35:0] ssram_data_reg;`
34			`assign ssram_data = (ssram_data_oe == 1'b1) ? ssram_data_reg : 36'bZ;`
35
36			`reg [4:0] state;`
37			`parameter [4:0]`
38			`S_IDLE = 5'd0,`
39			`S_W1 = 5'd1,`
40			`S_W2 = 5'd2,`
41			`S_W3 = 5'd3,`
42			`S_W4 = 5'd4,`
43			`S_W5 = 5'd5,`
44			`S_W6 = 5'd6,`
45			`S_IDLE2 = 5'd7,`
46			`S_R1 = 5'd8,`
47			`S_R2 = 5'd9,`
48			`S_R3 = 5'd10,`
49			`S_R4 = 5'd11,`
50			`S_R5 = 5'd12,`
51			`S_R6 = 5'd13,`
52			`S_R7 = 5'd14,`
53			`S_R8 = 5'd15,`
54			`S_R9 = 5'd16,`
55			`S_IDLE3 = 5'd17,`
56			`S_IDLE4 = 5'd18;`
57
58			`altsyncram debug_ram_inst(`
59			`.clock0(clk),`
60
61			`.address_a({3'b0, state}),`
62			`.wren_a(state < 5'd17),`
63			`.data_a(ssram_data),`
64			`.q_a()`
65			`);`
66			`defparam`
67			`debug_ram_inst.operation_mode = "SINGLE_PORT",`
68			`debug_ram_inst.width_a = 36,`
69			`debug_ram_inst.widthad_a = 8,`
70			`debug_ram_inst.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=vgadeb";`
71
72
73			`always @(posedge clk or negedge reset_n) begin`
74			`if(reset_n == 1'b0) begin`
75			`ssram_address <= 19'd0;`
76			`ssram_adsc_n <= 1'b1;`
77			`ssram_advance_n <= 1'b1;`
78			`ssram_data_reg <= 36'd0;`
79			`ssram_data_oe <= 1'b0;`
80			`ssram_oe_n <= 1'b1;`
81			`ssram_writeen_n <= 1'b1;`
82			`ssram_byteen_n <= 4'b1111;`
83
84			`state <= S_IDLE;`
85			`end`
86			`else begin`
87			`case(state)`
88			`S_IDLE: begin`
89			`ssram_address <= 19'd0;`
90			`ssram_adsc_n <= 1'b1;`
91			`ssram_advance_n <= 1'b1;`
92			`ssram_data_reg <= 36'd0;`
93			`ssram_data_oe <= 1'b0;`
94			`ssram_oe_n <= 1'b1;`
95			`ssram_writeen_n <= 1'b1;`
96			`ssram_byteen_n <= 4'b1111;`
97
98			`state <= S_R1;`
99			`end`
100			`S_W1: begin`
101			`// address, byte enables and write enables output`
102			`ssram_address <= 19'h23600;`
103			`ssram_adsc_n <= 1'b0;`
104			`ssram_advance_n <= 1'b1;`
105			`ssram_data_reg <= { 4'b0, 32'hC1000008 };`
106			`ssram_data_oe <= 1'b1;`
107			`ssram_oe_n <= 1'b1;`
108			`ssram_writeen_n <= 1'b0;`
109			`ssram_byteen_n <= 4'b0000;`
110
111			`state <= S_W2;`
112			`end`
113			`S_W2: begin`
114			`ssram_adsc_n <= 1'b1;`
115			`ssram_advance_n <= 1'b0;`
116			`ssram_data_reg <= { 4'b0, 32'hC2000007 };`
117
118			`state <= S_W3;`
119			`end`
120			`S_W3: begin`
121			`ssram_data_reg <= { 4'b0, 32'hC3000006 };`
122
123			`state <= S_W4;`
124			`end`
125			`S_W4: begin`
126			`ssram_data_reg <= { 4'b0, 32'hC4000005 };`
127
128			`state <= S_W5;`
129			`end`
130			`S_W5: begin`
131			`ssram_address <= 19'h23604;`
132			`ssram_adsc_n <= 1'b0;`
133			`ssram_advance_n <= 1'b1;`
134			`ssram_data_reg <= { 4'b0, 32'hC5000004 };`
135
136			`state <= S_W6;`
137			`end`
138			`S_W6: begin`
139			`ssram_adsc_n <= 1'b1;`
140			`ssram_advance_n <= 1'b0;`
141			`ssram_data_reg <= { 4'b0, 32'hC6000003 };`
142
143			`state <= S_IDLE2;`
144			`end`
145
146			`S_IDLE2: begin`
147			`ssram_address <= 19'd0;`
148			`ssram_adsc_n <= 1'b1;`
149			`ssram_advance_n <= 1'b1;`
150			`ssram_data_reg <= 32'd0;`
151			`ssram_data_oe <= 1'b0;`
152			`ssram_oe_n <= 1'b1;`
153			`ssram_writeen_n <= 1'b1;`
154			`ssram_byteen_n <= 4'b1111;`
155
156			`state <= S_R1;`
157			`end`
158			`S_R1: begin`
159			`// address and byte enables output`
160			`ssram_address <= 19'h2D800; //19'd0;`
161			`ssram_adsc_n <= 1'b0;`
162			`ssram_advance_n <= 1'b1;`
163			`ssram_data_reg <= 32'd0;`
164			`ssram_data_oe <= 1'b0;`
165			`ssram_oe_n <= 1'b1;`
166			`ssram_writeen_n <= 1'b1;`
167			`ssram_byteen_n <= 4'b0000;`
168
169			`state <= S_R2;`
170			`end`
171			`S_R2: begin`
172			`// address and byte enables latched`
173			`ssram_adsc_n <= 1'b1;`
174			`ssram_advance_n <= 1'b0;`
175
176			`state <= S_R3;`
177			`end`
178			`S_R3: begin`
179			`// output enable output`
180			`ssram_oe_n <= 1'b0;`
181
182			`state <= S_R4;`
183			`end`
184			`S_R4: begin`
185			`// save data output`
186			`//if(ssram_data[31:0] == { 4'b0, 32'hC1000000 })`
187			`state <= S_R5;`
188			`//else`
189			`// state <= S_IDLE4;`
190			`end`
191			`S_R5: begin`
192			`ssram_address <= 19'h2D804;//19'd4;`
193			`ssram_adsc_n <= 1'b0;`
194			`ssram_advance_n <= 1'b1;`
195
196			`//if(ssram_data[31:0] == { 4'b0, 32'hC2000000 })`
197			`state <= S_R6;`
198			`//else`
199			`// state <= S_IDLE4;`
200			`end`
201			`S_R6: begin`
202			`ssram_adsc_n <= 1'b1;`
203			`ssram_advance_n <= 1'b0;`
204
205			`//if(ssram_data[31:0] == { 4'b0, 32'hC3000000 })`
206			`state <= S_R7;`
207			`//else`
208			`// state <= S_IDLE4;`
209			`end`
210			`S_R7: begin`
211			`//if(ssram_data[31:0] == { 4'b0, 32'hC4000000 })`
212			`state <= S_R8;`
213			`//else`
214			`// state <= S_IDLE4;`
215			`end`
216			`S_R8: begin`
217			`//if(ssram_data[31:0] == { 4'b0, 32'hC5000000 })`
218			`state <= S_R9;//S_IDLE3;`
219			`//else`
220			`// state <= S_IDLE4;`
221			`end`
222			`S_R9: begin`
223			`state <= S_IDLE3;`
224			`end`
225			`S_IDLE3: begin`
226			`ssram_address <= 19'd0;`
227			`ssram_adsc_n <= 1'b1;`
228			`ssram_advance_n <= 1'b1;`
229			`ssram_data_reg <= 32'd0;`
230			`ssram_data_oe <= 1'b0;`
231			`ssram_oe_n <= 1'b1;`
232			`ssram_writeen_n <= 1'b1;`
233			`ssram_byteen_n <= 4'b1111;`
234			`end`
235			`S_IDLE4: begin`
236			`ssram_address <= 19'd0;`
237			`ssram_adsc_n <= 1'b1;`
238			`ssram_advance_n <= 1'b1;`
239			`ssram_data_reg <= 32'd0;`
240			`ssram_data_oe <= 1'b0;`
241			`ssram_oe_n <= 1'b1;`
242			`ssram_writeen_n <= 1'b1;`
243			`ssram_byteen_n <= 4'b1111;`
244			`end`
245			`endcase`
246			`end`
247			`end`
248
249			`endmodule`
250
251
252			`/*`
253			`// TEST: with static adsc_n and adsp_n -> can not write 2-burst`
254			`module ssram_test(`
255			`input clk,`
256			`input reset_n,`
257
258			`// ssram`
259			`output reg [18:0] ssram_address,`
260			`output reg ssram_oe_n,`
261			`output reg ssram_writeen_n,`
262			`output reg [3:0] ssram_byteen_n,`
263			`output ssram_adsp_n,`
264			`output ssram_clk,`
265			`output ssram_globalw_n,`
266			`output ssram_advance_n,`
267			`output ssram_adsc_n,`
268			`output ssram_ce1_n,`
269			`output ssram_ce2,`
270			`output ssram_ce3_n,`
271			`inout [35:0] ssram_data,`
272
273			`output [7:0] debug`
274			`);`
275
276			`assign debug = DAT_I[31:24];`
277
278			`assign ssram_clk = clk;`
279			`assign ssram_globalw_n = 1'b1;`
280			`assign ssram_adsp_n = 1'b1;`
281			`assign ssram_ce1_n = 1'b0;`
282			`assign ssram_ce2 = 1'b1;`
283			`assign ssram_ce3_n = 1'b0;`
284			`assign ssram_advance_n = 1'b1;`
285			`assign ssram_adsc_n = 1'b1;`
286
287			`reg ssram_data_oe;`
288			`reg [35:0] ssram_data_reg;`
289			`assign ssram_data = (ssram_data_oe == 1'b1) ? ssram_data_reg : 36'bZ;`
290
291			`reg [31:0] DAT_I;`
292
293			`reg [3:0] state;`
294			`parameter [3:0]`
295			`S_IDLE = 4'd0,`
296			`S_W1 = 4'd1,`
297			`S_W2 = 4'd2,`
298			`S_W3 = 4'd3,`
299			`S_W4 = 4'd4,`
300			`S_W5 = 4'd5,`
301			`S_IDLE2 = 4'd6,`
302			`S_R1 = 4'd7,`
303			`S_R2 = 4'd8,`
304			`S_R3 = 4'd9,`
305			`S_R4 = 4'd10,`
306			`S_IDLE3 = 4'd11;`
307
308			`always @(posedge clk or negedge reset_n) begin`
309			`if(reset_n == 1'b0) begin`
310			`ssram_address <= 19'd0;`
311			`ssram_data_reg <= 36'd0;`
312			`ssram_data_oe <= 1'b0;`
313			`ssram_oe_n <= 1'b1;`
314			`ssram_writeen_n <= 1'b1;`
315			`ssram_byteen_n <= 4'b1111;`
316
317			`DAT_I <= 32'd0;`
318			`state <= S_IDLE;`
319			`end`
320			`else begin`
321			`case(state)`
322			`S_IDLE: begin`
323			`ssram_address <= 19'd0;`
324			`ssram_data_reg <= 36'd0;`
325			`ssram_data_oe <= 1'b0;`
326			`ssram_oe_n <= 1'b1;`
327			`ssram_writeen_n <= 1'b1;`
328			`ssram_byteen_n <= 4'b1111;`
329
330			`state <= S_W1;`
331			`end`
332			`S_W1: begin`
333			`// address, byte enables and write enables output`
334			`ssram_address <= 19'd0;`
335			`ssram_data_reg <= 36'd0;`
336			`ssram_data_oe <= 1'b0;`
337			`ssram_oe_n <= 1'b1;`
338			`ssram_writeen_n <= 1'b0;`
339			`ssram_byteen_n <= 4'b0000;`
340
341			`state <= S_W2;`
342			`end`
343			`S_W2: begin`
344			`// address, byte enables and write enables latched`
345			`ssram_data_reg <= { 4'b0, 32'h71000000 };`
346			`ssram_data_oe <= 1'b1;`
347
348			`ssram_address <= 19'd1;`
349
350			`state <= S_W3;`
351			`end`
352			`S_W3: begin`
353			`state <= S_W4;`
354			`end`
355			`S_W4: begin`
356			`ssram_data_reg <= { 4'b0, 32'h72000000 };`
357
358			`state <= S_IDLE2;`
359			`end`
360
361			`S_IDLE2: begin`
362			`ssram_address <= 19'd0;`
363			`ssram_data_reg <= 32'd0;`
364			`ssram_data_oe <= 1'b0;`
365			`ssram_oe_n <= 1'b1;`
366			`ssram_writeen_n <= 1'b1;`
367			`ssram_byteen_n <= 4'b1111;`
368
369			`state <= S_R1;`
370			`end`
371			`S_R1: begin`
372			`// address and byte enables output`
373			`ssram_address <= 19'd0;`
374			`ssram_data_reg <= 32'd0;`
375			`ssram_data_oe <= 1'b0;`
376			`ssram_oe_n <= 1'b1;`
377			`ssram_writeen_n <= 1'b1;`
378			`ssram_byteen_n <= 4'b0000;`
379
380			`state <= S_R2;`
381			`end`
382			`S_R2: begin`
383			`// address and byte enables latched`
384			`state <= S_R3;`
385			`end`
386			`S_R3: begin`
387			`// output enable output`
388			`ssram_oe_n <= 1'b0;`
389
390			`state <= S_R4;`
391			`end`
392			`S_R4: begin`
393			`// save data output`
394			`DAT_I <= ssram_data[31:0];`
395
396			`state <= S_IDLE3;`
397			`end`
398			`S_IDLE3: begin`
399			`ssram_address <= 19'd0;`
400			`ssram_data_reg <= 32'd0;`
401			`ssram_data_oe <= 1'b0;`
402			`ssram_oe_n <= 1'b1;`
403			`ssram_writeen_n <= 1'b1;`
404			`ssram_byteen_n <= 4'b1111;`
405			`end`
406			`endcase`
407			`end`
408			`end`
409
410			`endmodule`
411			`*/`