URL https://opencores.org/ocsvn/aor3000/aor3000/trunk

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[/] [aor3000/] [trunk/] [linux/] [arch/] [mips/] [include/] [asm/] [mach-aor3000/] [war.h] - Blame information for rev 2

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#ifndef __ASM_MACH_AOR3000_WAR_H
#define __ASM_MACH_AOR3000_WAR_H
 
#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR    0
#define R4600_V2_HIT_CACHEOP_WAR    0
#define R5432_CP0_INTERRUPT_WAR     0
#define BCM1250_M3_WAR          0
#define SIBYTE_1956_WAR         0
#define MIPS4K_ICACHE_REFILL_WAR    0
#define MIPS_CACHE_SYNC_WAR     0
#define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR   0
#define R10000_LLSC_WAR         0
#define MIPS34K_MISSED_ITLB_WAR     0
 
#endif /* __ASM_MACH_AOR3000_WAR_H */

Line No.	Rev	Author	Line
1	2	alfik	`#ifndef __ASM_MACH_AOR3000_WAR_H`
2			`#define __ASM_MACH_AOR3000_WAR_H`
3
4			`#define R4600_V1_INDEX_ICACHEOP_WAR 0`
5			`#define R4600_V1_HIT_CACHEOP_WAR 0`
6			`#define R4600_V2_HIT_CACHEOP_WAR 0`
7			`#define R5432_CP0_INTERRUPT_WAR 0`
8			`#define BCM1250_M3_WAR 0`
9			`#define SIBYTE_1956_WAR 0`
10			`#define MIPS4K_ICACHE_REFILL_WAR 0`
11			`#define MIPS_CACHE_SYNC_WAR 0`
12			`#define TX49XX_ICACHE_INDEX_INV_WAR 0`
13			`#define ICACHE_REFILLS_WORKAROUND_WAR 0`
14			`#define R10000_LLSC_WAR 0`
15			`#define MIPS34K_MISSED_ITLB_WAR 0`
16
17			`#endif /* __ASM_MACH_AOR3000_WAR_H */`

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[/] [aor3000/] [trunk/] [linux/] [arch/] [mips/] [include/] [asm/] [mach-aor3000/] [war.h] - Blame information for rev 2