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/*

 * This file is subject to the terms and conditions of the BSD License. See

 * the file "LICENSE" in the main directory of this archive for more details.

 *

 * Copyright (C) 2014 Aleksander Osman

 */

`include "defines.v"

module pipeline_mem(

    input               clk,

    input               rst_n,

    //

    input       [5:0]   interrupt_vector,

    //

    output              mem_stall,

    //

    output              config_kernel_mode,

    output              config_switch_caches,

    //

    input       [6:0]   exe_cmd,

    input       [31:0]  exe_instr,

    input       [31:0]  exe_pc_plus4,

    input               exe_pc_user_seg,

    input       [31:0]  exe_badvpn,

    input       [31:0]  exe_a,

    input       [31:0]  exe_b,

    input       [1:0]   exe_branched,

    input       [31:0]  exe_branch_address,

    input               exe_cmd_cp0,

    input               exe_cmd_load,

    input               exe_cmd_store,

    //

    input       [4:0]   exe_result_index,

    input       [31:0]  exe_result,

    //

    output reg  [4:0]   mem_result_index,

    output      [31:0]  mem_result,

    //

    output      [4:0]   muldiv_result_index,

    output      [31:0]  muldiv_result,

    //

    output              tlb_ram_read_do,

    output      [5:0]   tlb_ram_read_index,

    input               tlb_ram_read_result_ready,

    input       [49:0]  tlb_ram_read_result,

    //

    output              tlb_ram_write_do,

    output      [5:0]   tlb_ram_write_index,

    output      [49:0]  tlb_ram_write_value,

    //

    output              tlb_ram_data_start,

    output      [19:0]  tlb_ram_data_vpn,

    input               tlb_ram_data_hit,

    input       [5:0]   tlb_ram_data_index,

    input       [49:0]  tlb_ram_data_result,

    input               tlb_ram_data_missed,

    //

    output              exception_start,

    output      [31:0]  exception_start_pc,

    //

    output              micro_flush_do,

    output      [5:0]   entryhi_asid,

    //

    input       [31:0]  data_address_next,

    input       [31:0]  data_address,

    //

    output      [8:0]   data_cache_read_address,

    input       [53:0]  data_cache_q,

    output      [8:0]   data_cache_write_address,

    output              data_cache_write_enable,

    output      [53:0]  data_cache_data,

    //

    output              ram_fifo_wrreq,

    output      [66:0]  ram_fifo_data,

    input               ram_fifo_full,

    //

    input       [31:0]  ram_result_address,

    input               ram_result_valid,

    input               ram_result_is_read_instr,

    input       [2:0]   ram_result_burstcount,

    input       [31:0]  ram_result

); /* verilator public_module */

//------------------------------------------------------------------------------ pipeline stall

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

assign mem_stall = ~(exception_start) && (

    muldiv_busy ||

    exe_cmd_tlbp || (tlbp_in_progress && ~(tlbp_update)) ||

    load_idle_tlb_ok_cache_bad_fifo_ok || load_idle_tlb_ok_cache_bad_fifo_bad || load_idle_tlb_wait || load_state != LOAD_IDLE ||

    store_idle_tlb_ok_fifo_bad || store_idle_tlb_wait || store_state != STORE_IDLE

);

reg mem_stalled;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   mem_stalled <= `FALSE;

    else                mem_stalled <= mem_stall;

end

//------------------------------------------------------------------------------ instruction decoding

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

wire [4:0] exe_instr_rt = exe_instr[20:16];

wire [4:0] exe_instr_rd = exe_instr[15:11];

wire mem_exc_coproc0_unusable = ~(config_coproc0_usable) && ~(config_kernel_mode) && exe_cmd_cp0;

wire exe_cmd_mtc0  = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_mtc0;

wire exe_cmd_rfe   = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_cp0_rfe;

wire exe_cmd_tlbr  = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_cp0_tlbr;

wire exe_cmd_tlbp  = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_cp0_tlbp;

wire exe_cmd_tlbwi = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_cp0_tlbwi;

wire exe_cmd_tlbwr = ~(mem_exc_coproc0_unusable) && ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd == `CMD_cp0_tlbwr;

wire exe_cmd_load_do  = ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd_load;

wire exe_cmd_store_do = ~(exception_start) && ~(config_kernel_mode_exc_now) && exe_cmd_store;

//------------------------------------------------------------------------------ next pipeline stage

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

reg config_kernel_mode_last;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   config_kernel_mode_last <= `TRUE;

    else                config_kernel_mode_last <= config_kernel_mode;

end

reg config_kernel_mode_changed;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)                       config_kernel_mode_changed <= `FALSE;

    else if(config_kernel_mode)             config_kernel_mode_changed <= `FALSE;

    else if(config_kernel_mode_exc_wait)    config_kernel_mode_changed <= `TRUE;

    else if(exe_cmd != `CMD_null)           config_kernel_mode_changed <= `FALSE;

end

wire config_kernel_mode_exc_now  = (config_kernel_mode_changed || (config_kernel_mode_last && ~(config_kernel_mode))) && exe_cmd != `CMD_null && exe_pc_user_seg;

wire config_kernel_mode_exc_wait = ~(config_kernel_mode_changed) && config_kernel_mode_last && ~(config_kernel_mode) && exe_cmd == `CMD_null;

//------------------------------------------------------------------------------

wire [4:0] mem_result_index_next =

    (exception_start || config_kernel_mode_exc_now)?        5'd0 :

    (exe_cmd == `CMD_cfc1_detect && config_coproc1_usable)? exe_instr_rt :

    (data_finished && load_idle_tlb_ok_finished)?           exe_instr_rt :

    (data_finished)?                                        load_instr_rt_reg :

    (muldiv_result_index != 5'd0)?                          muldiv_result_index :

    (exe_cmd == `CMD_mfc0 && ~(mem_exc_coproc0_unusable))?  exe_instr_rt :

                                                            exe_result_index;

wire [31:0] mem_result_next =

    (exe_cmd == `CMD_cfc1_detect && config_coproc1_usable)? 32'd0 :

    (muldiv_result_index != 5'd0)?                          muldiv_result :

    (exe_cmd == `CMD_mfc0 && ~(mem_exc_coproc0_unusable))?  coproc0_output :

                                                            exe_result;

wire [6:0] mem_cmd_next =

    (exception_start)?                                                                                                          `CMD_null :

    (config_kernel_mode_exc_now)?                                                                                               `CMD_exc_load_addr_err :

    (exe_cmd == `CMD_cfc1_detect && ~(config_coproc1_usable))?                                                                  `CMD_exc_coproc_unusable :

    (mem_exc_coproc0_unusable)?                                                                                                 `CMD_exc_coproc_unusable :

    (store_idle_tlb_bad_exc_modif || store_tlb_tlb_bad_exc_modif)?                                                              `CMD_exc_tlb_modif :

    (load_idle_tlb_bad_exc_inv || load_tlb_tlb_bad_exc_inv || (load_tlb_tlb_bad_exc_miss && data_address_reg[31] == 1'b1))?     `CMD_exc_load_tlb :

    (store_idle_tlb_bad_exc_inv || store_tlb_tlb_bad_exc_inv || (store_tlb_tlb_bad_exc_miss && data_address_reg[31] == 1'b1))?  `CMD_exc_store_tlb :

    (load_tlb_tlb_bad_exc_miss  && data_address_reg[31] == 1'b0)?                                                               `CMD_exc_tlb_load_miss :

    (store_tlb_tlb_bad_exc_miss && data_address_reg[31] == 1'b0)?                                                               `CMD_exc_tlb_store_miss :

                                                                                                                                exe_cmd;

wire [31:0] mem_badvpn_next =

    (exe_cmd_load_do || exe_cmd_store_do)?                      { data_address[31:2],     ((exe_instr[27:26] == 2'b10)? 2'b00 : data_address[1:0]) } :

    (load_state != LOAD_IDLE || store_state != STORE_IDLE)?     { data_address_reg[31:2], ((mem_left_right   == 2'b10)? 2'b00 : data_address_reg[1:0]) } :

                                                                exe_badvpn;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   mem_result_index <= 5'd0;

    else                mem_result_index <= mem_result_index_next;

end

reg [31:0] mem_result_nodata;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   mem_result_nodata <= 32'd0;

    else                mem_result_nodata <= mem_result_next;

end

reg [31:0] mem_result_data;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   mem_result_data <= 32'd0;

    else                mem_result_data <= data_finished_value;

end

reg mem_data_finished;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   mem_data_finished <= `FALSE;

    else                mem_data_finished <= data_finished;

end

assign mem_result = (mem_data_finished)? mem_result_data : mem_result_nodata;

//------------------------------------------------------------------------------

reg [6:0] mem_cmd;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   mem_cmd <= `CMD_null;

    else                mem_cmd <= mem_cmd_next;

end

reg [31:0] mem_branch_address;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   mem_branch_address <= 32'd0;

    else                mem_branch_address <= exe_branch_address;

end

reg [31:0] mem_instr;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   mem_instr <= 32'd0;

    else                mem_instr <= exe_instr;

end

reg [31:0] mem_badvpn;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)   mem_badvpn <= 32'd0;

    else                mem_badvpn <= mem_badvpn_next;

end

reg [1:0] mem_branched;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)       mem_branched <= 2'd0;

    else if(~(mem_stalled)) mem_branched <= exe_branched;

end

reg [31:0] mem_pc_plus4;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)       mem_pc_plus4 <= 32'd0;

    else if(~(mem_stalled)) mem_pc_plus4 <= exe_pc_plus4;

end

//------------------------------------------------------------------------------ tlb

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

//input               tlb_ram_data_hit,

//input       [5:0]   tlb_ram_data_index,

//input       [49:0]  tlb_ram_data_result,

//input               tlb_ram_data_missed

assign tlb_ram_write_do    = exe_cmd_tlbwi || exe_cmd_tlbwr;

assign tlb_ram_write_index = tlbw_index;

assign tlb_ram_write_value = tlbw_value;

assign tlb_ram_read_do    = exe_cmd_tlbr;

assign tlb_ram_read_index = tlbr_index;

assign tlb_ram_data_start = exe_cmd_tlbp || exe_cmd_load_do || exe_cmd_store_do;

assign tlb_ram_data_vpn =

    (exe_cmd_tlbp || tlbp_in_progress)?     tlbw_value[19:0] :

    (exe_cmd_load_do || exe_cmd_store_do)?  data_address[31:12] :

                                            data_address_reg[31:12];

//------------------------------------------------------------------------------ tlb probe

reg tlbp_in_progress;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)       tlbp_in_progress <= `FALSE;

    else if(exe_cmd_tlbp)   tlbp_in_progress <= `TRUE;

    else if(tlbp_update)    tlbp_in_progress <= `FALSE;

end

wire       tlbp_update = tlbp_in_progress && (tlb_ram_data_hit || tlb_ram_data_missed);

wire       tlbp_hit    = tlb_ram_data_hit;

wire [5:0] tlbp_index  = tlb_ram_data_index;

//------------------------------------------------------------------------------ load / store common

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

wire tlb_use_at_idle = (exe_cmd_load_do || exe_cmd_store_do) && (data_address[31] == 1'b0 || data_address[31:30] == 2'b11);

wire [19:0] pfn_at_idle =

    (~(tlb_use_at_idle))?   { 3'b0, data_address[28:12] } :

    (micro_check_matched)?  micro_check_result[39:20] :

                            tlb_ram_data_result[39:20];

reg [19:0] pfn_reg;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)                                       pfn_reg <= 20'd0;

    else if(exe_cmd_load_do || exe_cmd_store_do)            pfn_reg <= pfn_at_idle;

    else if(load_tlb_tlb_ok_cache_bad || store_tlb_tlb_ok)  pfn_reg <= tlb_ram_data_result[39:20];

end

wire n_at_idle =

    (~(tlb_use_at_idle))?   data_address[31:29] == 3'b101 :

    (micro_check_matched)?  micro_check_result[46] :

                            tlb_ram_data_result[46];

reg n_reg;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)                                       n_reg <= `FALSE;

    else if(exe_cmd_load_do || exe_cmd_store_do)            n_reg <= n_at_idle;

    else if(load_tlb_tlb_ok_cache_bad || store_tlb_tlb_ok)  n_reg <= tlb_ram_data_result[46];

end

wire [3:0] byte_byteenable =

    (data_address[1:0] == 2'b00)?   4'b0001 :

    (data_address[1:0] == 2'b01)?   4'b0010 :

    (data_address[1:0] == 2'b10)?   4'b0100 :

                                    4'b1000;

wire [3:0] halfword_byteenable =

    (data_address[1:0] == 2'b00)?   4'b0011 :

                                    4'b1100;

wire [3:0] lwl_byteenable =

    (data_address[1:0] == 2'b00)?   4'b0001 :

    (data_address[1:0] == 2'b01)?   4'b0011 :

    (data_address[1:0] == 2'b10)?   4'b0111 :

                                    4'b1111;

wire [3:0] lwr_byteenable =

    (data_address[1:0] == 2'b00)?   4'b1111 :

    (data_address[1:0] == 2'b01)?   4'b1110 :

    (data_address[1:0] == 2'b10)?   4'b1100 :

                                    4'b1000;

wire [3:0] data_byteenable =

    (load_idle_cmd_lb || load_idle_cmd_lbu || load_idle_cmd_sb)?    byte_byteenable :

    (load_idle_cmd_lh || load_idle_cmd_lhu || load_idle_cmd_sh)?    halfword_byteenable :

    (load_idle_cmd_lwl || load_idle_cmd_swl)?                       lwl_byteenable :

    (load_idle_cmd_lwr || load_idle_cmd_swr)?                       lwr_byteenable :

                                                                    4'b1111;

reg [3:0] data_byteenable_reg;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)           data_byteenable_reg <= 4'b0;

    else if(exe_cmd_load_do)    data_byteenable_reg <= load_idle_byteenable;

    else if(exe_cmd_store_do)   data_byteenable_reg <= data_byteenable;

end

reg [53:0] data_cache_q_reg;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)           data_cache_q_reg <= 54'd0;

    else if(exe_cmd_load_do)    data_cache_q_reg <= data_cache_q;

    else if(exe_cmd_store_do)   data_cache_q_reg <= { data_cache_q[53:32], store_idle_data };

end

reg [31:0] data_address_reg;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)                             data_address_reg <= 32'b0;

    else if(exe_cmd_load_do || exe_cmd_store_do)  data_address_reg <= data_address;

end

reg [1:0] mem_left_right;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)                             mem_left_right <= 2'b0;

    else if(exe_cmd_load_do || exe_cmd_store_do)  mem_left_right <= exe_instr[27:26];

end

//------------------------------------------------------------------------------ load

//------------------------------------------------------------------------------

//------------------------------------------------------------------------------

localparam [1:0] LOAD_IDLE   = 2'd0;

localparam [1:0] LOAD_TLB    = 2'd1;

localparam [1:0] LOAD_FIFO   = 2'd2;

localparam [1:0] LOAD_RESULT = 2'd3;

reg [1:0] load_state;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)                                                                                                       load_state <= LOAD_IDLE;

    else if(load_idle_tlb_ok_cache_bad_fifo_ok)                                                                             load_state <= LOAD_RESULT;

    else if(load_idle_tlb_ok_cache_bad_fifo_bad)                                                                            load_state <= LOAD_FIFO;

    else if(load_idle_tlb_wait)                                                                                             load_state <= LOAD_TLB;

    else if(load_tlb_tlb_ok_finished)                                                                                       load_state <= LOAD_IDLE;

    else if(load_tlb_tlb_bad_exc_inv || load_tlb_tlb_bad_exc_miss)                                                          load_state <= LOAD_IDLE;

    else if(load_tlb_tlb_ok_cache_bad_fifo_ok)                                                                              load_state <= LOAD_RESULT;

    else if(load_tlb_tlb_ok_cache_bad_fifo_bad)                                                                             load_state <= LOAD_FIFO;

    else if(load_fifo_end)                                                                                                  load_state <= LOAD_RESULT;

    else if(load_state == LOAD_RESULT && ram_result_valid && ~(ram_result_is_read_instr) && ram_result_burstcount == 3'd1)  load_state <= LOAD_IDLE;

end

wire sr_cm_clear = config_isolate_cache && (load_idle_tlb_ok_cache_ok || load_tlb_tlb_ok_cache_ok);

wire sr_cm_set   = config_isolate_cache && (load_idle_tlb_ok_cache_isolate || load_tlb_tlb_ok_cache_isolate);

wire        data_finished       = load_idle_tlb_ok_finished || load_tlb_tlb_ok_finished || (ram_result_valid && ~(ram_result_is_read_instr) && ram_result_address[31:2] == { pfn_reg, data_address_reg[11:2] });

wire [31:0] data_finished_value = (load_idle_tlb_ok_finished)? load_idle_result[31:0] : load_result_value;

//------------------------------------------------------------------------------ state IDLE

wire load_idle_cmd_lb  = exe_instr[28:26] == 3'b000;

wire load_idle_cmd_lbu = exe_instr[28:26] == 3'b100;

wire load_idle_cmd_lh  = exe_instr[28:26] == 3'b001;

wire load_idle_cmd_lhu = exe_instr[28:26] == 3'b101;

wire load_idle_cmd_lw  = exe_instr[28:26] == 3'b011;

wire load_idle_cmd_lwl = exe_instr[28:26] == 3'b010;

wire load_idle_cmd_lwr = exe_instr[28:26] == 3'b110;

wire load_idle_cmd_sb  = exe_instr[28:26] == 3'b000;

wire load_idle_cmd_sh  = exe_instr[28:26] == 3'b001;

//not used: wire load_idle_cmd_sw  = exe_instr[28:26] == 3'b011;

wire load_idle_cmd_swl = exe_instr[28:26] == 3'b010;

wire load_idle_cmd_swr = exe_instr[28:26] == 3'b110;

wire [31:0] load_idle_rt = (exe_instr_rt == mem_result_index)?  mem_result : exe_b;

wire [7:0] load_idle_byte =

    (data_address[1:0] == 2'd0)?    data_cache_q[7:0] :

    (data_address[1:0] == 2'd1)?    data_cache_q[15:8] :

    (data_address[1:0] == 2'd2)?    data_cache_q[23:16] :

                                    data_cache_q[31:24];

wire [15:0] load_idle_halfword =

    (data_address[1:0] == 2'd0)?    data_cache_q[15:0] :

                                    data_cache_q[31:16];

wire [31:0] load_idle_lwl =

    (data_address[1:0] == 2'd0)?    { data_cache_q[7:0],  load_idle_rt[23:0] } :

    (data_address[1:0] == 2'd1)?    { data_cache_q[15:0], load_idle_rt[15:0] } :

    (data_address[1:0] == 2'd2)?    { data_cache_q[23:0], load_idle_rt[7:0] } :

                                    data_cache_q[31:0];

wire [31:0] load_idle_lwr =

    (data_address[1:0] == 2'd0)?    data_cache_q[31:0] :

    (data_address[1:0] == 2'd1)?    { load_idle_rt[31:24], data_cache_q[31:8] } :

    (data_address[1:0] == 2'd2)?    { load_idle_rt[31:16], data_cache_q[31:16] } :

                                    { load_idle_rt[31:8],  data_cache_q[31:24] };

wire [31:0] load_idle_result =

    (load_idle_cmd_lb)?     { {24{load_idle_byte[7]}}, load_idle_byte } :

    (load_idle_cmd_lbu)?    { 24'd0, load_idle_byte } :

    (load_idle_cmd_lh)?     { {16{load_idle_halfword[15]}}, load_idle_halfword } :

    (load_idle_cmd_lhu)?    { 16'd0, load_idle_halfword } :

    (load_idle_cmd_lw)?     data_cache_q[31:0] :

    (load_idle_cmd_lwl)?    load_idle_lwl :

                            load_idle_lwr;

wire [3:0] load_idle_byteenable = (~(n_at_idle))? 4'hF : data_byteenable;

reg [2:0] load_cmd_reg;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)           load_cmd_reg <= 3'b0;

    else if(exe_cmd_load_do)    load_cmd_reg <= exe_instr[28:26];

end

reg [4:0] load_instr_rt_reg;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)           load_instr_rt_reg <= 5'b0;

    else if(exe_cmd_load_do)    load_instr_rt_reg <= exe_instr_rt;

end

reg [31:0] load_rt_reg;

always @(posedge clk or negedge rst_n) begin

    if(rst_n == 1'b0)           load_rt_reg <= 32'd0;

    else if(exe_cmd_load_do)    load_rt_reg <= load_idle_rt;

end

wire load_idle_tlb_ok_cache_ok = exe_cmd_load_do && data_cache_q[53] && ~(n_at_idle) && (

    (~(tlb_use_at_idle) && data_cache_q[52:32] == { pfn_at_idle, data_address[11] }) ||                                                        //tlb not in use

    (tlb_use_at_idle && micro_check_matched && micro_check_result[48] && data_cache_q[52:32] == {micro_check_result[39:20], data_address[11]}) //tlb in micro

);

wire load_idle_tlb_ok_cache_isolate = exe_cmd_load_do && config_isolate_cache && (

    ~(tlb_use_at_idle) ||                                               //tlb not in use

    (tlb_use_at_idle && micro_check_matched && micro_check_result[48])  //tlb in micro

);

wire load_idle_tlb_ok_finished = load_idle_tlb_ok_cache_ok || load_idle_tlb_ok_cache_isolate;

wire load_idle_tlb_bad_exc_inv = exe_cmd_load_do && tlb_use_at_idle && (

    (micro_check_matched && ~(micro_check_result[48])) //tlb in micro

);

wire load_idle_tlb_ok_cache_bad = exe_cmd_load_do && (

    (~(tlb_use_at_idle) && (~(data_cache_q[53]) || n_at_idle || data_cache_q[52:32] != { pfn_at_idle, data_address[11] })) ||                                                          //tlb not in use

    (tlb_use_at_idle && micro_check_matched && micro_check_result[48] && (~(data_cache_q[53]) || n_at_idle || data_cache_q[52:32] != { micro_check_result[39:20], data_address[11] })) //tlb in micro

);

wire load_idle_tlb_ok_cache_bad_fifo_ok  = load_idle_tlb_ok_cache_bad && ~(ram_fifo_full);

wire load_idle_tlb_ok_cache_bad_fifo_bad = load_idle_tlb_ok_cache_bad && ram_fifo_full;

wire load_idle_tlb_wait = exe_cmd_load_do && tlb_use_at_idle && ~(micro_check_matched);

//------------------------------------------------------------------------------ state TLB

wire load_tlb_tlb_ok_cache_ok      = load_state == LOAD_TLB && tlb_ram_data_hit && tlb_ram_data_result[48] && data_cache_q_reg[53] && data_cache_q_reg[52:32] == { tlb_ram_data_result[39:20], data_address_reg[11] };

wire load_tlb_tlb_ok_cache_isolate = load_state == LOAD_TLB && tlb_ram_data_hit && tlb_ram_data_result[48] && config_isolate_cache;

wire load_tlb_tlb_ok_finished = load_tlb_tlb_ok_cache_ok || load_tlb_tlb_ok_cache_isolate;

wire load_tlb_tlb_bad_exc_inv = load_state == LOAD_TLB && tlb_ram_data_hit && ~(tlb_ram_data_result[48]);

wire load_tlb_tlb_bad_exc_miss= load_state == LOAD_TLB && ~(tlb_ram_data_hit) && tlb_ram_data_missed;

wire load_tlb_tlb_ok_cache_bad =

    load_state == LOAD_TLB && tlb_ram_data_hit && tlb_ram_data_result[48] && (~(data_cache_q_reg[53]) || data_cache_q_reg[52:32] != { tlb_ram_data_result[39:20], data_address_reg[11] });

wire load_tlb_tlb_ok_cache_bad_fifo_ok  = load_tlb_tlb_ok_cache_bad && ~(ram_fifo_full);

wire load_tlb_tlb_ok_cache_bad_fifo_bad = load_tlb_tlb_ok_cache_bad && ram_fifo_full;

//------------------------------------------------------------------------------ state FIFO

wire load_fifo_end = load_state == LOAD_FIFO && ~(ram_fifo_full);

//------------------------------------------------------------------------------ state TLB or RESULT

wire load_result_cmd_lb  = load_cmd_reg == 3'b000;

wire load_result_cmd_lbu = load_cmd_reg == 3'b100;

wire load_result_cmd_lh  = load_cmd_reg == 3'b001;

wire load_result_cmd_lhu = load_cmd_reg == 3'b101;

wire load_result_cmd_lw  = load_cmd_reg == 3'b011;

wire load_result_cmd_lwl = load_cmd_reg == 3'b010;