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[/] [aor3000/] [trunk/] [sim/] [aoR3000/] [main_tester.cpp] - Blame information for rev 2

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1 2 alfik 
/*
2 
 * This file is subject to the terms and conditions of the BSD License. See
3 
 * the file "LICENSE" in the main directory of this archive for more details.
4 
 *
5 
 * Copyright (C) 2014 Aleksander Osman
6 
 */
7 
 
8 
#include <cstdio>
9 
#include <cstdlib>
10 
 
11 
#include <sys/mman.h>
12 
#include <sys/types.h>
13 
#include <sys/stat.h>
14 
#include <fcntl.h>
15 
#include <unistd.h>
16 
 
17 
#include "VaoR3000.h"
18 
#include "VaoR3000_aoR3000.h"
19 
#include "VaoR3000_pipeline_rf.h"
20 
#include "VaoR3000_pipeline_if.h"
21 
#include "VaoR3000_pipeline_mem.h"
22 
#include "VaoR3000_block_muldiv.h"
23 
#include "VaoR3000_memory_tlb_ram.h"
24 
#include "VaoR3000_block_cp0.h"
25 
#include "VaoR3000_pipeline_exe.h"
26 
#include "VaoR3000_model_true_dual_ram__W32_WB4.h"
27 
#include "VaoR3000_model_simple_dual_ram__W20_WB5.h"
28 
 
29 
#include "verilated.h"
30 
#include "verilated_vcd_c.h"
31 
 
32 
#include "shared_mem.h"
33 
 
34 
//------------------------------------------------------------------------------
35 
 
36 
volatile shared_mem_t *shared_ptr = NULL;
37 
 
38 
//------------------------------------------------------------------------------
39 
 
40 
#define GET(field, mask) \
41 
    (shared_ptr->initial.field & mask)
42 
 
43 
void initialize(VaoR3000 *top) {
44 
 
45 
    top->v->pipeline_rf_inst->regs_a_inst->__PVT__mem[0] = top->v->pipeline_rf_inst->regs_b_inst->__PVT__mem[0] = 0;
46 
    for(int i=1; i<32; i++) top->v->pipeline_rf_inst->regs_a_inst->__PVT__mem[i] = top->v->pipeline_rf_inst->regs_b_inst->__PVT__mem[i] = GET(reg[i-1], 0xFFFFFFFF);
47 
 
48 
    top->v->pipeline_if_inst->__PVT__exc_start_pc           = GET(pc, 0xFFFFFFFF);
49 
    //not compared: top->v->pipeline_mem_inst->block_muldiv_inst->__PVT__hi = GET(hi, 0xFFFFFFFF);
50 
    //not compared: top->v->pipeline_mem_inst->block_muldiv_inst->__PVT__lo = GET(lo, 0xFFFFFFFF);
51 
 
52 
    for(int i=0; i<64; i++) {
53 
/*
54 
[19:0]  vpn
55 
[39:20] pfn
56 
[45:40] asid
57 
[46]    n noncachable
58 
[47]    d dirty = write-enable
59 
[48]    v valid
60 
[49]    g global
61 
*/
62 
        uint64 entry = 0;
63 
        entry |= (uint64)(GET(tlb[i].vpn, 0xFFFFF)) << 0;
64 
        entry |= (uint64)(GET(tlb[i].asid, 0x3F))   << 40;
65 
        entry |= (uint64)(GET(tlb[i].pfn, 0xFFFFF)) << 20;
66 
        entry |= (uint64)(GET(tlb[i].n,   0x1))     << 46;
67 
        entry |= (uint64)(GET(tlb[i].d,   0x1))     << 47;
68 
        entry |= (uint64)(GET(tlb[i].v,   0x1))     << 48;
69 
        entry |= (uint64)(GET(tlb[i].g,   0x1))     << 49;
70 
 
71 
        if((i % 8) == 0) top->v->memory_tlb_ram_inst->tlb0_inst->__PVT__mem[i/8]     = entry;
72 
        if((i % 8) == 1) top->v->memory_tlb_ram_inst->tlb0_inst->__PVT__mem[8+(i/8)] = entry;
73 
        if((i % 8) == 2) top->v->memory_tlb_ram_inst->tlb1_inst->__PVT__mem[i/8]     = entry;
74 
        if((i % 8) == 3) top->v->memory_tlb_ram_inst->tlb1_inst->__PVT__mem[8+(i/8)] = entry;
75 
        if((i % 8) == 4) top->v->memory_tlb_ram_inst->tlb2_inst->__PVT__mem[i/8]     = entry;
76 
        if((i % 8) == 5) top->v->memory_tlb_ram_inst->tlb2_inst->__PVT__mem[8+(i/8)] = entry;
77 
        if((i % 8) == 6) top->v->memory_tlb_ram_inst->tlb3_inst->__PVT__mem[i/8]     = entry;
78 
        if((i % 8) == 7) top->v->memory_tlb_ram_inst->tlb3_inst->__PVT__mem[8+(i/8)] = entry;
79 
    }
80 
 
81 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__tlb_probe   = GET(index_p, 0x1);
82 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__tlbr_index  = GET(index_index, 0x3F);
83 
 
84 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__tlb_random  = GET(random, 0x3F);
85 
 
86 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_pfn = GET(entrylo_pfn, 0xFFFFF);
87 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_n   = GET(entrylo_n,   0x1);
88 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_d   = GET(entrylo_d,   0x1);
89 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_v   = GET(entrylo_v,   0x1);
90 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_g   = GET(entrylo_g,   0x1);
91 
 
92 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__tlb_ptebase = GET(context_ptebase, 0x7FF);
93 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__tlb_badvpn  = GET(context_badvpn,  0x7FFFF);
94 
 
95 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__badvaddr    = GET(bad_vaddr, 0xFFFFFFFF);
96 
 
97 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entryhi_vpn  = GET(entryhi_vpn, 0xFFFFF);
98 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entryhi_asid = GET(entryhi_asid, 0x3F);
99 
 
100 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_coproc_usable     = GET(sr_cp_usable,     0xF);
101 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_reverse_endian    = GET(sr_rev_endian,    0x1);
102 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_bev               = GET(sr_bootstrap_vec, 0x1);
103 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_tlb_shutdown      = GET(sr_tlb_shutdown,  0x1);
104 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_parity_error      = GET(sr_parity_err,    0x1);
105 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_cm                = GET(sr_cache_miss,    0x1);
106 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_parity_zero       = GET(sr_parity_zero,   0x1);
107 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__config_switch_caches = GET(sr_switch_cache,  0x1);
108 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__config_isolate_cache = GET(sr_isolate_cache, 0x1);
109 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_im                = GET(sr_irq_mask,      0xFF);
110 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_ku_ie             = GET(sr_ku_ie,         0x3F);
111 
 
112 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__cause_bd          = GET(cause_branch_delay, 0x1);
113 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__cause_ce          = GET(cause_cp_error,     0x3);
114 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__cause_ip_writable = GET(cause_irq_pending,  0x3); //only 2 lowest bits
115 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__cause_exccode     = GET(cause_exc_code,     0x1F);
116 
 
117 
    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__epc = GET(epc, 0xFFFFFFFF);
118 
}
119 
 
120 
//------------------------------------------------------------------------------
121 
 
122 
#define PUT(field, val, mask) \
123 
    shared_ptr->proc_ao.report.state.field = (val) & mask
124 
 
125 
void report(VaoR3000 *top, bool is_cp0_update, bool is_tlbr) {
126 
 
127 
    for(int i=1; i<32; i++) PUT(reg[i-1], top->v->pipeline_rf_inst->regs_a_inst->__PVT__mem[i], 0xFFFFFFFF);
128 
 
129 
    PUT(pc, top->v->pipeline_if_inst->__PVT__if_pc,                  0xFFFFFFFF);
130 
    //not compared: PUT(hi, top->v->pipeline_mem_inst->block_muldiv_inst->__PVT__hi, 0xFFFFFFFF);
131 
    //not compared: PUT(lo, top->v->pipeline_mem_inst->block_muldiv_inst->__PVT__lo, 0xFFFFFFFF);
132 
 
133 
    if(is_tlbr) {
134 
        PUT(entrylo_pfn, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_pfn, 0xFFFFF);
135 
        PUT(entrylo_n,   top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_n,   0x1);
136 
        PUT(entrylo_d,   top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_d,   0x1);
137 
        PUT(entrylo_v,   top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_v,   0x1);
138 
        PUT(entrylo_g,   top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_g,   0x1);
139 
 
140 
        PUT(entryhi_vpn,  top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entryhi_vpn,  0xFFFFF);
141 
        PUT(entryhi_asid, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entryhi_asid, 0x3F);
142 
    }
143 
 
144 
    if(is_cp0_update == false) return;
145 
 
146 
    for(int i=0; i<64; i++) {
147 
        uint64 entry = 0;
148 
        if((i % 8) == 0) entry = top->v->memory_tlb_ram_inst->tlb0_inst->__PVT__mem[i/8];
149 
        if((i % 8) == 1) entry = top->v->memory_tlb_ram_inst->tlb0_inst->__PVT__mem[8+(i/8)];
150 
        if((i % 8) == 2) entry = top->v->memory_tlb_ram_inst->tlb1_inst->__PVT__mem[i/8];
151 
        if((i % 8) == 3) entry = top->v->memory_tlb_ram_inst->tlb1_inst->__PVT__mem[8+(i/8)];
152 
        if((i % 8) == 4) entry = top->v->memory_tlb_ram_inst->tlb2_inst->__PVT__mem[i/8];
153 
        if((i % 8) == 5) entry = top->v->memory_tlb_ram_inst->tlb2_inst->__PVT__mem[8+(i/8)];
154 
        if((i % 8) == 6) entry = top->v->memory_tlb_ram_inst->tlb3_inst->__PVT__mem[i/8];
155 
        if((i % 8) == 7) entry = top->v->memory_tlb_ram_inst->tlb3_inst->__PVT__mem[8+(i/8)];
156 
/*
157 
[19:0]  vpn
158 
[39:20] pfn
159 
[45:40] asid
160 
[46]    n noncachable
161 
[47]    d dirty = write-enable
162 
[48]    v valid
163 
[49]    g global
164 
*/
165 
        PUT(tlb[i].vpn,  entry >> 0,  0xFFFFF);
166 
        PUT(tlb[i].asid, entry >> 40, 0x3F);
167 
 
168 
        PUT(tlb[i].pfn,  entry >> 20, 0xFFFFF);
169 
        PUT(tlb[i].n,    entry >> 46, 0x1);
170 
        PUT(tlb[i].d,    entry >> 47, 0x1);
171 
        PUT(tlb[i].v,    entry >> 48, 0x1);
172 
        PUT(tlb[i].g,    entry >> 49, 0x1);
173 
    }
174 
 
175 
    PUT(index_p,     top->v->pipeline_mem_inst->block_cp0_inst->__PVT__tlb_probe,  0x1);
176 
    PUT(index_index, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__tlbr_index, 0x3F);
177 
 
178 
    PUT(random, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__tlb_random, 0x3F);
179 
 
180 
    PUT(entrylo_pfn, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_pfn, 0xFFFFF);
181 
    PUT(entrylo_n,   top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_n,   0x1);
182 
    PUT(entrylo_d,   top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_d,   0x1);
183 
    PUT(entrylo_v,   top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_v,   0x1);
184 
    PUT(entrylo_g,   top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entrylo_g,   0x1);
185 
 
186 
    PUT(context_ptebase, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__tlb_ptebase, 0x7FF);
187 
    PUT(context_badvpn,  top->v->pipeline_mem_inst->block_cp0_inst->__PVT__tlb_badvpn,  0x7FFFF);
188 
 
189 
    PUT(bad_vaddr, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__badvaddr, 0xFFFFFFFF);
190 
 
191 
    PUT(entryhi_vpn,  top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entryhi_vpn,  0xFFFFF);
192 
    PUT(entryhi_asid, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__entryhi_asid, 0x3F);
193 
 
194 
    PUT(sr_cp_usable,     top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_coproc_usable,     0xF);
195 
    PUT(sr_rev_endian,    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_reverse_endian,    0x1);
196 
    PUT(sr_bootstrap_vec, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_bev,               0x1);
197 
    PUT(sr_tlb_shutdown,  top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_tlb_shutdown,      0x1);
198 
    PUT(sr_parity_err,    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_parity_error,      0x1);
199 
    PUT(sr_cache_miss,    top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_cm,                0x1);
200 
    PUT(sr_parity_zero,   top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_parity_zero,       0x1);
201 
    PUT(sr_switch_cache,  top->v->pipeline_mem_inst->block_cp0_inst->__PVT__config_switch_caches, 0x1);
202 
    PUT(sr_isolate_cache, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__config_isolate_cache, 0x1);
203 
    PUT(sr_irq_mask,      top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_im,                0xFF);
204 
    PUT(sr_ku_ie,         top->v->pipeline_mem_inst->block_cp0_inst->__PVT__sr_ku_ie,             0x3F);
205 
 
206 
    PUT(cause_branch_delay, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__cause_bd,          0x1);
207 
    PUT(cause_cp_error,     top->v->pipeline_mem_inst->block_cp0_inst->__PVT__cause_ce,          0x3);
208 
    PUT(cause_irq_pending,  top->v->pipeline_mem_inst->block_cp0_inst->__PVT__cause_ip_writable, 0x3); //only 2 lowest bits
209 
    PUT(cause_exc_code,     top->v->pipeline_mem_inst->block_cp0_inst->__PVT__cause_exccode,     0x1F);
210 
 
211 
    PUT(epc, top->v->pipeline_mem_inst->block_cp0_inst->__PVT__epc, 0xFFFFFFFF);
212 
}
213 
 
214 
//------------------------------------------------------------------------------
215 
 
216 
void usleep_or_finish() {
217 
    if(shared_ptr->test_finished) {
218 
        printf("Finishing.\n");
219 
        exit(0);
220 
    }
221 
    usleep(1);
222 
}
223 
 
224 
//------------------------------------------------------------------------------
225 
 
226 
int main(int argc, char **argv) {
227 
 
228 
    //map shared memory
229 
    int fd = open("./../tester/shared_mem.dat", O_RDWR, S_IRUSR | S_IWUSR);
230 
 
231 
    if(fd == -1) {
232 
        perror("open() failed for shared_mem.dat");
233 
        return -1;
234 
    }
235 
 
236 
    shared_ptr = (shared_mem_t *)mmap(NULL, sizeof(shared_mem_t), PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
237 
 
238 
    if(shared_ptr == MAP_FAILED) {
239 
        perror("mmap() failed");
240 
        close(fd);
241 
        return -2;
242 
    }
243 
 
244 
    //--------------------------------------------------------------------------
245 
 
246 
    Verilated::commandArgs(argc, argv);
247 
 
248 
    Verilated::traceEverOn(true);
249 
    VerilatedVcdC* tracer = new VerilatedVcdC;
250 
 
251 
    VaoR3000 *top = new VaoR3000();
252 
    top->trace (tracer, 99);
253 
    //tracer->rolloverMB(1000000);
254 
    tracer->open("aoR3000.vcd");
255 
 
256 
    bool dump_enabled = true;
257 
 
258 
    //reset
259 
    vluint64_t halfcycle = 0;
260 
 
261 
    top->clk = 0; top->rst_n = 1; top->eval(); if(dump_enabled) { tracer->dump(halfcycle); } halfcycle++;
262 
    top->clk = 0; top->rst_n = 0; top->eval(); if(dump_enabled) { tracer->dump(halfcycle); } halfcycle++;
263 
    top->rst_n = 1;
264 
 
265 
    printf("Waiting for initialize..."); fflush(stdout);
266 
    while(shared_ptr->proc_ao.initialize_do == false) usleep_or_finish();
267 
 
268 
    initialize(top);
269 
    shared_ptr->proc_ao.initialize_do = false;
270 
    printf("done\n");
271 
 
272 
 
273 
    //--------------------------------------------------------------------------
274 
 
275 
    uint32 event_counter = 0;
276 
 
277 
    struct read_t {
278 
        uint32 count;
279 
        uint32 byteenable;
280 
        uint32 address;
281 
    };
282 
    read_t read[5];
283 
    uint32 read_list_count = sizeof(read) / sizeof(read_t);
284 
    memset(read, 0, sizeof(read));
285 
 
286 
    bool   stall_wait = false;
287 
    uint32 stall_pc = 0;
288 
    uint32 stall_branched = 0;
289 
    bool   stall_state = false;
290 
 
291 
    while(!Verilated::gotFinish()) {
292 
 
293 
        //---------------------------------------------------------------------- avalon master
294 
 
295 
        top->avm_waitrequest   = 0;
296 
        top->avm_readdatavalid = 0;
297 
        top->avm_readdata      = 0;
298 
 
299 
        if(top->avm_read) {
300 
            bool found = false;
301 
            for(uint32 i=0; i<read_list_count; i++) {
302 
                if(read[i].count == 0) {
303 
                    read[i].address    = top->avm_address & 0xFFFFFFFC;
304 
                    read[i].byteenable = top->avm_byteenable;
305 
                    read[i].count      = top->avm_burstcount;
306 
 
307 
                    found = true;
308 
                    break;
309 
                }
310 
            }
311 
            if(found == false) {
312 
                printf("[aoR3000]: read fatal error: too many reads.\n");
313 
                exit(-1);
314 
            }
315 
        }
316 
        else if(read[0].count > 0) {
317 
            top->avm_readdatavalid = 1;
318 
 
319 
            if(read[0].address < 0x08000000) {
320 
                top->avm_readdata = shared_ptr->mem.ints[read[0].address/4];
321 
            }
322 
            else {
323 
                shared_ptr->proc_ao.read_address    = read[0].address & 0xFFFFFFFC;
324 
                shared_ptr->proc_ao.read_byteenable = read[0].byteenable;
325 
                shared_ptr->proc_ao.read_do         = true;
326 
 
327 
                while(shared_ptr->proc_ao.read_do) usleep_or_finish();
328 
 
329 
                top->avm_readdata = shared_ptr->proc_ao.read_data;
330 
            }
331 
            read[0].address += 4;
332 
            read[0].count--;
333 
 
334 
            if(read[0].count == 0) {
335 
                memmove(&read[0], &read[1], sizeof(read) - sizeof(read_t));
336 
            }
337 
        }
338 
 
339 
        //----------------------------------------------------------------------
340 
 
341 
        uint32 cmd = top->v->pipeline_mem_inst->__PVT__mem_cmd & 0x7F;
342 
 
343 
        bool stall_start = cmd != 0   && stall_state == true;
344 
        bool stall_end   = stall_wait && stall_state == false;
345 
 
346 
        uint32 was_instruction = ((cmd != 0) && stall_state == false) || stall_end;
347 
        uint32 was_pc          = top->v->pipeline_mem_inst->__PVT__mem_pc_plus4;
348 
 
349 
        if(stall_start) {
350 
            stall_wait = true;
351 
            stall_pc = was_pc;
352 
        }
353 
        else if(stall_end) {
354 
            stall_wait = false;
355 
        }
356 
 
357 
        stall_state = (top->v->pipeline_mem_inst->__PVT__mem_stall & 1) != 0;
358 
 
359 
        report(top, true, false);
360 
 
361 
        //---------------------------------------------------------------------- interrupt
362 
 
363 
        top->interrupt_vector = (was_instruction && shared_ptr->irq2_at_event == (event_counter + 1))? 0x1 : 0;
364 
 
365 
        //---------------------------------------------------------------------- clock
366 
        top->clk = 0;
367 
        top->eval();
368 
 
369 
        if(dump_enabled) tracer->dump(halfcycle);
370 
        halfcycle++;
371 
 
372 
        top->clk = 1;
373 
        top->eval();
374 
 
375 
        if(dump_enabled) tracer->dump(halfcycle);
376 
        halfcycle++;
377 
 
378 
        tracer->flush();
379 
 
380 
        //----------------------------------------------------------------------
381 
        if(top->avm_write) {
382 
            if(top->avm_burstcount != 1) {
383 
                printf("[avalon master error]: top->avm_burstcount(%d) != 1\n", top->avm_burstcount);
384 
                exit(-1);
385 
            }
386 
 
387 
            uint32 mask = 0;
388 
            uint32 byteena = top->avm_byteenable;
389 
            for(uint32 i=0; i<4; i++) {
390 
                if(byteena & 1) mask |= (0xFF << (i*8));
391 
                byteena >>= 1;
392 
            }
393 
 
394 
            shared_ptr->proc_ao.write_address    = top->avm_address & 0xFFFFFFFC;
395 
            shared_ptr->proc_ao.write_byteenable = top->avm_byteenable;
396 
            shared_ptr->proc_ao.write_data       = top->avm_writedata & mask;
397 
            shared_ptr->proc_ao.write_do         = true;
398 
 
399 
            while(shared_ptr->proc_ao.write_do) usleep_or_finish();
400 
        }
401 
 
402 
        uint32 is_exception = top->v->pipeline_if_inst->__PVT__exc_waiting & 1;
403 
 
404 
        if((is_exception && (event_counter > 0 || halfcycle >= (4*2))) || was_instruction) {
405 
 
406 
            was_pc       = (stall_end)? stall_pc       : was_pc;
407 
 
408 
            report(top, is_exception, cmd == 40); //TLBR
409 
            shared_ptr->proc_ao.report.counter     = event_counter;
410 
            shared_ptr->proc_ao.report.exception   = (is_exception)? 1 : 0;
411 
 
412 
            if(is_exception)    PUT(pc, top->v->pipeline_if_inst->__PVT__exc_start_pc, 0xFFFFFFFF);
413 
            else                PUT(pc, was_pc, 0xFFFFFFFF);
414 
 
415 
            shared_ptr->proc_ao.report_do = true;
416 
 
417 
            while(shared_ptr->proc_ao.report_do) usleep_or_finish();
418 
 
419 
            event_counter++;
420 
        }
421 
    }
422 
 
423 
    top->final();
424 
    delete top;
425 
    return 0;
426 
}
427 
 
428 
//------------------------------------------------------------------------------
429 
 
430 
/*
431 
module aoR3000(
432 
    input               clk,
433 
    input               rst_n,
434 
 
435 
    //
436 
    input       [5:0]   interrupt_vector,
437 
 
438 
    //
439 
    output      [31:0]  avm_address,
440 
    output      [31:0]  avm_writedata,
441 
    output      [3:0]   avm_byteenable,
442 
    output      [2:0]   avm_burstcount,
443 
    output              avm_write,
444 
    output              avm_read,
445 
 
446 
    input               avm_waitrequest,
447 
    input               avm_readdatavalid,
448 
    input       [31:0]  avm_readdata
449 
);
450 
*/
451 
 
452 
//------------------------------------------------------------------------------

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