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URL https://opencores.org/ocsvn/astron_diagnostics/astron_diagnostics/trunk

Subversion Repositories astron_diagnostics

[/] [astron_diagnostics/] [trunk/] [hdllib.cfg] - Blame information for rev 4

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Line No. Rev Author Line
1 4 danv
hdl_lib_name = astron_diagnostics
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hdl_library_clause_name = astron_diagnostics_lib
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hdl_lib_uses_synth = common_pkg dp_pkg dp_components common_components astron_ram astron_counter astron_ram astron_multiplexer astron_mm astron_pipeline
4 2 danv
hdl_lib_uses_sim =
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hdl_lib_technology =
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synth_files =
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    diag_pkg.vhd
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#    src/vhdl/diag_bypass.vhd
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#    src/vhdl/diag_tx_frm.vhd
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    diag_rx_seq.vhd
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#    src/vhdl/diag_frm_generator.vhd
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#    src/vhdl/diag_frm_monitor.vhd
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    mms_diag_rx_seq.vhd
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#    src/vhdl/diag_wg.vhd
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#    src/vhdl/diag_wg_wideband.vhd
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#    src/vhdl/diag_wg_wideband_reg.vhd
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#    src/vhdl/mms_diag_wg_wideband.vhd
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    diag_data_buffer.vhd
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#    src/vhdl/diag_data_buffer_dev.vhd
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    mms_diag_data_buffer.vhd
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#    src/vhdl/mms_diag_data_buffer_dev.vhd
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    diag_tx_seq.vhd
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    diag_block_gen.vhd
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    diag_block_gen_reg.vhd
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    mms_diag_tx_seq.vhd
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    mms_diag_block_gen.vhd
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test_bench_files =
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#    tb/vhdl/tb_diag_pkg.vhd
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#    tb/vhdl/tb_diag_wg.vhd
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#    tb/vhdl/tb_diag_wg_wideband.vhd
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#    tb/vhdl/tb_diag_tx_seq.vhd
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#    tb/vhdl/tb_diag_rx_seq.vhd
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#    tb/vhdl/tb_tb_diag_rx_seq.vhd
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#    tb/vhdl/tb_diag_tx_frm.vhd
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#    tb/vhdl/tb_diag_frm_generator.vhd
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#    tb/vhdl/tb_diag_frm_monitor.vhd
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#    tb/vhdl/tb_diag_data_buffer_dev.vhd
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#    tb/vhdl/tb_mms_diag_seq.vhd
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#    tb/vhdl/tb_tb_mms_diag_seq.vhd
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#    tb/vhdl/tb_diag_block_gen.vhd
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#    tb/vhdl/tb_tb_diag_block_gen.vhd
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#    tb/vhdl/tb_mms_diag_block_gen.vhd
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#    tb/vhdl/tb_tb_mms_diag_block_gen.vhd
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#    tb/vhdl/tb_diag_regression.vhd
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regression_test_vhdl =
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#    tb/vhdl/tb_diag_wg.vhd
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#    tb/vhdl/tb_diag_wg_wideband.vhd
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#    tb/vhdl/tb_diag_frm_generator.vhd
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#    tb/vhdl/tb_diag_frm_monitor.vhd
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#    tb/vhdl/tb_tb_diag_block_gen.vhd
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#    tb/vhdl/tb_tb_diag_rx_seq.vhd
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#    tb/vhdl/tb_tb_mms_diag_seq.vhd
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#    tb/vhdl/tb_tb_mms_diag_block_gen.vhd
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[modelsim_project_file]
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modelsim_copy_files =
63 4 danv
#    src/data data
64 2 danv
 
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[quartus_project_file]
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