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1 69 wsong0210
/*
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 Asynchronous SDM NoC
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 (C)2011 Wei Song
4
 Advanced Processor Technologies Group
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 Computer Science, the Univ. of Manchester, UK
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7
 Authors:
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 Wei Song     wsong83@gmail.com
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 License: LGPL 3.0 or later
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 A CM of a buffered Clos for SDM-Clos routers
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 *** SystemVerilog is used ***
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15
 History:
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 08/07/2011  Initial version. <wsong83@gmail.com>
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*/
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// the router structure definitions
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`include "define.v"
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23 70 wsong0210
module cm (
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   // Outputs
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   do0, do1, do2, do3, dia, do4,
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   // Inputs
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   di0, di1, di2, di3, sdec, ndec, ldec, wdec, edec, di4, doa, doa4,
28 70 wsong0210
`ifndef ENABLE_CRRD
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   cms,
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`endif
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   rst_n
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   );
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   parameter KN = 5;           // dummy parameter, the number of IMs
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   parameter DW = 8;           // the data width of each IP
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   parameter SCN = DW/2;       // the number of sub-channels in one IP
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   input [KN-1:0][SCN-1:0]    di0, di1, di2, di3;      // input data
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   input [3:0]                 sdec, ndec, ldec;        // the decoded direction requests
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   input [1:0]                 wdec, edec;              // the decoded direction requests
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   output [KN-1:0][SCN-1:0]   do0, do1, do2, do3;      // output data
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`ifdef ENABLE_CHANNEL_SLICING
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   input [KN-1:0][SCN-1:0]    di4;                     // data input
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   output [KN-1:0][SCN-1:0]   dia;                       // input ack
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   output [KN-1:0][SCN-1:0]   do4;                       // data output
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   input [KN-1:0][SCN-1:0]    doa, doa4;         // output ack
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`else
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   input [KN-1:0]              di4;                     // data input
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   output [KN-1:0]             dia;                     // input ack
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   output [KN-1:0]             do4;                     // data output
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   input [KN-1:0]              doa, doa4;               // output ack
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`endif // !`ifdef ENABLE_CHANNEL_SLICING
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`ifndef ENABLE_CRRD
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   output [KN-1:0]             cms; // the state feedback to IMs
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`endif
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   input                      rst_n; // global active low reset
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   wire [3:0]                  wcfg, ecfg, lcfg; // switch configuration
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   wire [1:0]                  scfg, ncfg;       // switch configuration
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   genvar                     i, j;
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   // data switch
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   dcb_xy #(.VCN(1), .VCW(DW))
68 70 wsong0210
   CMDCB (
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          .sia   ( dia[0]    ),
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          .wia   ( dia[1]    ),
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          .nia   ( dia[2]    ),
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          .eia   ( dia[3]    ),
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          .lia   ( dia[4]    ),
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          .so0   ( do0[0]    ),
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          .so1   ( do1[0]    ),
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          .so2   ( do2[0]    ),
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          .so3   ( do3[0]    ),
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          .so4   ( do4[0]    ),
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          .wo0   ( do0[1]    ),
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          .wo1   ( do1[1]    ),
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          .wo2   ( do2[1]    ),
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          .wo3   ( do3[1]    ),
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          .wo4   ( do4[1]    ),
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          .no0   ( do0[2]    ),
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          .no1   ( do1[2]    ),
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          .no2   ( do2[2]    ),
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          .no3   ( do3[2]    ),
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          .no4   ( do4[2]    ),
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          .eo0   ( do0[3]    ),
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          .eo1   ( do1[3]    ),
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          .eo2   ( do2[3]    ),
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          .eo3   ( do3[3]    ),
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          .eo4   ( do4[3]    ),
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          .lo0   ( do0[4]    ),
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          .lo1   ( do1[4]    ),
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          .lo2   ( do2[4]    ),
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          .lo3   ( do3[4]    ),
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          .lo4   ( do4[4]    ),
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          .si0   ( di0[0]    ),
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          .si1   ( di1[0]    ),
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          .si2   ( di2[0]    ),
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          .si3   ( di3[0]    ),
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          .si4   ( di4[0]    ),
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          .wi0   ( di0[1]    ),
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          .wi1   ( di1[1]    ),
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          .wi2   ( di2[1]    ),
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          .wi3   ( di3[1]    ),
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          .wi4   ( di4[1]    ),
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          .ni0   ( di0[2]    ),
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          .ni1   ( di1[2]    ),
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          .ni2   ( di2[2]    ),
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          .ni3   ( di3[2]    ),
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          .ni4   ( di4[2]    ),
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          .ei0   ( di0[3]    ),
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          .ei1   ( di1[3]    ),
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          .ei2   ( di2[3]    ),
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          .ei3   ( di3[3]    ),
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          .ei4   ( di4[3]    ),
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          .li0   ( di0[4]    ),
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          .li1   ( di1[4]    ),
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          .li2   ( di2[4]    ),
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          .li3   ( di3[4]    ),
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          .li4   ( di4[4]    ),
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          .soa   ( doa[0]    ),
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          .woa   ( doa[1]    ),
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          .noa   ( doa[2]    ),
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          .eoa   ( doa[3]    ),
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          .loa   ( doa[4]    ),
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          .soa4  ( doa4[0]   ),
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          .woa4  ( doa4[1]   ),
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          .noa4  ( doa4[2]   ),
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          .eoa4  ( doa4[3]   ),
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          .loa4  ( doa4[4]   ),
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          .wcfg  ( wcfg      ),
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          .ecfg  ( ecfg      ),
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          .lcfg  ( lcfg      ),
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          .scfg  ( scfg      ),
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          .ncfg  ( ncfg      )
139 70 wsong0210
          );
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   // the allocator
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   cm_alloc CMD (
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`ifndef ENABLE_CRRD
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                 .s     ( cms   ),
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`endif
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                 .sra   (       ),
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                 .wra   (       ),
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                 .nra   (       ),
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                 .era   (       ),
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                 .lra   (       ),
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                 .scfg  ( scfg  ),
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                 .ncfg  ( ncfg  ),
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                 .wcfg  ( wcfg  ),
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                 .ecfg  ( ecfg  ),
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                 .lcfg  ( lcfg  ),
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                 .sr    ( sdec  ),
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                 .wr    ( wdec  ),
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                 .nr    ( ndec  ),
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                 .er    ( edec  ),
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                 .lr    ( ldec  )
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                 );
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endmodule // cm

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