URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [clos_opt/] [clos_opt/] [src/] [router.v] - Blame information for rev 75

Go to most recent revision | Details | Compare with Previous | View Log


/*
 Asynchronous SDM NoC
 (C)2011 Wei Song
 Advanced Processor Technologies Group
 Computer Science, the Univ. of Manchester, UK
 
 Authors:
 Wei Song     wsong83@gmail.com
 
 License: LGPL 3.0 or later
 
 Wormhole/SDM router top level module
 *** SystemVerilog is used ***
 
 History:
 28/05/2009  Initial version. <wsong83@gmail.com>
 23/09/2010  Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
 22/10/2010  Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
 25/05/2011  Clean up for opensource. <wsong83@gmail.com>
 21/07/2011  Preparation for the buffered Clos switch. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
`include "define.v"
 
module router(/*AUTOARG*/
   // Outputs
   so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,
   eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,
   wia, nia, eia, lia,
   // Inputs
   si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
   ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,
   woa, noa, eoa, loa, addrx, addry, rst_n
   );
 
   parameter VCN = 1;           // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router
   parameter DW = 32;           // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN
   parameter IPD = 1;           // the number of half-buffer stages in input buffers
   parameter OPD = 2;           // the number of half-buffer stages in output buffers
   parameter SCN = DW/2;        // the number of 1-of-4 sub-channel in each virtual circuit
 
   input [VCN-1:0][SCN-1:0]      si0, si1, si2, si3; // south input [0], X+1
   input [VCN-1:0][SCN-1:0]        wi0, wi1, wi2, wi3; // west input [1], Y-1
   input [VCN-1:0][SCN-1:0]        ni0, ni1, ni2, ni3; // north input [2], X-1
   input [VCN-1:0][SCN-1:0]        ei0, ei1, ei2, ei3; // east input [3], Y+1
   input [VCN-1:0][SCN-1:0]        li0, li1, li2, li3; // local input
   output [VCN-1:0][SCN-1:0]       so0, so1, so2, so3; // south output
   output [VCN-1:0][SCN-1:0]       wo0, wo1, wo2, wo3; // west output
   output [VCN-1:0][SCN-1:0]       no0, no1, no2, no3; // north output
   output [VCN-1:0][SCN-1:0]       eo0, eo1, eo2, eo3; // east output
   output [VCN-1:0][SCN-1:0]       lo0, lo1, lo2, lo3; // local output
 
   // eof bits and ack lines
`ifdef ENABLE_CHANNEL_SLICING
   input [VCN-1:0][SCN-1:0]        si4, wi4, ni4, ei4, li4;
   output [VCN-1:0][SCN-1:0]       so4, wo4, no4, eo4, lo4;
   output [VCN-1:0][SCN-1:0]       sia, wia, nia, eia, lia;
   input [VCN-1:0][SCN-1:0]        soa, woa, noa, eoa, loa;
`else
   input [VCN-1:0]                si4, wi4, ni4, ei4, li4;
   output [VCN-1:0]               so4, wo4, no4, eo4, lo4;
   output [VCN-1:0]               sia, wia, nia, eia, lia;
   input [VCN-1:0]                soa, woa, noa, eoa, loa;
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
   input [7:0]                    addrx, addry; // the local address of the router, coded in 1-of-4 coding
   input                         rst_n;        // active low reset signal
 
   // internal wires, input buffers to switches (crossbar): [dir]2[cb][1-of-4 index]
   wire [VCN-1:0][SCN-1:0]         s2c0, s2c1, s2c2, s2c3; // south input to switch data
   wire [VCN-1:0][SCN-1:0]         w2c0, w2c1, w2c2, w2c3;
   wire [VCN-1:0][SCN-1:0]         n2c0, n2c1, n2c2, n2c3;
   wire [VCN-1:0][SCN-1:0]         e2c0, e2c1, e2c2, e2c3;
   wire [VCN-1:0][SCN-1:0]         l2c0, l2c1, l2c2, l2c3;
   // internal wires, switches (crossbar) to output buffers: [cb]2[dir][1-of-4 index]
   wire [VCN-1:0][SCN-1:0]         c2s0, c2s1, c2s2, c2s3;
   wire [VCN-1:0][SCN-1:0]         c2w0, c2w1, c2w2, c2w3;
   wire [VCN-1:0][SCN-1:0]         c2n0, c2n1, c2n2, c2n3; // switch to north output
   wire [VCN-1:0][SCN-1:0]         c2e0, c2e1, c2e2, c2e3;
   wire [VCN-1:0][SCN-1:0]         c2l0, c2l1, c2l2, c2l3;
 
   // internal wires for ack and eof bits
`ifdef ENABLE_CHANNEL_SLICING
   wire [VCN-1:0][SCN-1:0]         s2c4, w2c4, n2c4, e2c4, l2c4;
   wire [VCN-1:0][SCN-1:0]         c2s4, c2w4, c2n4, c2e4, c2l4;
   wire [VCN-1:0][SCN-1:0]         s2ca, w2ca, n2ca, e2ca, l2ca;
   wire [VCN-1:0][SCN-1:0]         c2sa, c2wa, c2na, c2ea, c2la;
`else
   wire [VCN-1:0]                 s2c4, w2c4, n2c4, e2c4, l2c4;
   wire [VCN-1:0]                 c2s4, c2w4, c2n4, c2e4, c2l4;
   wire [VCN-1:0]                 s2ca, w2ca, n2ca, e2ca, l2ca;
   wire [VCN-1:0]                 c2sa, c2wa, c2na, c2ea, c2la;
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
   // the requests/acks from/to input buffers to switch allocators
   wire [VCN-1:0][3:0]             sreq, nreq, lreq;
   wire [VCN-1:0][1:0]             wreq, ereq;
   wire [VCN-1:0]                 sack, wack, nack, eack, lack;
 
   // configuration bits for the switches
`ifdef ENABLE_CLOS
   wire [4:0][VCN-1:0][VCN-1:0]  imcfg;
   wire [VCN-1:0][1:0]             scfg, ncfg;
   wire [VCN-1:0][3:0]             wcfg, ecfg, lcfg;
`else // normal crossbar based SDM
   wire [VCN-1:0][2*VCN-1:0]       scfg, ncfg;
   wire [VCN-1:0][4*VCN-1:0]       wcfg, ecfg, lcfg;
`endif
 
 
   genvar                 i;
 
   generate
      for (i=0; i<VCN; i++) begin: SC
 
         // --------------- input buffers ------------------- //
 
         inp_buf #(.DIR(0), .RN(4), .DW(DW), .PD(IPD))
         SIB (
              .o0     ( s2c0[i]  ),
              .o1     ( s2c1[i]  ),
              .o2     ( s2c2[i]  ),
              .o3     ( s2c3[i]  ),
              .o4     ( s2c4[i]  ),
              .ia     ( sia[i]   ),
              .deco   ( sreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( si0[i]   ),
              .i1     ( si1[i]   ),
              .i2     ( si2[i]   ),
              .i3     ( si3[i]   ),
              .i4     ( si4[i]   ),
              .oa     ( s2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    )
              );
 
         inp_buf #(.DIR(1), .RN(2), .DW(DW), .PD(IPD))
         WIB (
              .o0     ( w2c0[i]  ),
              .o1     ( w2c1[i]  ),
              .o2     ( w2c2[i]  ),
              .o3     ( w2c3[i]  ),
              .o4     ( w2c4[i]  ),
              .ia     ( wia[i]   ),
              .deco   ( wreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( wi0[i]   ),
              .i1     ( wi1[i]   ),
              .i2     ( wi2[i]   ),
              .i3     ( wi3[i]   ),
              .i4     ( wi4[i]   ),
              .oa     ( w2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    )
              );
 
         inp_buf #(.DIR(2), .RN(4), .DW(DW), .PD(IPD))
         NIB (
              .o0     ( n2c0[i]  ),
              .o1     ( n2c1[i]  ),
              .o2     ( n2c2[i]  ),
              .o3     ( n2c3[i]  ),
              .o4     ( n2c4[i]  ),
              .ia     ( nia[i]   ),
              .deco   ( nreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( ni0[i]   ),
              .i1     ( ni1[i]   ),
              .i2     ( ni2[i]   ),
              .i3     ( ni3[i]   ),
              .i4     ( ni4[i]   ),
              .oa     ( n2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    )
              );
 
         inp_buf #(.DIR(3), .RN(2), .DW(DW), .PD(IPD))
         EIB (
              .o0     ( e2c0[i]  ),
              .o1     ( e2c1[i]  ),
              .o2     ( e2c2[i]  ),
              .o3     ( e2c3[i]  ),
              .o4     ( e2c4[i]  ),
              .ia     ( eia[i]   ),
              .deco   ( ereq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( ei0[i]   ),
              .i1     ( ei1[i]   ),
              .i2     ( ei2[i]   ),
              .i3     ( ei3[i]   ),
              .i4     ( ei4[i]   ),
              .oa     ( e2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    )
              );
 
         inp_buf #(.DIR(4), .RN(4), .DW(DW), .PD(IPD))
         LIB (
              .o0     ( l2c0[i]  ),
              .o1     ( l2c1[i]  ),
              .o2     ( l2c2[i]  ),
              .o3     ( l2c3[i]  ),
              .o4     ( l2c4[i]  ),
              .ia     ( lia[i]   ),
              .deco   ( lreq[i]  ),
              .rst_n  ( rst_n    ),
              .i0     ( li0[i]   ),
              .i1     ( li1[i]   ),
              .i2     ( li2[i]   ),
              .i3     ( li3[i]   ),
              .i4     ( li4[i]   ),
              .oa     ( l2ca[i]  ),
              .addrx  ( addrx    ),
              .addry  ( addry    )
              );
 
         // --------------------- output buffers ---------------- //
         outp_buf #(.DW(DW), .PD(OPD))
         SOB (
              .o0     ( so0[i]   ),
              .o1     ( so1[i]   ),
              .o2     ( so2[i]   ),
              .o3     ( so3[i]   ),
              .o4     ( so4[i]   ),
              .oa     ( soa[i]   ),
              .i0     ( c2s0[i]  ),
              .i1     ( c2s1[i]  ),
              .i2     ( c2s2[i]  ),
              .i3     ( c2s3[i]  ),
              .i4     ( c2s4[i]  ),
              .ia     ( c2sa[i]  ),
              .ia4    ( c2sa4[i] ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         WOB (
              .o0     ( wo0[i]   ),
              .o1     ( wo1[i]   ),
              .o2     ( wo2[i]   ),
              .o3     ( wo3[i]   ),
              .o4     ( wo4[i]   ),
              .oa     ( woa[i]   ),
              .i0     ( c2w0[i]  ),
              .i1     ( c2w1[i]  ),
              .i2     ( c2w2[i]  ),
              .i3     ( c2w3[i]  ),
              .i4     ( c2w4[i]  ),
              .ia     ( c2wa[i]  ),
              .ia4    ( c2wa4[i] ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         NOB (
              .o0     ( no0[i]   ),
              .o1     ( no1[i]   ),
              .o2     ( no2[i]   ),
              .o3     ( no3[i]   ),
              .o4     ( no4[i]   ),
              .oa     ( noa[i]   ),
              .i0     ( c2n0[i]  ),
              .i1     ( c2n1[i]  ),
              .i2     ( c2n2[i]  ),
              .i3     ( c2n3[i]  ),
              .i4     ( c2n4[i]  ),
              .ia     ( c2na[i]  ),
              .ia4    ( c2na4[i] ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         EOB (
              .o0     ( eo0[i]   ),
              .o1     ( eo1[i]   ),
              .o2     ( eo2[i]   ),
              .o3     ( eo3[i]   ),
              .o4     ( eo4[i]   ),
              .oa     ( eoa[i]   ),
              .i0     ( c2e0[i]  ),
              .i1     ( c2e1[i]  ),
              .i2     ( c2e2[i]  ),
              .i3     ( c2e3[i]  ),
              .i4     ( c2e4[i]  ),
              .ia     ( c2ea[i]  ),
              .ia4    ( c2ea4[i] ),
              .rst_n  ( rst_n    )
              );
 
         outp_buf #(.DW(DW), .PD(OPD))
         LOB (
              .o0     ( lo0[i]   ),
              .o1     ( lo1[i]   ),
              .o2     ( lo2[i]   ),
              .o3     ( lo3[i]   ),
              .o4     ( lo4[i]   ),
              .oa     ( loa[i]   ),
              .i0     ( c2l0[i]  ),
              .i1     ( c2l1[i]  ),
              .i2     ( c2l2[i]  ),
              .i3     ( c2l3[i]  ),
              .i4     ( c2l4[i]  ),
              .ia     ( c2la[i]  ),
              .ia4    ( c2la4[i] ),
              .rst_n  ( rst_n    )
              );
 
      end // block: SC
   endgenerate
 
`ifdef ENABLE_CLOS
   clos #(.MN(VCN), .NN(VCN), .DW(DW))
   CB (
       .so0     ( c2s0      ),
       .so1     ( c2s1      ),
       .so2     ( c2s2      ),
       .so3     ( c2s3      ),
       .so4     ( c2s4      ),
       .soa     ( c2sa      ),
       .soa4    ( c2sa4     ),
       .wo0     ( c2w0      ),
       .wo1     ( c2w1      ),
       .wo2     ( c2w2      ),
       .wo3     ( c2w3      ),
       .wo4     ( c2w4      ),
       .woa     ( c2wa      ),
       .woa4    ( c2wa4     ),
       .no0     ( c2n0      ),
       .no1     ( c2n1      ),
       .no2     ( c2n2      ),
       .no3     ( c2n3      ),
       .no4     ( c2n4      ),
       .noa     ( c2na      ),
       .noa4    ( c2na4     ),
       .eo0     ( c2e0      ),
       .eo1     ( c2e1      ),
       .eo2     ( c2e2      ),
       .eo3     ( c2e3      ),
       .eo4     ( c2e4      ),
       .eoa     ( c2ea      ),
       .eoa4    ( c2ea4     ),
       .lo0     ( c2l0      ),
       .lo1     ( c2l1      ),
       .lo2     ( c2l2      ),
       .lo3     ( c2l3      ),
       .lo4     ( c2l4      ),
       .loa     ( c2la      ),
       .loa4    ( c2la4     ),
       .si0     ( s2c0      ),
       .si1     ( s2c1      ),
       .si2     ( s2c2      ),
       .si3     ( s2c3      ),
       .si4     ( s2c4      ),
       .sia     ( s2ca      ),
       .wi0     ( w2c0      ),
       .wi1     ( w2c1      ),
       .wi2     ( w2c2      ),
       .wi3     ( w2c3      ),
       .wi4     ( w2c4      ),
       .wia     ( w2ca      ),
       .ni0     ( n2c0      ),
       .ni1     ( n2c1      ),
       .ni2     ( n2c2      ),
       .ni3     ( n2c3      ),
       .ni4     ( n2c4      ),
       .nia     ( n2ca      ),
       .ei0     ( e2c0      ),
       .ei1     ( e2c1      ),
       .ei2     ( e2c2      ),
       .ei3     ( e2c3      ),
       .ei4     ( e2c4      ),
       .eia     ( e2ca      ),
       .li0     ( l2c0      ),
       .li1     ( l2c1      ),
       .li2     ( l2c2      ),
       .li3     ( l2c3      ),
       .li4     ( l2c4      ),
       .lia     ( l2ca      ),
       .rst_n   ( rst_n     )
       ) ;
 
`else  // Crossbar based SDM
 
   dcb_xy #(.VCN(VCN), .VCW(DW))
   CB (
       .so0     ( c2s0      ),
       .so1     ( c2s1      ),
       .so2     ( c2s2      ),
       .so3     ( c2s3      ),
       .so4     ( c2s4      ),
       .soa     ( c2sa      ),
       .wo0     ( c2w0      ),
       .wo1     ( c2w1      ),
       .wo2     ( c2w2      ),
       .wo3     ( c2w3      ),
       .wo4     ( c2w4      ),
       .woa     ( c2wa      ),
       .no0     ( c2n0      ),
       .no1     ( c2n1      ),
       .no2     ( c2n2      ),
       .no3     ( c2n3      ),
       .no4     ( c2n4      ),
       .noa     ( c2na      ),
       .eo0     ( c2e0      ),
       .eo1     ( c2e1      ),
       .eo2     ( c2e2      ),
       .eo3     ( c2e3      ),
       .eo4     ( c2e4      ),
       .eoa     ( c2ea      ),
       .lo0     ( c2l0      ),
       .lo1     ( c2l1      ),
       .lo2     ( c2l2      ),
       .lo3     ( c2l3      ),
       .lo4     ( c2l4      ),
       .loa     ( c2la      ),
       .si0     ( s2c0      ),
       .si1     ( s2c1      ),
       .si2     ( s2c2      ),
       .si3     ( s2c3      ),
       .si4     ( s2c4      ),
       .sia     ( s2ca      ),
       .wi0     ( w2c0      ),
       .wi1     ( w2c1      ),
       .wi2     ( w2c2      ),
       .wi3     ( w2c3      ),
       .wi4     ( w2c4      ),
       .wia     ( w2ca      ),
       .ni0     ( n2c0      ),
       .ni1     ( n2c1      ),
       .ni2     ( n2c2      ),
       .ni3     ( n2c3      ),
       .ni4     ( n2c4      ),
       .nia     ( n2ca      ),
       .ei0     ( e2c0      ),
       .ei1     ( e2c1      ),
       .ei2     ( e2c2      ),
       .ei3     ( e2c3      ),
       .ei4     ( e2c4      ),
       .eia     ( e2ca      ),
       .li0     ( l2c0      ),
       .li1     ( l2c1      ),
       .li2     ( l2c2      ),
       .li3     ( l2c3      ),
       .li4     ( l2c4      ),
       .lia     ( l2ca      ),
       .wcfg    ( wcfg      ),
       .ecfg    ( ecfg      ),
       .lcfg    ( lcfg      ),
       .scfg    ( scfg      ),
       .ncfg    ( ncfg      )
       ) ;
 
 
   sdm_sch #(.VCN(VCN))
   ALLOC (
          .sack  ( sack    ),
          .wack  ( wack    ),
          .nack  ( nack    ),
          .eack  ( eack    ),
          .lack  ( lack    ),
          .scfg  ( scfg    ),
          .ncfg  ( ncfg    ),
          .wcfg  ( wcfg    ),
          .ecfg  ( ecfg    ),
          .lcfg  ( lcfg    ),
          .sreq  ( sreq    ),
          .nreq  ( nreq    ),
          .lreq  ( lreq    ),
          .wreq  ( wreq    ),
          .ereq  ( ereq    ),
          .rst_n ( rst_n   )
          );
`endif
 
endmodule // router

Line No.	Rev	Author	Line
1	13	wsong0210	`/*`
2			`Asynchronous SDM NoC`
3			`(C)2011 Wei Song`
4			`Advanced Processor Technologies Group`
5			`Computer Science, the Univ. of Manchester, UK`
6
7			`Authors:`
8			`Wei Song wsong83@gmail.com`
9
10			`License: LGPL 3.0 or later`
11
12			`Wormhole/SDM router top level module`
13			`* SystemVerilog is used *`
14
15			`History:`
16			`28/05/2009 Initial version. <wsong83@gmail.com>`
17			`23/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>`
18			`22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>`
19	19	wsong0210	`25/05/2011 Clean up for opensource. <wsong83@gmail.com>`
20	75	wsong0210	`21/07/2011 Preparation for the buffered Clos switch. <wsong83@gmail.com>`
21	13	wsong0210
22			`*/`
23
24			`// the router structure definitions`
25			`include "define.v"
26
27			`module router(/AUTOARG/`
28			`// Outputs`
29			`so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0,`
30			`eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia,`
31			`wia, nia, eia, lia,`
32			`// Inputs`
33			`si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,`
34			`ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa,`
35			`woa, noa, eoa, loa, addrx, addry, rst_n`
36			`);`
37
38			`parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router`
39			`parameter DW = 32; // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN`
40			`parameter IPD = 1; // the number of half-buffer stages in input buffers`
41			`parameter OPD = 2; // the number of half-buffer stages in output buffers`
42			`parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit`
43
44			`input [VCN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1`
45			`input [VCN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1`
46			`input [VCN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1`
47			`input [VCN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1`
48			`input [VCN-1:0][SCN-1:0] li0, li1, li2, li3; // local input`
49			`output [VCN-1:0][SCN-1:0] so0, so1, so2, so3; // south output`
50			`output [VCN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output`
51			`output [VCN-1:0][SCN-1:0] no0, no1, no2, no3; // north output`
52			`output [VCN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output`
53			`output [VCN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output`
54
55			`// eof bits and ack lines`
56			`ifdef ENABLE_CHANNEL_SLICING
57			`input [VCN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4;`
58			`output [VCN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4;`
59			`output [VCN-1:0][SCN-1:0] sia, wia, nia, eia, lia;`
60			`input [VCN-1:0][SCN-1:0] soa, woa, noa, eoa, loa;`
61			`else
62			`input [VCN-1:0] si4, wi4, ni4, ei4, li4;`
63			`output [VCN-1:0] so4, wo4, no4, eo4, lo4;`
64			`output [VCN-1:0] sia, wia, nia, eia, lia;`
65			`input [VCN-1:0] soa, woa, noa, eoa, loa;`
66			`endif // !`ifdef ENABLE_CHANNEL_SLICING
67
68			`input [7:0] addrx, addry; // the local address of the router, coded in 1-of-4 coding`
69			`input rst_n; // active low reset signal`
70
71			`// internal wires, input buffers to switches (crossbar): [dir]2[cb][1-of-4 index]`
72			`wire [VCN-1:0][SCN-1:0] s2c0, s2c1, s2c2, s2c3; // south input to switch data`
73			`wire [VCN-1:0][SCN-1:0] w2c0, w2c1, w2c2, w2c3;`
74			`wire [VCN-1:0][SCN-1:0] n2c0, n2c1, n2c2, n2c3;`
75			`wire [VCN-1:0][SCN-1:0] e2c0, e2c1, e2c2, e2c3;`
76			`wire [VCN-1:0][SCN-1:0] l2c0, l2c1, l2c2, l2c3;`
77			`// internal wires, switches (crossbar) to output buffers: [cb]2[dir][1-of-4 index]`
78			`wire [VCN-1:0][SCN-1:0] c2s0, c2s1, c2s2, c2s3;`
79			`wire [VCN-1:0][SCN-1:0] c2w0, c2w1, c2w2, c2w3;`
80			`wire [VCN-1:0][SCN-1:0] c2n0, c2n1, c2n2, c2n3; // switch to north output`
81			`wire [VCN-1:0][SCN-1:0] c2e0, c2e1, c2e2, c2e3;`
82			`wire [VCN-1:0][SCN-1:0] c2l0, c2l1, c2l2, c2l3;`
83
84			`// internal wires for ack and eof bits`
85			`ifdef ENABLE_CHANNEL_SLICING
86			`wire [VCN-1:0][SCN-1:0] s2c4, w2c4, n2c4, e2c4, l2c4;`
87			`wire [VCN-1:0][SCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;`
88			`wire [VCN-1:0][SCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;`
89			`wire [VCN-1:0][SCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;`
90			`else
91			`wire [VCN-1:0] s2c4, w2c4, n2c4, e2c4, l2c4;`
92			`wire [VCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;`
93			`wire [VCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;`
94			`wire [VCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;`
95			`endif // !`ifdef ENABLE_CHANNEL_SLICING
96
97			`// the requests/acks from/to input buffers to switch allocators`
98			`wire [VCN-1:0][3:0] sreq, nreq, lreq;`
99			`wire [VCN-1:0][1:0] wreq, ereq;`
100			`wire [VCN-1:0] sack, wack, nack, eack, lack;`
101
102			`// configuration bits for the switches`
103			`ifdef ENABLE_CLOS
104			`wire [4:0][VCN-1:0][VCN-1:0] imcfg;`
105			`wire [VCN-1:0][1:0] scfg, ncfg;`
106			`wire [VCN-1:0][3:0] wcfg, ecfg, lcfg;`
107			`else // normal crossbar based SDM
108			`wire [VCN-1:0][2*VCN-1:0] scfg, ncfg;`
109			`wire [VCN-1:0][4*VCN-1:0] wcfg, ecfg, lcfg;`
110			`endif
111
112
113			`genvar i;`
114
115			`generate`
116			`for (i=0; i<VCN; i++) begin: SC`
117
118			`// --------------- input buffers ------------------- //`
119
120			`inp_buf #(.DIR(0), .RN(4), .DW(DW), .PD(IPD))`
121			`SIB (`
122			`.o0 ( s2c0[i] ),`
123			`.o1 ( s2c1[i] ),`
124			`.o2 ( s2c2[i] ),`
125			`.o3 ( s2c3[i] ),`
126			`.o4 ( s2c4[i] ),`
127			`.ia ( sia[i] ),`
128	75	wsong0210	`.deco ( sreq[i] ),`
129	13	wsong0210	`.rst_n ( rst_n ),`
130			`.i0 ( si0[i] ),`
131			`.i1 ( si1[i] ),`
132			`.i2 ( si2[i] ),`
133			`.i3 ( si3[i] ),`
134			`.i4 ( si4[i] ),`
135			`.oa ( s2ca[i] ),`
136			`.addrx ( addrx ),`
137	75	wsong0210	`.addry ( addry )`
138	13	wsong0210	`);`
139
140			`inp_buf #(.DIR(1), .RN(2), .DW(DW), .PD(IPD))`
141			`WIB (`
142			`.o0 ( w2c0[i] ),`
143			`.o1 ( w2c1[i] ),`
144			`.o2 ( w2c2[i] ),`
145			`.o3 ( w2c3[i] ),`
146			`.o4 ( w2c4[i] ),`
147			`.ia ( wia[i] ),`
148	75	wsong0210	`.deco ( wreq[i] ),`
149	13	wsong0210	`.rst_n ( rst_n ),`
150			`.i0 ( wi0[i] ),`
151			`.i1 ( wi1[i] ),`
152			`.i2 ( wi2[i] ),`
153			`.i3 ( wi3[i] ),`
154			`.i4 ( wi4[i] ),`
155			`.oa ( w2ca[i] ),`
156			`.addrx ( addrx ),`
157	75	wsong0210	`.addry ( addry )`
158	13	wsong0210	`);`
159
160			`inp_buf #(.DIR(2), .RN(4), .DW(DW), .PD(IPD))`
161			`NIB (`
162			`.o0 ( n2c0[i] ),`
163			`.o1 ( n2c1[i] ),`
164			`.o2 ( n2c2[i] ),`
165			`.o3 ( n2c3[i] ),`
166			`.o4 ( n2c4[i] ),`
167			`.ia ( nia[i] ),`
168	75	wsong0210	`.deco ( nreq[i] ),`
169	13	wsong0210	`.rst_n ( rst_n ),`
170			`.i0 ( ni0[i] ),`
171			`.i1 ( ni1[i] ),`
172			`.i2 ( ni2[i] ),`
173			`.i3 ( ni3[i] ),`
174			`.i4 ( ni4[i] ),`
175			`.oa ( n2ca[i] ),`
176			`.addrx ( addrx ),`
177	75	wsong0210	`.addry ( addry )`
178	13	wsong0210	`);`
179
180			`inp_buf #(.DIR(3), .RN(2), .DW(DW), .PD(IPD))`
181			`EIB (`
182			`.o0 ( e2c0[i] ),`
183			`.o1 ( e2c1[i] ),`
184			`.o2 ( e2c2[i] ),`
185			`.o3 ( e2c3[i] ),`
186			`.o4 ( e2c4[i] ),`
187			`.ia ( eia[i] ),`
188	75	wsong0210	`.deco ( ereq[i] ),`
189	13	wsong0210	`.rst_n ( rst_n ),`
190			`.i0 ( ei0[i] ),`
191			`.i1 ( ei1[i] ),`
192			`.i2 ( ei2[i] ),`
193			`.i3 ( ei3[i] ),`
194			`.i4 ( ei4[i] ),`
195			`.oa ( e2ca[i] ),`
196			`.addrx ( addrx ),`
197	75	wsong0210	`.addry ( addry )`
198	13	wsong0210	`);`
199
200			`inp_buf #(.DIR(4), .RN(4), .DW(DW), .PD(IPD))`
201			`LIB (`
202			`.o0 ( l2c0[i] ),`
203			`.o1 ( l2c1[i] ),`
204			`.o2 ( l2c2[i] ),`
205			`.o3 ( l2c3[i] ),`
206			`.o4 ( l2c4[i] ),`
207			`.ia ( lia[i] ),`
208	75	wsong0210	`.deco ( lreq[i] ),`
209	13	wsong0210	`.rst_n ( rst_n ),`
210			`.i0 ( li0[i] ),`
211			`.i1 ( li1[i] ),`
212			`.i2 ( li2[i] ),`
213			`.i3 ( li3[i] ),`
214			`.i4 ( li4[i] ),`
215			`.oa ( l2ca[i] ),`
216			`.addrx ( addrx ),`
217	75	wsong0210	`.addry ( addry )`
218	13	wsong0210	`);`
219
220			`// --------------------- output buffers ---------------- //`
221			`outp_buf #(.DW(DW), .PD(OPD))`
222			`SOB (`
223			`.o0 ( so0[i] ),`
224			`.o1 ( so1[i] ),`
225			`.o2 ( so2[i] ),`
226			`.o3 ( so3[i] ),`
227			`.o4 ( so4[i] ),`
228			`.oa ( soa[i] ),`
229			`.i0 ( c2s0[i] ),`
230			`.i1 ( c2s1[i] ),`
231			`.i2 ( c2s2[i] ),`
232			`.i3 ( c2s3[i] ),`
233			`.i4 ( c2s4[i] ),`
234			`.ia ( c2sa[i] ),`
235	75	wsong0210	`.ia4 ( c2sa4[i] ),`
236	13	wsong0210	`.rst_n ( rst_n )`
237			`);`
238
239			`outp_buf #(.DW(DW), .PD(OPD))`
240			`WOB (`
241			`.o0 ( wo0[i] ),`
242			`.o1 ( wo1[i] ),`
243			`.o2 ( wo2[i] ),`
244			`.o3 ( wo3[i] ),`
245			`.o4 ( wo4[i] ),`
246			`.oa ( woa[i] ),`
247			`.i0 ( c2w0[i] ),`
248			`.i1 ( c2w1[i] ),`
249			`.i2 ( c2w2[i] ),`
250			`.i3 ( c2w3[i] ),`
251			`.i4 ( c2w4[i] ),`
252			`.ia ( c2wa[i] ),`
253	75	wsong0210	`.ia4 ( c2wa4[i] ),`
254	13	wsong0210	`.rst_n ( rst_n )`
255			`);`
256
257			`outp_buf #(.DW(DW), .PD(OPD))`
258			`NOB (`
259			`.o0 ( no0[i] ),`
260			`.o1 ( no1[i] ),`
261			`.o2 ( no2[i] ),`
262			`.o3 ( no3[i] ),`
263			`.o4 ( no4[i] ),`
264			`.oa ( noa[i] ),`
265			`.i0 ( c2n0[i] ),`
266			`.i1 ( c2n1[i] ),`
267			`.i2 ( c2n2[i] ),`
268			`.i3 ( c2n3[i] ),`
269			`.i4 ( c2n4[i] ),`
270			`.ia ( c2na[i] ),`
271	75	wsong0210	`.ia4 ( c2na4[i] ),`
272	13	wsong0210	`.rst_n ( rst_n )`
273			`);`
274
275			`outp_buf #(.DW(DW), .PD(OPD))`
276			`EOB (`
277			`.o0 ( eo0[i] ),`
278			`.o1 ( eo1[i] ),`
279			`.o2 ( eo2[i] ),`
280			`.o3 ( eo3[i] ),`
281			`.o4 ( eo4[i] ),`
282			`.oa ( eoa[i] ),`
283			`.i0 ( c2e0[i] ),`
284			`.i1 ( c2e1[i] ),`
285			`.i2 ( c2e2[i] ),`
286			`.i3 ( c2e3[i] ),`
287			`.i4 ( c2e4[i] ),`
288			`.ia ( c2ea[i] ),`
289	75	wsong0210	`.ia4 ( c2ea4[i] ),`
290	13	wsong0210	`.rst_n ( rst_n )`
291			`);`
292
293			`outp_buf #(.DW(DW), .PD(OPD))`
294			`LOB (`
295			`.o0 ( lo0[i] ),`
296			`.o1 ( lo1[i] ),`
297			`.o2 ( lo2[i] ),`
298			`.o3 ( lo3[i] ),`
299			`.o4 ( lo4[i] ),`
300			`.oa ( loa[i] ),`
301			`.i0 ( c2l0[i] ),`
302			`.i1 ( c2l1[i] ),`
303			`.i2 ( c2l2[i] ),`
304			`.i3 ( c2l3[i] ),`
305			`.i4 ( c2l4[i] ),`
306			`.ia ( c2la[i] ),`
307	75	wsong0210	`.ia4 ( c2la4[i] ),`
308	13	wsong0210	`.rst_n ( rst_n )`
309			`);`
310
311			`end // block: SC`
312			`endgenerate`
313
314			`ifdef ENABLE_CLOS
315	75	wsong0210	`clos #(.MN(VCN), .NN(VCN), .DW(DW))`
316	13	wsong0210	`CB (`
317			`.so0 ( c2s0 ),`
318			`.so1 ( c2s1 ),`
319			`.so2 ( c2s2 ),`
320			`.so3 ( c2s3 ),`
321			`.so4 ( c2s4 ),`
322			`.soa ( c2sa ),`
323	75	wsong0210	`.soa4 ( c2sa4 ),`
324	13	wsong0210	`.wo0 ( c2w0 ),`
325			`.wo1 ( c2w1 ),`
326			`.wo2 ( c2w2 ),`
327			`.wo3 ( c2w3 ),`
328			`.wo4 ( c2w4 ),`
329			`.woa ( c2wa ),`
330	75	wsong0210	`.woa4 ( c2wa4 ),`
331	13	wsong0210	`.no0 ( c2n0 ),`
332			`.no1 ( c2n1 ),`
333			`.no2 ( c2n2 ),`
334			`.no3 ( c2n3 ),`
335			`.no4 ( c2n4 ),`
336			`.noa ( c2na ),`
337	75	wsong0210	`.noa4 ( c2na4 ),`
338	13	wsong0210	`.eo0 ( c2e0 ),`
339			`.eo1 ( c2e1 ),`
340			`.eo2 ( c2e2 ),`
341			`.eo3 ( c2e3 ),`
342			`.eo4 ( c2e4 ),`
343			`.eoa ( c2ea ),`
344	75	wsong0210	`.eoa4 ( c2ea4 ),`
345	13	wsong0210	`.lo0 ( c2l0 ),`
346			`.lo1 ( c2l1 ),`
347			`.lo2 ( c2l2 ),`
348			`.lo3 ( c2l3 ),`
349			`.lo4 ( c2l4 ),`
350			`.loa ( c2la ),`
351	75	wsong0210	`.loa4 ( c2la4 ),`
352	13	wsong0210	`.si0 ( s2c0 ),`
353			`.si1 ( s2c1 ),`
354			`.si2 ( s2c2 ),`
355			`.si3 ( s2c3 ),`
356			`.si4 ( s2c4 ),`
357			`.sia ( s2ca ),`
358			`.wi0 ( w2c0 ),`
359			`.wi1 ( w2c1 ),`
360			`.wi2 ( w2c2 ),`
361			`.wi3 ( w2c3 ),`
362			`.wi4 ( w2c4 ),`
363			`.wia ( w2ca ),`
364			`.ni0 ( n2c0 ),`
365			`.ni1 ( n2c1 ),`
366			`.ni2 ( n2c2 ),`
367			`.ni3 ( n2c3 ),`
368			`.ni4 ( n2c4 ),`
369			`.nia ( n2ca ),`
370			`.ei0 ( e2c0 ),`
371			`.ei1 ( e2c1 ),`
372			`.ei2 ( e2c2 ),`
373			`.ei3 ( e2c3 ),`
374			`.ei4 ( e2c4 ),`
375			`.eia ( e2ca ),`
376			`.li0 ( l2c0 ),`
377			`.li1 ( l2c1 ),`
378			`.li2 ( l2c2 ),`
379			`.li3 ( l2c3 ),`
380			`.li4 ( l2c4 ),`
381			`.lia ( l2ca ),`
382	75	wsong0210	`.rst_n ( rst_n )`
383	13	wsong0210	`) ;`
384
385			`else // Crossbar based SDM
386
387	28	wsong0210	`dcb_xy #(.VCN(VCN), .VCW(DW))`
388	13	wsong0210	`CB (`
389			`.so0 ( c2s0 ),`
390			`.so1 ( c2s1 ),`
391			`.so2 ( c2s2 ),`
392			`.so3 ( c2s3 ),`
393			`.so4 ( c2s4 ),`
394			`.soa ( c2sa ),`
395			`.wo0 ( c2w0 ),`
396			`.wo1 ( c2w1 ),`
397			`.wo2 ( c2w2 ),`
398			`.wo3 ( c2w3 ),`
399			`.wo4 ( c2w4 ),`
400			`.woa ( c2wa ),`
401			`.no0 ( c2n0 ),`
402			`.no1 ( c2n1 ),`
403			`.no2 ( c2n2 ),`
404			`.no3 ( c2n3 ),`
405			`.no4 ( c2n4 ),`
406			`.noa ( c2na ),`
407			`.eo0 ( c2e0 ),`
408			`.eo1 ( c2e1 ),`
409			`.eo2 ( c2e2 ),`
410			`.eo3 ( c2e3 ),`
411			`.eo4 ( c2e4 ),`
412			`.eoa ( c2ea ),`
413			`.lo0 ( c2l0 ),`
414			`.lo1 ( c2l1 ),`
415			`.lo2 ( c2l2 ),`
416			`.lo3 ( c2l3 ),`
417			`.lo4 ( c2l4 ),`
418			`.loa ( c2la ),`
419			`.si0 ( s2c0 ),`
420			`.si1 ( s2c1 ),`
421			`.si2 ( s2c2 ),`
422			`.si3 ( s2c3 ),`
423			`.si4 ( s2c4 ),`
424			`.sia ( s2ca ),`
425			`.wi0 ( w2c0 ),`
426			`.wi1 ( w2c1 ),`
427			`.wi2 ( w2c2 ),`
428			`.wi3 ( w2c3 ),`
429			`.wi4 ( w2c4 ),`
430			`.wia ( w2ca ),`
431			`.ni0 ( n2c0 ),`
432			`.ni1 ( n2c1 ),`
433			`.ni2 ( n2c2 ),`
434			`.ni3 ( n2c3 ),`
435			`.ni4 ( n2c4 ),`
436			`.nia ( n2ca ),`
437			`.ei0 ( e2c0 ),`
438			`.ei1 ( e2c1 ),`
439			`.ei2 ( e2c2 ),`
440			`.ei3 ( e2c3 ),`
441			`.ei4 ( e2c4 ),`
442			`.eia ( e2ca ),`
443			`.li0 ( l2c0 ),`
444			`.li1 ( l2c1 ),`
445			`.li2 ( l2c2 ),`
446			`.li3 ( l2c3 ),`
447			`.li4 ( l2c4 ),`
448			`.lia ( l2ca ),`
449			`.wcfg ( wcfg ),`
450			`.ecfg ( ecfg ),`
451			`.lcfg ( lcfg ),`
452			`.scfg ( scfg ),`
453			`.ncfg ( ncfg )`
454			`) ;`
455
456
457			`sdm_sch #(.VCN(VCN))`
458			`ALLOC (`
459			`.sack ( sack ),`
460			`.wack ( wack ),`
461			`.nack ( nack ),`
462			`.eack ( eack ),`
463			`.lack ( lack ),`
464			`.scfg ( scfg ),`
465			`.ncfg ( ncfg ),`
466			`.wcfg ( wcfg ),`
467			`.ecfg ( ecfg ),`
468			`.lcfg ( lcfg ),`
469			`.sreq ( sreq ),`
470			`.nreq ( nreq ),`
471			`.lreq ( lreq ),`
472			`.wreq ( wreq ),`
473	19	wsong0210	`.ereq ( ereq ),`
474			`.rst_n ( rst_n )`
475	13	wsong0210	`);`
476			`endif
477
478			`endmodule // router`

Browse

Tools

Subversion Repositories async_sdm_noc

[/] [async_sdm_noc/] [branches/] [clos_opt/] [clos_opt/] [src/] [router.v] - Blame information for rev 75