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tobil |
--------------------------------------------------------------------------------
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Release 11.1 Trace (nt)
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Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
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C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
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C:/EDAptability/coremultiplier/reference/avr/ise/ise_s3/ise_s3/ise_s3.ise
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-intstyle ise -v 3 -s 4 -fastpaths -xml avr_core.twx avr_core.ncd -o
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avr_core.twr avr_core.pcf -ucf avr_core.ucf
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Design file: avr_core.ncd
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Physical constraint file: avr_core.pcf
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Device,package,speed: xc3s200a,fg320,-4 (PRODUCTION 1.41 2009-03-03)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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================================================================================
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Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 24 ns HIGH 50%;
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128661977 paths analyzed, 1314 endpoints analyzed, 47 failing endpoints
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47 timing errors detected. (47 setup errors, 0 hold errors, 0 component switching limit errors)
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Minimum period is 24.997ns.
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--------------------------------------------------------------------------------
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Slack (setup path): -0.997ns (requirement - (data path - clock path skew + uncertainty))
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Source: pm_fetch_dec_Inst/nirq_st0 (FF)
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Destination: pm_fetch_dec_Inst/pc_high_5 (FF)
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Requirement: 24.000ns
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Data Path Delay: 24.914ns (Levels of Logic = 16)
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Clock Path Skew: -0.083ns (0.588 - 0.671)
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| 41 |
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Source Clock: cp2_BUFGP rising at 0.000ns
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Destination Clock: cp2_BUFGP rising at 24.000ns
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Clock Uncertainty: 0.000ns
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| 44 |
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| 45 |
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Maximum Data Path: pm_fetch_dec_Inst/nirq_st0 to pm_fetch_dec_Inst/pc_high_5
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Location Delay type Delay(ns) Physical Resource
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Logical Resource(s)
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| 48 |
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------------------------------------------------- -------------------
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| 49 |
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SLICE_X6Y29.XQ Tcko 0.631 pm_fetch_dec_Inst/nirq_st0
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pm_fetch_dec_Inst/nirq_st0
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| 51 |
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SLICE_X9Y35.F2 net (fanout=6) 0.828 pm_fetch_dec_Inst/nirq_st0
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| 52 |
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SLICE_X9Y35.COUT Topcyf 1.195 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
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| 53 |
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pm_fetch_dec_Inst/nop_insert_st_wg_lut<0>
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| 54 |
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pm_fetch_dec_Inst/nop_insert_st_wg_cy<0>
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| 55 |
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pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
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| 56 |
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SLICE_X9Y36.CIN net (fanout=1) 0.000 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
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| 57 |
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SLICE_X9Y36.COUT Tbyp 0.130 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
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| 58 |
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pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
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| 59 |
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pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
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| 60 |
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SLICE_X9Y28.G3 net (fanout=13) 1.062 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
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| 61 |
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SLICE_X9Y28.Y Tilo 0.648 pm_fetch_dec_Inst/alu_data_r_in_or0001
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| 62 |
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pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
|
| 63 |
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SLICE_X13Y26.G3 net (fanout=101) 0.773 pm_fetch_dec_Inst/nop_insert_st
|
| 64 |
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SLICE_X13Y26.Y Tilo 0.648 N556
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| 65 |
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pm_fetch_dec_Inst/reg_rd_adr<3>2
|
| 66 |
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SLICE_X18Y26.G2 net (fanout=3) 0.752 pm_fetch_dec_Inst/reg_rd_adr<3>2
|
| 67 |
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SLICE_X18Y26.Y Tilo 0.707 GPRF_Inst/N188
|
| 68 |
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pm_fetch_dec_Inst/reg_rd_adr<3>47_1
|
| 69 |
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SLICE_X16Y28.G4 net (fanout=14) 0.736 pm_fetch_dec_Inst/reg_rd_adr<3>47
|
| 70 |
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SLICE_X16Y28.Y Tilo 0.707 N603
|
| 71 |
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pm_fetch_dec_Inst/reg_rd_adr<2>62_SW1
|
| 72 |
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SLICE_X17Y28.F1 net (fanout=1) 0.173 N843
|
| 73 |
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SLICE_X17Y28.X Tilo 0.643 GPRF_Inst/N158
|
| 74 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<0>1131
|
| 75 |
|
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SLICE_X26Y21.F4 net (fanout=7) 1.335 GPRF_Inst/N158
|
| 76 |
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SLICE_X26Y21.X Tilo 0.692 GPRF_Inst/sg_tmp_rd_data_31<2>150
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| 77 |
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GPRF_Inst/sg_tmp_rd_data_31<2>150
|
| 78 |
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SLICE_X23Y24.F3 net (fanout=1) 0.562 GPRF_Inst/sg_tmp_rd_data_31<2>150
|
| 79 |
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SLICE_X23Y24.X Tilo 0.643 GPRF_Inst/sg_tmp_rd_data_31<2>256
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| 80 |
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GPRF_Inst/sg_tmp_rd_data_31<2>256
|
| 81 |
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SLICE_X20Y20.G2 net (fanout=2) 0.648 GPRF_Inst/sg_tmp_rd_data_31<2>256
|
| 82 |
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SLICE_X20Y20.Y Tilo 0.707 ALU_Inst/incdec_op_carry<2>
|
| 83 |
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GPRF_Inst/sg_tmp_rd_data_31<2>282_1
|
| 84 |
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SLICE_X19Y31.F3 net (fanout=10) 1.134 GPRF_Inst/sg_tmp_rd_data_31<2>282
|
| 85 |
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SLICE_X19Y31.X Tif5x 0.924 BP_Inst/bit_test_mux_out_7_mux0000184
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| 86 |
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BP_Inst/bit_test_mux_out_7_mux0000184_G
|
| 87 |
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BP_Inst/bit_test_mux_out_7_mux0000184
|
| 88 |
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SLICE_X6Y44.F2 net (fanout=2) 1.049 BP_Inst/bit_test_mux_out_7_mux0000184
|
| 89 |
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SLICE_X6Y44.X Tilo 0.692 BP_Inst/N01
|
| 90 |
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BP_Inst/bit_test_mux_out_7_mux00001112
|
| 91 |
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SLICE_X4Y57.G4 net (fanout=9) 1.529 BP_Inst/N01
|
| 92 |
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SLICE_X4Y57.Y Tilo 0.707 pm_fetch_dec_Inst/N2
|
| 93 |
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pm_fetch_dec_Inst/brxx_st_and000011
|
| 94 |
|
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SLICE_X8Y41.F2 net (fanout=13) 1.111 pm_fetch_dec_Inst/cpu_busy_and0000
|
| 95 |
|
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SLICE_X8Y41.X Tilo 0.692 pm_fetch_dec_Inst/brxx_st
|
| 96 |
|
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pm_fetch_dec_Inst/I65_mux0000<0>41
|
| 97 |
|
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SLICE_X6Y60.G4 net (fanout=11) 1.287 pm_fetch_dec_Inst/N87
|
| 98 |
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SLICE_X6Y60.Y Tilo 0.707 pm_fetch_dec_Inst/pc_high<5>
|
| 99 |
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pm_fetch_dec_Inst/I65_mux0000<8>30
|
| 100 |
|
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SLICE_X6Y60.F4 net (fanout=1) 0.060 pm_fetch_dec_Inst/I65_mux0000<8>30/O
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| 101 |
|
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SLICE_X6Y60.CLK Tfck 0.802 pm_fetch_dec_Inst/pc_high<5>
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| 102 |
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pm_fetch_dec_Inst/I65_mux0000<8>40
|
| 103 |
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pm_fetch_dec_Inst/pc_high_5
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| 104 |
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------------------------------------------------- ---------------------------
|
| 105 |
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Total 24.914ns (11.875ns logic, 13.039ns route)
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| 106 |
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(47.7% logic, 52.3% route)
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| 107 |
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| 108 |
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--------------------------------------------------------------------------------
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Slack (setup path): -0.962ns (requirement - (data path - clock path skew + uncertainty))
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| 110 |
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Source: pm_fetch_dec_Inst/push_st (FF)
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| 111 |
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Destination: pm_fetch_dec_Inst/pc_high_5 (FF)
|
| 112 |
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Requirement: 24.000ns
|
| 113 |
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Data Path Delay: 24.879ns (Levels of Logic = 16)
|
| 114 |
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Clock Path Skew: -0.083ns (0.255 - 0.338)
|
| 115 |
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Source Clock: cp2_BUFGP rising at 0.000ns
|
| 116 |
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Destination Clock: cp2_BUFGP rising at 24.000ns
|
| 117 |
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Clock Uncertainty: 0.000ns
|
| 118 |
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| 119 |
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Maximum Data Path: pm_fetch_dec_Inst/push_st to pm_fetch_dec_Inst/pc_high_5
|
| 120 |
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Location Delay type Delay(ns) Physical Resource
|
| 121 |
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Logical Resource(s)
|
| 122 |
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------------------------------------------------- -------------------
|
| 123 |
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SLICE_X8Y36.YQ Tcko 0.676 pm_fetch_dec_Inst/call_st3
|
| 124 |
|
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pm_fetch_dec_Inst/push_st
|
| 125 |
|
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SLICE_X9Y35.G3 net (fanout=4) 0.765 pm_fetch_dec_Inst/push_st
|
| 126 |
|
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SLICE_X9Y35.COUT Topcyg 1.178 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
|
| 127 |
|
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pm_fetch_dec_Inst/nop_insert_st_wg_lut<1>
|
| 128 |
|
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pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
|
| 129 |
|
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SLICE_X9Y36.CIN net (fanout=1) 0.000 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
|
| 130 |
|
|
SLICE_X9Y36.COUT Tbyp 0.130 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
|
| 131 |
|
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pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
|
| 132 |
|
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pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
|
| 133 |
|
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SLICE_X9Y28.G3 net (fanout=13) 1.062 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
|
| 134 |
|
|
SLICE_X9Y28.Y Tilo 0.648 pm_fetch_dec_Inst/alu_data_r_in_or0001
|
| 135 |
|
|
pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
|
| 136 |
|
|
SLICE_X13Y26.G3 net (fanout=101) 0.773 pm_fetch_dec_Inst/nop_insert_st
|
| 137 |
|
|
SLICE_X13Y26.Y Tilo 0.648 N556
|
| 138 |
|
|
pm_fetch_dec_Inst/reg_rd_adr<3>2
|
| 139 |
|
|
SLICE_X18Y26.G2 net (fanout=3) 0.752 pm_fetch_dec_Inst/reg_rd_adr<3>2
|
| 140 |
|
|
SLICE_X18Y26.Y Tilo 0.707 GPRF_Inst/N188
|
| 141 |
|
|
pm_fetch_dec_Inst/reg_rd_adr<3>47_1
|
| 142 |
|
|
SLICE_X16Y28.G4 net (fanout=14) 0.736 pm_fetch_dec_Inst/reg_rd_adr<3>47
|
| 143 |
|
|
SLICE_X16Y28.Y Tilo 0.707 N603
|
| 144 |
|
|
pm_fetch_dec_Inst/reg_rd_adr<2>62_SW1
|
| 145 |
|
|
SLICE_X17Y28.F1 net (fanout=1) 0.173 N843
|
| 146 |
|
|
SLICE_X17Y28.X Tilo 0.643 GPRF_Inst/N158
|
| 147 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<0>1131
|
| 148 |
|
|
SLICE_X26Y21.F4 net (fanout=7) 1.335 GPRF_Inst/N158
|
| 149 |
|
|
SLICE_X26Y21.X Tilo 0.692 GPRF_Inst/sg_tmp_rd_data_31<2>150
|
| 150 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<2>150
|
| 151 |
|
|
SLICE_X23Y24.F3 net (fanout=1) 0.562 GPRF_Inst/sg_tmp_rd_data_31<2>150
|
| 152 |
|
|
SLICE_X23Y24.X Tilo 0.643 GPRF_Inst/sg_tmp_rd_data_31<2>256
|
| 153 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<2>256
|
| 154 |
|
|
SLICE_X20Y20.G2 net (fanout=2) 0.648 GPRF_Inst/sg_tmp_rd_data_31<2>256
|
| 155 |
|
|
SLICE_X20Y20.Y Tilo 0.707 ALU_Inst/incdec_op_carry<2>
|
| 156 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<2>282_1
|
| 157 |
|
|
SLICE_X19Y31.F3 net (fanout=10) 1.134 GPRF_Inst/sg_tmp_rd_data_31<2>282
|
| 158 |
|
|
SLICE_X19Y31.X Tif5x 0.924 BP_Inst/bit_test_mux_out_7_mux0000184
|
| 159 |
|
|
BP_Inst/bit_test_mux_out_7_mux0000184_G
|
| 160 |
|
|
BP_Inst/bit_test_mux_out_7_mux0000184
|
| 161 |
|
|
SLICE_X6Y44.F2 net (fanout=2) 1.049 BP_Inst/bit_test_mux_out_7_mux0000184
|
| 162 |
|
|
SLICE_X6Y44.X Tilo 0.692 BP_Inst/N01
|
| 163 |
|
|
BP_Inst/bit_test_mux_out_7_mux00001112
|
| 164 |
|
|
SLICE_X4Y57.G4 net (fanout=9) 1.529 BP_Inst/N01
|
| 165 |
|
|
SLICE_X4Y57.Y Tilo 0.707 pm_fetch_dec_Inst/N2
|
| 166 |
|
|
pm_fetch_dec_Inst/brxx_st_and000011
|
| 167 |
|
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SLICE_X8Y41.F2 net (fanout=13) 1.111 pm_fetch_dec_Inst/cpu_busy_and0000
|
| 168 |
|
|
SLICE_X8Y41.X Tilo 0.692 pm_fetch_dec_Inst/brxx_st
|
| 169 |
|
|
pm_fetch_dec_Inst/I65_mux0000<0>41
|
| 170 |
|
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SLICE_X6Y60.G4 net (fanout=11) 1.287 pm_fetch_dec_Inst/N87
|
| 171 |
|
|
SLICE_X6Y60.Y Tilo 0.707 pm_fetch_dec_Inst/pc_high<5>
|
| 172 |
|
|
pm_fetch_dec_Inst/I65_mux0000<8>30
|
| 173 |
|
|
SLICE_X6Y60.F4 net (fanout=1) 0.060 pm_fetch_dec_Inst/I65_mux0000<8>30/O
|
| 174 |
|
|
SLICE_X6Y60.CLK Tfck 0.802 pm_fetch_dec_Inst/pc_high<5>
|
| 175 |
|
|
pm_fetch_dec_Inst/I65_mux0000<8>40
|
| 176 |
|
|
pm_fetch_dec_Inst/pc_high_5
|
| 177 |
|
|
------------------------------------------------- ---------------------------
|
| 178 |
|
|
Total 24.879ns (11.903ns logic, 12.976ns route)
|
| 179 |
|
|
(47.8% logic, 52.2% route)
|
| 180 |
|
|
|
| 181 |
|
|
--------------------------------------------------------------------------------
|
| 182 |
|
|
Slack (setup path): -0.894ns (requirement - (data path - clock path skew + uncertainty))
|
| 183 |
|
|
Source: pm_fetch_dec_Inst/nirq_st0 (FF)
|
| 184 |
|
|
Destination: pm_fetch_dec_Inst/pc_high_5 (FF)
|
| 185 |
|
|
Requirement: 24.000ns
|
| 186 |
|
|
Data Path Delay: 24.811ns (Levels of Logic = 16)
|
| 187 |
|
|
Clock Path Skew: -0.083ns (0.588 - 0.671)
|
| 188 |
|
|
Source Clock: cp2_BUFGP rising at 0.000ns
|
| 189 |
|
|
Destination Clock: cp2_BUFGP rising at 24.000ns
|
| 190 |
|
|
Clock Uncertainty: 0.000ns
|
| 191 |
|
|
|
| 192 |
|
|
Maximum Data Path: pm_fetch_dec_Inst/nirq_st0 to pm_fetch_dec_Inst/pc_high_5
|
| 193 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 194 |
|
|
Logical Resource(s)
|
| 195 |
|
|
------------------------------------------------- -------------------
|
| 196 |
|
|
SLICE_X6Y29.XQ Tcko 0.631 pm_fetch_dec_Inst/nirq_st0
|
| 197 |
|
|
pm_fetch_dec_Inst/nirq_st0
|
| 198 |
|
|
SLICE_X9Y35.F2 net (fanout=6) 0.828 pm_fetch_dec_Inst/nirq_st0
|
| 199 |
|
|
SLICE_X9Y35.COUT Topcyf 1.195 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
|
| 200 |
|
|
pm_fetch_dec_Inst/nop_insert_st_wg_lut<0>
|
| 201 |
|
|
pm_fetch_dec_Inst/nop_insert_st_wg_cy<0>
|
| 202 |
|
|
pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
|
| 203 |
|
|
SLICE_X9Y36.CIN net (fanout=1) 0.000 pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
|
| 204 |
|
|
SLICE_X9Y36.COUT Tbyp 0.130 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
|
| 205 |
|
|
pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
|
| 206 |
|
|
pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
|
| 207 |
|
|
SLICE_X9Y28.G3 net (fanout=13) 1.062 pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
|
| 208 |
|
|
SLICE_X9Y28.Y Tilo 0.648 pm_fetch_dec_Inst/alu_data_r_in_or0001
|
| 209 |
|
|
pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>1
|
| 210 |
|
|
SLICE_X10Y27.F3 net (fanout=101) 0.590 pm_fetch_dec_Inst/nop_insert_st
|
| 211 |
|
|
SLICE_X10Y27.X Tilo 0.692 pm_fetch_dec_Inst/reg_rd_adr<0>23
|
| 212 |
|
|
pm_fetch_dec_Inst/reg_rd_adr<0>23
|
| 213 |
|
|
SLICE_X18Y26.G4 net (fanout=9) 0.788 pm_fetch_dec_Inst/reg_rd_adr<0>23
|
| 214 |
|
|
SLICE_X18Y26.Y Tilo 0.707 GPRF_Inst/N188
|
| 215 |
|
|
pm_fetch_dec_Inst/reg_rd_adr<3>47_1
|
| 216 |
|
|
SLICE_X16Y28.G4 net (fanout=14) 0.736 pm_fetch_dec_Inst/reg_rd_adr<3>47
|
| 217 |
|
|
SLICE_X16Y28.Y Tilo 0.707 N603
|
| 218 |
|
|
pm_fetch_dec_Inst/reg_rd_adr<2>62_SW1
|
| 219 |
|
|
SLICE_X17Y28.F1 net (fanout=1) 0.173 N843
|
| 220 |
|
|
SLICE_X17Y28.X Tilo 0.643 GPRF_Inst/N158
|
| 221 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<0>1131
|
| 222 |
|
|
SLICE_X26Y21.F4 net (fanout=7) 1.335 GPRF_Inst/N158
|
| 223 |
|
|
SLICE_X26Y21.X Tilo 0.692 GPRF_Inst/sg_tmp_rd_data_31<2>150
|
| 224 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<2>150
|
| 225 |
|
|
SLICE_X23Y24.F3 net (fanout=1) 0.562 GPRF_Inst/sg_tmp_rd_data_31<2>150
|
| 226 |
|
|
SLICE_X23Y24.X Tilo 0.643 GPRF_Inst/sg_tmp_rd_data_31<2>256
|
| 227 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<2>256
|
| 228 |
|
|
SLICE_X20Y20.G2 net (fanout=2) 0.648 GPRF_Inst/sg_tmp_rd_data_31<2>256
|
| 229 |
|
|
SLICE_X20Y20.Y Tilo 0.707 ALU_Inst/incdec_op_carry<2>
|
| 230 |
|
|
GPRF_Inst/sg_tmp_rd_data_31<2>282_1
|
| 231 |
|
|
SLICE_X19Y31.F3 net (fanout=10) 1.134 GPRF_Inst/sg_tmp_rd_data_31<2>282
|
| 232 |
|
|
SLICE_X19Y31.X Tif5x 0.924 BP_Inst/bit_test_mux_out_7_mux0000184
|
| 233 |
|
|
BP_Inst/bit_test_mux_out_7_mux0000184_G
|
| 234 |
|
|
BP_Inst/bit_test_mux_out_7_mux0000184
|
| 235 |
|
|
SLICE_X6Y44.F2 net (fanout=2) 1.049 BP_Inst/bit_test_mux_out_7_mux0000184
|
| 236 |
|
|
SLICE_X6Y44.X Tilo 0.692 BP_Inst/N01
|
| 237 |
|
|
BP_Inst/bit_test_mux_out_7_mux00001112
|
| 238 |
|
|
SLICE_X4Y57.G4 net (fanout=9) 1.529 BP_Inst/N01
|
| 239 |
|
|
SLICE_X4Y57.Y Tilo 0.707 pm_fetch_dec_Inst/N2
|
| 240 |
|
|
pm_fetch_dec_Inst/brxx_st_and000011
|
| 241 |
|
|
SLICE_X8Y41.F2 net (fanout=13) 1.111 pm_fetch_dec_Inst/cpu_busy_and0000
|
| 242 |
|
|
SLICE_X8Y41.X Tilo 0.692 pm_fetch_dec_Inst/brxx_st
|
| 243 |
|
|
pm_fetch_dec_Inst/I65_mux0000<0>41
|
| 244 |
|
|
SLICE_X6Y60.G4 net (fanout=11) 1.287 pm_fetch_dec_Inst/N87
|
| 245 |
|
|
SLICE_X6Y60.Y Tilo 0.707 pm_fetch_dec_Inst/pc_high<5>
|
| 246 |
|
|
pm_fetch_dec_Inst/I65_mux0000<8>30
|
| 247 |
|
|
SLICE_X6Y60.F4 net (fanout=1) 0.060 pm_fetch_dec_Inst/I65_mux0000<8>30/O
|
| 248 |
|
|
SLICE_X6Y60.CLK Tfck 0.802 pm_fetch_dec_Inst/pc_high<5>
|
| 249 |
|
|
pm_fetch_dec_Inst/I65_mux0000<8>40
|
| 250 |
|
|
pm_fetch_dec_Inst/pc_high_5
|
| 251 |
|
|
------------------------------------------------- ---------------------------
|
| 252 |
|
|
Total 24.811ns (11.919ns logic, 12.892ns route)
|
| 253 |
|
|
(48.0% logic, 52.0% route)
|
| 254 |
|
|
|
| 255 |
|
|
--------------------------------------------------------------------------------
|
| 256 |
|
|
|
| 257 |
|
|
Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 24 ns HIGH 50%;
|
| 258 |
|
|
--------------------------------------------------------------------------------
|
| 259 |
|
|
Slack (hold path): 0.973ns (requirement - (clock path skew + uncertainty - data path))
|
| 260 |
|
|
Source: pm_fetch_dec_Inst/pc_high_1 (FF)
|
| 261 |
|
|
Destination: pm_fetch_dec_Inst/program_counter_tmp_9 (FF)
|
| 262 |
|
|
Requirement: 0.000ns
|
| 263 |
|
|
Data Path Delay: 1.003ns (Levels of Logic = 0)
|
| 264 |
|
|
Clock Path Skew: 0.030ns (0.281 - 0.251)
|
| 265 |
|
|
Source Clock: cp2_BUFGP rising at 24.000ns
|
| 266 |
|
|
Destination Clock: cp2_BUFGP rising at 24.000ns
|
| 267 |
|
|
Clock Uncertainty: 0.000ns
|
| 268 |
|
|
|
| 269 |
|
|
Minimum Data Path: pm_fetch_dec_Inst/pc_high_1 to pm_fetch_dec_Inst/program_counter_tmp_9
|
| 270 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 271 |
|
|
Logical Resource(s)
|
| 272 |
|
|
------------------------------------------------- -------------------
|
| 273 |
|
|
SLICE_X7Y59.XQ Tcko 0.473 pm_fetch_dec_Inst/pc_high<1>
|
| 274 |
|
|
pm_fetch_dec_Inst/pc_high_1
|
| 275 |
|
|
SLICE_X4Y61.BX net (fanout=7) 0.392 pm_fetch_dec_Inst/pc_high<1>
|
| 276 |
|
|
SLICE_X4Y61.CLK Tckdi (-Th) -0.138 pm_fetch_dec_Inst/program_counter_tmp<9>
|
| 277 |
|
|
pm_fetch_dec_Inst/program_counter_tmp_9
|
| 278 |
|
|
------------------------------------------------- ---------------------------
|
| 279 |
|
|
Total 1.003ns (0.611ns logic, 0.392ns route)
|
| 280 |
|
|
(60.9% logic, 39.1% route)
|
| 281 |
|
|
|
| 282 |
|
|
--------------------------------------------------------------------------------
|
| 283 |
|
|
Slack (hold path): 1.056ns (requirement - (clock path skew + uncertainty - data path))
|
| 284 |
|
|
Source: pm_fetch_dec_Inst/pc_high_5 (FF)
|
| 285 |
|
|
Destination: pm_fetch_dec_Inst/program_counter_tmp_13 (FF)
|
| 286 |
|
|
Requirement: 0.000ns
|
| 287 |
|
|
Data Path Delay: 1.067ns (Levels of Logic = 0)
|
| 288 |
|
|
Clock Path Skew: 0.011ns (0.065 - 0.054)
|
| 289 |
|
|
Source Clock: cp2_BUFGP rising at 24.000ns
|
| 290 |
|
|
Destination Clock: cp2_BUFGP rising at 24.000ns
|
| 291 |
|
|
Clock Uncertainty: 0.000ns
|
| 292 |
|
|
|
| 293 |
|
|
Minimum Data Path: pm_fetch_dec_Inst/pc_high_5 to pm_fetch_dec_Inst/program_counter_tmp_13
|
| 294 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 295 |
|
|
Logical Resource(s)
|
| 296 |
|
|
------------------------------------------------- -------------------
|
| 297 |
|
|
SLICE_X6Y60.XQ Tcko 0.505 pm_fetch_dec_Inst/pc_high<5>
|
| 298 |
|
|
pm_fetch_dec_Inst/pc_high_5
|
| 299 |
|
|
SLICE_X6Y63.BX net (fanout=5) 0.424 pm_fetch_dec_Inst/pc_high<5>
|
| 300 |
|
|
SLICE_X6Y63.CLK Tckdi (-Th) -0.138 pm_fetch_dec_Inst/program_counter_tmp<13>
|
| 301 |
|
|
pm_fetch_dec_Inst/program_counter_tmp_13
|
| 302 |
|
|
------------------------------------------------- ---------------------------
|
| 303 |
|
|
Total 1.067ns (0.643ns logic, 0.424ns route)
|
| 304 |
|
|
(60.3% logic, 39.7% route)
|
| 305 |
|
|
|
| 306 |
|
|
--------------------------------------------------------------------------------
|
| 307 |
|
|
Slack (hold path): 1.065ns (requirement - (clock path skew + uncertainty - data path))
|
| 308 |
|
|
Source: pm_fetch_dec_Inst/ramwe_int (FF)
|
| 309 |
|
|
Destination: pm_fetch_dec_Inst/ramwe_int (FF)
|
| 310 |
|
|
Requirement: 0.000ns
|
| 311 |
|
|
Data Path Delay: 1.065ns (Levels of Logic = 0)
|
| 312 |
|
|
Clock Path Skew: 0.000ns
|
| 313 |
|
|
Source Clock: cp2_BUFGP rising at 24.000ns
|
| 314 |
|
|
Destination Clock: cp2_BUFGP rising at 24.000ns
|
| 315 |
|
|
Clock Uncertainty: 0.000ns
|
| 316 |
|
|
|
| 317 |
|
|
Minimum Data Path: pm_fetch_dec_Inst/ramwe_int to pm_fetch_dec_Inst/ramwe_int
|
| 318 |
|
|
Location Delay type Delay(ns) Physical Resource
|
| 319 |
|
|
Logical Resource(s)
|
| 320 |
|
|
------------------------------------------------- -------------------
|
| 321 |
|
|
SLICE_X1Y32.YQ Tcko 0.464 pm_fetch_dec_Inst/ramwe_int
|
| 322 |
|
|
pm_fetch_dec_Inst/ramwe_int
|
| 323 |
|
|
SLICE_X1Y32.BY net (fanout=4) 0.461 pm_fetch_dec_Inst/ramwe_int
|
| 324 |
|
|
SLICE_X1Y32.CLK Tckdi (-Th) -0.140 pm_fetch_dec_Inst/ramwe_int
|
| 325 |
|
|
pm_fetch_dec_Inst/ramwe_int
|
| 326 |
|
|
------------------------------------------------- ---------------------------
|
| 327 |
|
|
Total 1.065ns (0.604ns logic, 0.461ns route)
|
| 328 |
|
|
(56.7% logic, 43.3% route)
|
| 329 |
|
|
|
| 330 |
|
|
--------------------------------------------------------------------------------
|
| 331 |
|
|
|
| 332 |
|
|
Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 24 ns HIGH 50%;
|
| 333 |
|
|
--------------------------------------------------------------------------------
|
| 334 |
|
|
Slack: 20.796ns (period - (min low pulse limit / (low pulse / period)))
|
| 335 |
|
|
Period: 24.000ns
|
| 336 |
|
|
Low pulse: 12.000ns
|
| 337 |
|
|
Low pulse limit: 1.602ns (Trpw)
|
| 338 |
|
|
Physical resource: IORegs_Inst/sreg<2>/SR
|
| 339 |
|
|
Logical resource: IORegs_Inst/sreg_2/SR
|
| 340 |
|
|
Location pin: SLICE_X4Y19.SR
|
| 341 |
|
|
Clock network: ireset_IBUF
|
| 342 |
|
|
--------------------------------------------------------------------------------
|
| 343 |
|
|
Slack: 20.796ns (period - (min high pulse limit / (high pulse / period)))
|
| 344 |
|
|
Period: 24.000ns
|
| 345 |
|
|
High pulse: 12.000ns
|
| 346 |
|
|
High pulse limit: 1.602ns (Trpw)
|
| 347 |
|
|
Physical resource: IORegs_Inst/sreg<2>/SR
|
| 348 |
|
|
Logical resource: IORegs_Inst/sreg_2/SR
|
| 349 |
|
|
Location pin: SLICE_X4Y19.SR
|
| 350 |
|
|
Clock network: ireset_IBUF
|
| 351 |
|
|
--------------------------------------------------------------------------------
|
| 352 |
|
|
Slack: 20.796ns (period - (min low pulse limit / (low pulse / period)))
|
| 353 |
|
|
Period: 24.000ns
|
| 354 |
|
|
Low pulse: 12.000ns
|
| 355 |
|
|
Low pulse limit: 1.602ns (Trpw)
|
| 356 |
|
|
Physical resource: IORegs_Inst/sph<0>/SR
|
| 357 |
|
|
Logical resource: IORegs_Inst/sph_0/SR
|
| 358 |
|
|
Location pin: SLICE_X2Y43.SR
|
| 359 |
|
|
Clock network: ireset_IBUF
|
| 360 |
|
|
--------------------------------------------------------------------------------
|
| 361 |
|
|
|
| 362 |
|
|
|
| 363 |
|
|
1 constraint not met.
|
| 364 |
|
|
|
| 365 |
|
|
|
| 366 |
|
|
Data Sheet report:
|
| 367 |
|
|
-----------------
|
| 368 |
|
|
All values displayed in nanoseconds (ns)
|
| 369 |
|
|
|
| 370 |
|
|
Clock to Setup on destination clock cp2
|
| 371 |
|
|
---------------+---------+---------+---------+---------+
|
| 372 |
|
|
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
| 373 |
|
|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
| 374 |
|
|
---------------+---------+---------+---------+---------+
|
| 375 |
|
|
cp2 | 24.997| | | |
|
| 376 |
|
|
---------------+---------+---------+---------+---------+
|
| 377 |
|
|
|
| 378 |
|
|
|
| 379 |
|
|
Timing summary:
|
| 380 |
|
|
---------------
|
| 381 |
|
|
|
| 382 |
|
|
Timing errors: 47 Score: 18553 (Setup/Max: 18553, Hold: 0)
|
| 383 |
|
|
|
| 384 |
|
|
Constraints cover 128661977 paths, 0 nets, and 7182 connections
|
| 385 |
|
|
|
| 386 |
|
|
Design statistics:
|
| 387 |
|
|
Minimum period: 24.997ns{1} (Maximum frequency: 40.005MHz)
|
| 388 |
|
|
|
| 389 |
|
|
|
| 390 |
|
|
------------------------------------Footnotes-----------------------------------
|
| 391 |
|
|
1) The minimum period statistic assumes all single cycle delays.
|
| 392 |
|
|
|
| 393 |
|
|
Analysis completed Fri Oct 01 23:50:17 2010
|
| 394 |
|
|
--------------------------------------------------------------------------------
|
| 395 |
|
|
|
| 396 |
|
|
Trace Settings:
|
| 397 |
|
|
-------------------------
|
| 398 |
|
|
Trace Settings
|
| 399 |
|
|
|
| 400 |
|
|
Peak Memory Usage: 145 MB
|
| 401 |
|
|
|
| 402 |
|
|
|
| 403 |
|
|
|
