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[/] [avr_hp/] [trunk/] [ise/] [ise_s3_cm4_one/] [avr_core_cm4_top.twr] - Blame information for rev 2

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--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/avr/ise/ise_s3_cm4_one_syneda/ise_s3_cm4_one_syneda/ise_s3_cm4_one_syneda.ise
-intstyle ise -v 3 -s 4 -fastpaths -xml avr_core_cm4_top.twx
avr_core_cm4_top.ncd -o avr_core_cm4_top.twr avr_core_cm4_top.pcf -ucf
avr_core_cm4_top.ucf
 
Design file:              avr_core_cm4_top.ncd
Physical constraint file: avr_core_cm4_top.pcf
Device,package,speed:     xc3s200a,fg320,-4 (PRODUCTION 1.41 2009-03-03)
Report level:             verbose report
 
Environment Variable      Effect
--------------------      ------
NONE                      No environment variables were set
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
   a 50 Ohm transmission line loading model.  For the details of this model,
   and for more information on accounting for different loading conditions,
   please see the device datasheet.
 
================================================================================
Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 11.5 ns HIGH 50%;
 
 145500 paths analyzed, 3279 endpoints analyzed, 0 failing endpoints
 
 Minimum period is  11.446ns.
--------------------------------------------------------------------------------
Slack (setup path):     0.054ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_0 (FF)
  Requirement:          11.500ns
  Data Path Delay:      11.290ns (Levels of Logic = 8)
  Clock Path Skew:      -0.156ns (0.566 - 0.722)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns
 
  Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 to AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X19Y23.XQ      Tcko                  0.591   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.G4      net (fanout=2)        1.177   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.COUT    Topcyg                1.178   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<4>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>
    SLICE_X18Y20.G3      net (fanout=51)       1.520   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
    SLICE_X18Y20.Y       Tilo                  0.707   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq0000111
    SLICE_X18Y20.F4      net (fanout=2)        0.131   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N104
    SLICE_X18Y20.X       Tilo                  0.692   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq000011
    SLICE_X19Y20.G4      net (fanout=7)        0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
    SLICE_X19Y20.Y       Tilo                  0.648   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011
    SLICE_X17Y18.G4      net (fanout=7)        0.391   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001
    SLICE_X17Y18.Y       Tilo                  0.648   AVR_Core_cm4_Inst/reg_rd_adr<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0
    SLICE_X17Y18.F3      net (fanout=1)        0.043   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0/O
    SLICE_X17Y18.X       Tilo                  0.643   AVR_Core_cm4_Inst/reg_rd_adr<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47
    SLICE_X15Y8.SR       net (fanout=33)       1.664   AVR_Core_cm4_Inst/reg_rd_adr<3>
    SLICE_X15Y8.CLK      Tsrck                 0.867   AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1<1>
                                                       AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_0
    -------------------------------------------------  ---------------------------
    Total                                     11.290ns (6.234ns logic, 5.056ns route)
                                                       (55.2% logic, 44.8% route)
 
--------------------------------------------------------------------------------
Slack (setup path):     0.054ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_1 (FF)
  Requirement:          11.500ns
  Data Path Delay:      11.290ns (Levels of Logic = 8)
  Clock Path Skew:      -0.156ns (0.566 - 0.722)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns
 
  Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 to AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X19Y23.XQ      Tcko                  0.591   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.G4      net (fanout=2)        1.177   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.COUT    Topcyg                1.178   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<4>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>
    SLICE_X18Y20.G3      net (fanout=51)       1.520   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
    SLICE_X18Y20.Y       Tilo                  0.707   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq0000111
    SLICE_X18Y20.F4      net (fanout=2)        0.131   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N104
    SLICE_X18Y20.X       Tilo                  0.692   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq000011
    SLICE_X19Y20.G4      net (fanout=7)        0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
    SLICE_X19Y20.Y       Tilo                  0.648   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011
    SLICE_X17Y18.G4      net (fanout=7)        0.391   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001
    SLICE_X17Y18.Y       Tilo                  0.648   AVR_Core_cm4_Inst/reg_rd_adr<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0
    SLICE_X17Y18.F3      net (fanout=1)        0.043   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0/O
    SLICE_X17Y18.X       Tilo                  0.643   AVR_Core_cm4_Inst/reg_rd_adr<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47
    SLICE_X15Y8.SR       net (fanout=33)       1.664   AVR_Core_cm4_Inst/reg_rd_adr<3>
    SLICE_X15Y8.CLK      Tsrck                 0.867   AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1<1>
                                                       AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_1
    -------------------------------------------------  ---------------------------
    Total                                     11.290ns (6.234ns logic, 5.056ns route)
                                                       (55.2% logic, 44.8% route)
 
--------------------------------------------------------------------------------
Slack (setup path):     0.061ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_18 (FF)
  Requirement:          11.500ns
  Data Path Delay:      11.266ns (Levels of Logic = 9)
  Clock Path Skew:      -0.173ns (0.549 - 0.722)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns
 
  Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 to AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_18
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X19Y23.XQ      Tcko                  0.591   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.G4      net (fanout=2)        1.177   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0
    SLICE_X21Y28.COUT    Topcyg                1.178   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<1>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>
    SLICE_X21Y29.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.CIN     net (fanout=1)        0.000   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>
    SLICE_X21Y30.COUT    Tbyp                  0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<4>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>
    SLICE_X18Y20.G3      net (fanout=51)       1.520   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st
    SLICE_X18Y20.Y       Tilo                  0.707   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq0000111
    SLICE_X18Y20.F4      net (fanout=2)        0.131   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N104
    SLICE_X18Y20.X       Tilo                  0.692   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq000011
    SLICE_X19Y20.G4      net (fanout=7)        0.130   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69
    SLICE_X19Y20.Y       Tilo                  0.648   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011
    SLICE_X14Y14.G2      net (fanout=7)        0.855   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001
    SLICE_X14Y14.Y       Tilo                  0.707   AVR_Core_cm4_Inst/reg_rd_adr<0>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<0>47
    SLICE_X14Y14.F4      net (fanout=3)        0.077   AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<0>47
    SLICE_X14Y14.X       Tilo                  0.692   AVR_Core_cm4_Inst/reg_rd_adr<0>
                                                       AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<0>56
    SLICE_X11Y15.G1      net (fanout=45)       1.174   AVR_Core_cm4_Inst/reg_rd_adr<0>
    SLICE_X11Y15.CLK     Tgck                  0.727   AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1<19>
                                                       AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_18_cmp_eq000011
                                                       AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_18
    -------------------------------------------------  ---------------------------
    Total                                     11.266ns (6.202ns logic, 5.064ns route)
                                                       (55.1% logic, 44.9% route)
 
--------------------------------------------------------------------------------
 
Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 11.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.601ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_16_7/SRL16E (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.708ns (Levels of Logic = 1)
  Clock Path Skew:      0.107ns (0.337 - 0.230)
  Source Clock:         cp2_BUFGP rising at 11.500ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns
 
  Minimum Data Path: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7 to AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_16_7/SRL16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X9Y22.XQ       Tcko                  0.473   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7
                                                       AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7
    SLICE_X6Y23.BX       net (fanout=2)        0.381   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7
    SLICE_X6Y23.CLK      Tdh         (-Th)     0.146   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_16_7
                                                       AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_16_7/SRL16E
    -------------------------------------------------  ---------------------------
    Total                                      0.708ns (0.327ns logic, 0.381ns route)
                                                       (46.2% logic, 53.8% route)
 
--------------------------------------------------------------------------------
Slack (hold path):      0.601ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_21_0/SRL16E (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.715ns (Levels of Logic = 1)
  Clock Path Skew:      0.114ns (0.430 - 0.316)
  Source Clock:         cp2_BUFGP rising at 11.500ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns
 
  Minimum Data Path: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0 to AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_21_0/SRL16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X3Y35.YQ       Tcko                  0.464   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_1
                                                       AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0
    SLICE_X0Y34.BY       net (fanout=2)        0.377   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0
    SLICE_X0Y34.CLK      Tdh         (-Th)     0.126   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_21_1
                                                       AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_21_0/SRL16E
    -------------------------------------------------  ---------------------------
    Total                                      0.715ns (0.338ns logic, 0.377ns route)
                                                       (47.3% logic, 52.7% route)
 
--------------------------------------------------------------------------------
Slack (hold path):      0.610ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5 (FF)
  Destination:          AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_19_5/SRL16E (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.746ns (Levels of Logic = 1)
  Clock Path Skew:      0.136ns (0.375 - 0.239)
  Source Clock:         cp2_BUFGP rising at 11.500ns
  Destination Clock:    cp2_BUFGP rising at 11.500ns
  Clock Uncertainty:    0.000ns
 
  Minimum Data Path: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5 to AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_19_5/SRL16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X8Y26.XQ       Tcko                  0.505   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5
                                                       AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5
    SLICE_X6Y26.BX       net (fanout=2)        0.387   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5
    SLICE_X6Y26.CLK      Tdh         (-Th)     0.146   AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_19_5
                                                       AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_19_5/SRL16E
    -------------------------------------------------  ---------------------------
    Total                                      0.746ns (0.359ns logic, 0.387ns route)
                                                       (48.1% logic, 51.9% route)
 
--------------------------------------------------------------------------------
 
Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 11.5 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 8.296ns (period - (min low pulse limit / (low pulse / period)))
  Period: 11.500ns
  Low pulse: 5.750ns
  Low pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR
  Logical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR
  Location pin: SLICE_X28Y46.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------
Slack: 8.296ns (period - (min high pulse limit / (high pulse / period)))
  Period: 11.500ns
  High pulse: 5.750ns
  High pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR
  Logical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR
  Location pin: SLICE_X28Y46.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------
Slack: 8.296ns (period - (min low pulse limit / (low pulse / period)))
  Period: 11.500ns
  Low pulse: 5.750ns
  Low pulse limit: 1.602ns (Trpw)
  Physical resource: AVR_Core_cm4_Inst/GPRF_Inst/r29h<0>/SR
  Logical resource: AVR_Core_cm4_Inst/GPRF_Inst/r29h_0/SR
  Location pin: SLICE_X2Y60.SR
  Clock network: ireset_IBUF
--------------------------------------------------------------------------------
 
 
All constraints were met.
 
 
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
 
Clock to Setup on destination clock cp2
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cp2            |   11.446|         |         |         |
---------------+---------+---------+---------+---------+
 
 
Timing summary:
---------------
 
Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)
 
Constraints cover 145500 paths, 0 nets, and 9529 connections
 
Design statistics:
   Minimum period:  11.446ns{1}   (Maximum frequency:  87.367MHz)
 
 
------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.
 
Analysis completed Sun Oct 03 11:38:16 2010
--------------------------------------------------------------------------------
 
Trace Settings:
-------------------------
Trace Settings
 
Peak Memory Usage: 163 MB
 
 
 

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[/] [avr_hp/] [trunk/] [ise/] [ise_s3_cm4_one/] [avr_core_cm4_top.twr] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`--------------------------------------------------------------------------------`
2			`Release 11.1 Trace (nt)`
3			`Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.`
4
5			`C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise`
6			`C:/EDAptability/coremultiplier/reference/avr/ise/ise_s3_cm4_one_syneda/ise_s3_cm4_one_syneda/ise_s3_cm4_one_syneda.ise`
7			`-intstyle ise -v 3 -s 4 -fastpaths -xml avr_core_cm4_top.twx`
8			`avr_core_cm4_top.ncd -o avr_core_cm4_top.twr avr_core_cm4_top.pcf -ucf`
9			`avr_core_cm4_top.ucf`
10
11			`Design file: avr_core_cm4_top.ncd`
12			`Physical constraint file: avr_core_cm4_top.pcf`
13			`Device,package,speed: xc3s200a,fg320,-4 (PRODUCTION 1.41 2009-03-03)`
14			`Report level: verbose report`
15
16			`Environment Variable Effect`
17			`-------------------- ------`
18			`NONE No environment variables were set`
19			`--------------------------------------------------------------------------------`
20
21			`INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths`
22			`option. All paths that are not constrained will be reported in the`
23			`unconstrained paths section(s) of the report.`
24			`INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on`
25			`a 50 Ohm transmission line loading model. For the details of this model,`
26			`and for more information on accounting for different loading conditions,`
27			`please see the device datasheet.`
28
29			`================================================================================`
30			`Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 11.5 ns HIGH 50%;`
31
32			`145500 paths analyzed, 3279 endpoints analyzed, 0 failing endpoints`
33
34			`Minimum period is 11.446ns.`
35			`--------------------------------------------------------------------------------`
36			`Slack (setup path): 0.054ns (requirement - (data path - clock path skew + uncertainty))`
37			`Source: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 (FF)`
38			`Destination: AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_0 (FF)`
39			`Requirement: 11.500ns`
40			`Data Path Delay: 11.290ns (Levels of Logic = 8)`
41			`Clock Path Skew: -0.156ns (0.566 - 0.722)`
42			`Source Clock: cp2_BUFGP rising at 0.000ns`
43			`Destination Clock: cp2_BUFGP rising at 11.500ns`
44			`Clock Uncertainty: 0.000ns`
45
46			`Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 to AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_0`
47			`Location Delay type Delay(ns) Physical Resource`
48			`Logical Resource(s)`
49			`------------------------------------------------- -------------------`
50			`SLICE_X19Y23.XQ Tcko 0.591 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0`
51			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0`
52			`SLICE_X21Y28.G4 net (fanout=2) 1.177 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0`
53			`SLICE_X21Y28.COUT Topcyg 1.178 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>`
54			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<1>`
55			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>`
56			`SLICE_X21Y29.CIN net (fanout=1) 0.000 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>`
57			`SLICE_X21Y29.COUT Tbyp 0.130 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>`
58			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>`
59			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>`
60			`SLICE_X21Y30.CIN net (fanout=1) 0.000 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>`
61			`SLICE_X21Y30.COUT Tbyp 0.130 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st`
62			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<4>`
63			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>`
64			`SLICE_X18Y20.G3 net (fanout=51) 1.520 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st`
65			`SLICE_X18Y20.Y Tilo 0.707 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69`
66			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq0000111`
67			`SLICE_X18Y20.F4 net (fanout=2) 0.131 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N104`
68			`SLICE_X18Y20.X Tilo 0.692 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69`
69			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq000011`
70			`SLICE_X19Y20.G4 net (fanout=7) 0.130 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69`
71			`SLICE_X19Y20.Y Tilo 0.648 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1`
72			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011`
73			`SLICE_X17Y18.G4 net (fanout=7) 0.391 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001`
74			`SLICE_X17Y18.Y Tilo 0.648 AVR_Core_cm4_Inst/reg_rd_adr<3>`
75			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0`
76			`SLICE_X17Y18.F3 net (fanout=1) 0.043 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0/O`
77			`SLICE_X17Y18.X Tilo 0.643 AVR_Core_cm4_Inst/reg_rd_adr<3>`
78			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47`
79			`SLICE_X15Y8.SR net (fanout=33) 1.664 AVR_Core_cm4_Inst/reg_rd_adr<3>`
80			`SLICE_X15Y8.CLK Tsrck 0.867 AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1<1>`
81			`AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_0`
82			`------------------------------------------------- ---------------------------`
83			`Total 11.290ns (6.234ns logic, 5.056ns route)`
84			`(55.2% logic, 44.8% route)`
85
86			`--------------------------------------------------------------------------------`
87			`Slack (setup path): 0.054ns (requirement - (data path - clock path skew + uncertainty))`
88			`Source: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 (FF)`
89			`Destination: AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_1 (FF)`
90			`Requirement: 11.500ns`
91			`Data Path Delay: 11.290ns (Levels of Logic = 8)`
92			`Clock Path Skew: -0.156ns (0.566 - 0.722)`
93			`Source Clock: cp2_BUFGP rising at 0.000ns`
94			`Destination Clock: cp2_BUFGP rising at 11.500ns`
95			`Clock Uncertainty: 0.000ns`
96
97			`Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 to AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_1`
98			`Location Delay type Delay(ns) Physical Resource`
99			`Logical Resource(s)`
100			`------------------------------------------------- -------------------`
101			`SLICE_X19Y23.XQ Tcko 0.591 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0`
102			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0`
103			`SLICE_X21Y28.G4 net (fanout=2) 1.177 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0`
104			`SLICE_X21Y28.COUT Topcyg 1.178 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>`
105			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<1>`
106			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>`
107			`SLICE_X21Y29.CIN net (fanout=1) 0.000 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>`
108			`SLICE_X21Y29.COUT Tbyp 0.130 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>`
109			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>`
110			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>`
111			`SLICE_X21Y30.CIN net (fanout=1) 0.000 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>`
112			`SLICE_X21Y30.COUT Tbyp 0.130 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st`
113			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<4>`
114			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>`
115			`SLICE_X18Y20.G3 net (fanout=51) 1.520 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st`
116			`SLICE_X18Y20.Y Tilo 0.707 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69`
117			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq0000111`
118			`SLICE_X18Y20.F4 net (fanout=2) 0.131 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N104`
119			`SLICE_X18Y20.X Tilo 0.692 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69`
120			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq000011`
121			`SLICE_X19Y20.G4 net (fanout=7) 0.130 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69`
122			`SLICE_X19Y20.Y Tilo 0.648 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1`
123			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011`
124			`SLICE_X17Y18.G4 net (fanout=7) 0.391 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001`
125			`SLICE_X17Y18.Y Tilo 0.648 AVR_Core_cm4_Inst/reg_rd_adr<3>`
126			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0`
127			`SLICE_X17Y18.F3 net (fanout=1) 0.043 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47_SW0/O`
128			`SLICE_X17Y18.X Tilo 0.643 AVR_Core_cm4_Inst/reg_rd_adr<3>`
129			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<3>47`
130			`SLICE_X15Y8.SR net (fanout=33) 1.664 AVR_Core_cm4_Inst/reg_rd_adr<3>`
131			`SLICE_X15Y8.CLK Tsrck 0.867 AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1<1>`
132			`AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_1`
133			`------------------------------------------------- ---------------------------`
134			`Total 11.290ns (6.234ns logic, 5.056ns route)`
135			`(55.2% logic, 44.8% route)`
136
137			`--------------------------------------------------------------------------------`
138			`Slack (setup path): 0.061ns (requirement - (data path - clock path skew + uncertainty))`
139			`Source: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 (FF)`
140			`Destination: AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_18 (FF)`
141			`Requirement: 11.500ns`
142			`Data Path Delay: 11.266ns (Levels of Logic = 9)`
143			`Clock Path Skew: -0.173ns (0.549 - 0.722)`
144			`Source Clock: cp2_BUFGP rising at 0.000ns`
145			`Destination Clock: cp2_BUFGP rising at 11.500ns`
146			`Clock Uncertainty: 0.000ns`
147
148			`Maximum Data Path: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0 to AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_18`
149			`Location Delay type Delay(ns) Physical Resource`
150			`Logical Resource(s)`
151			`------------------------------------------------- -------------------`
152			`SLICE_X19Y23.XQ Tcko 0.591 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0`
153			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0`
154			`SLICE_X21Y28.G4 net (fanout=2) 1.177 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ncall_st0`
155			`SLICE_X21Y28.COUT Topcyg 1.178 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>`
156			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_lut<1>`
157			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>`
158			`SLICE_X21Y29.CIN net (fanout=1) 0.000 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<1>`
159			`SLICE_X21Y29.COUT Tbyp 0.130 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>`
160			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<2>`
161			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>`
162			`SLICE_X21Y30.CIN net (fanout=1) 0.000 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<3>`
163			`SLICE_X21Y30.COUT Tbyp 0.130 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st`
164			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<4>`
165			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st_wg_cy<5>`
166			`SLICE_X18Y20.G3 net (fanout=51) 1.520 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/nop_insert_st`
167			`SLICE_X18Y20.Y Tilo 0.707 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69`
168			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq0000111`
169			`SLICE_X18Y20.F4 net (fanout=2) 0.131 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N104`
170			`SLICE_X18Y20.X Tilo 0.692 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69`
171			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_icall_cmp_eq000011`
172			`SLICE_X19Y20.G4 net (fanout=7) 0.130 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/N69`
173			`SLICE_X19Y20.Y Tilo 0.648 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cml_1`
174			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr_int_or00011`
175			`SLICE_X14Y14.G2 net (fanout=7) 0.855 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/idc_adiw_cmp_eq00001`
176			`SLICE_X14Y14.Y Tilo 0.707 AVR_Core_cm4_Inst/reg_rd_adr<0>`
177			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<0>47`
178			`SLICE_X14Y14.F4 net (fanout=3) 0.077 AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<0>47`
179			`SLICE_X14Y14.X Tilo 0.692 AVR_Core_cm4_Inst/reg_rd_adr<0>`
180			`AVR_Core_cm4_Inst/pm_fetch_dec_Inst/reg_rd_adr<0>56`
181			`SLICE_X11Y15.G1 net (fanout=45) 1.174 AVR_Core_cm4_Inst/reg_rd_adr<0>`
182			`SLICE_X11Y15.CLK Tgck 0.727 AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1<19>`
183			`AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_18_cmp_eq000011`
184			`AVR_Core_cm4_Inst/GPRF_Inst/sg_rd_decode_cml_1_18`
185			`------------------------------------------------- ---------------------------`
186			`Total 11.266ns (6.202ns logic, 5.064ns route)`
187			`(55.1% logic, 44.9% route)`
188
189			`--------------------------------------------------------------------------------`
190
191			`Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 11.5 ns HIGH 50%;`
192			`--------------------------------------------------------------------------------`
193			`Slack (hold path): 0.601ns (requirement - (clock path skew + uncertainty - data path))`
194			`Source: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7 (FF)`
195			`Destination: AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_16_7/SRL16E (FF)`
196			`Requirement: 0.000ns`
197			`Data Path Delay: 0.708ns (Levels of Logic = 1)`
198			`Clock Path Skew: 0.107ns (0.337 - 0.230)`
199			`Source Clock: cp2_BUFGP rising at 11.500ns`
200			`Destination Clock: cp2_BUFGP rising at 11.500ns`
201			`Clock Uncertainty: 0.000ns`
202
203			`Minimum Data Path: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7 to AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_16_7/SRL16E`
204			`Location Delay type Delay(ns) Physical Resource`
205			`Logical Resource(s)`
206			`------------------------------------------------- -------------------`
207			`SLICE_X9Y22.XQ Tcko 0.473 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7`
208			`AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7`
209			`SLICE_X6Y23.BX net (fanout=2) 0.381 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_16_7`
210			`SLICE_X6Y23.CLK Tdh (-Th) 0.146 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_16_7`
211			`AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_16_7/SRL16E`
212			`------------------------------------------------- ---------------------------`
213			`Total 0.708ns (0.327ns logic, 0.381ns route)`
214			`(46.2% logic, 53.8% route)`
215
216			`--------------------------------------------------------------------------------`
217			`Slack (hold path): 0.601ns (requirement - (clock path skew + uncertainty - data path))`
218			`Source: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0 (FF)`
219			`Destination: AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_21_0/SRL16E (FF)`
220			`Requirement: 0.000ns`
221			`Data Path Delay: 0.715ns (Levels of Logic = 1)`
222			`Clock Path Skew: 0.114ns (0.430 - 0.316)`
223			`Source Clock: cp2_BUFGP rising at 11.500ns`
224			`Destination Clock: cp2_BUFGP rising at 11.500ns`
225			`Clock Uncertainty: 0.000ns`
226
227			`Minimum Data Path: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0 to AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_21_0/SRL16E`
228			`Location Delay type Delay(ns) Physical Resource`
229			`Logical Resource(s)`
230			`------------------------------------------------- -------------------`
231			`SLICE_X3Y35.YQ Tcko 0.464 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_1`
232			`AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0`
233			`SLICE_X0Y34.BY net (fanout=2) 0.377 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_21_0`
234			`SLICE_X0Y34.CLK Tdh (-Th) 0.126 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_21_1`
235			`AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_21_0/SRL16E`
236			`------------------------------------------------- ---------------------------`
237			`Total 0.715ns (0.338ns logic, 0.377ns route)`
238			`(47.3% logic, 52.7% route)`
239
240			`--------------------------------------------------------------------------------`
241			`Slack (hold path): 0.610ns (requirement - (clock path skew + uncertainty - data path))`
242			`Source: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5 (FF)`
243			`Destination: AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_19_5/SRL16E (FF)`
244			`Requirement: 0.000ns`
245			`Data Path Delay: 0.746ns (Levels of Logic = 1)`
246			`Clock Path Skew: 0.136ns (0.375 - 0.239)`
247			`Source Clock: cp2_BUFGP rising at 11.500ns`
248			`Destination Clock: cp2_BUFGP rising at 11.500ns`
249			`Clock Uncertainty: 0.000ns`
250
251			`Minimum Data Path: AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5 to AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_19_5/SRL16E`
252			`Location Delay type Delay(ns) Physical Resource`
253			`Logical Resource(s)`
254			`------------------------------------------------- -------------------`
255			`SLICE_X8Y26.XQ Tcko 0.505 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5`
256			`AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5`
257			`SLICE_X6Y26.BX net (fanout=2) 0.387 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_1_19_5`
258			`SLICE_X6Y26.CLK Tdh (-Th) 0.146 AVR_Core_cm4_Inst/GPRF_Inst/register_file_cml_3_19_5`
259			`AVR_Core_cm4_Inst/GPRF_Inst/Mshreg_register_file_cml_3_19_5/SRL16E`
260			`------------------------------------------------- ---------------------------`
261			`Total 0.746ns (0.359ns logic, 0.387ns route)`
262			`(48.1% logic, 51.9% route)`
263
264			`--------------------------------------------------------------------------------`
265
266			`Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 11.5 ns HIGH 50%;`
267			`--------------------------------------------------------------------------------`
268			`Slack: 8.296ns (period - (min low pulse limit / (low pulse / period)))`
269			`Period: 11.500ns`
270			`Low pulse: 5.750ns`
271			`Low pulse limit: 1.602ns (Trpw)`
272			`Physical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR`
273			`Logical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR`
274			`Location pin: SLICE_X28Y46.SR`
275			`Clock network: ireset_IBUF`
276			`--------------------------------------------------------------------------------`
277			`Slack: 8.296ns (period - (min high pulse limit / (high pulse / period)))`
278			`Period: 11.500ns`
279			`High pulse: 5.750ns`
280			`High pulse limit: 1.602ns (Trpw)`
281			`Physical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR`
282			`Logical resource: AVR_Core_cm4_Inst/pm_fetch_dec_Inst/ramwe_int/SR`
283			`Location pin: SLICE_X28Y46.SR`
284			`Clock network: ireset_IBUF`
285			`--------------------------------------------------------------------------------`
286			`Slack: 8.296ns (period - (min low pulse limit / (low pulse / period)))`
287			`Period: 11.500ns`
288			`Low pulse: 5.750ns`
289			`Low pulse limit: 1.602ns (Trpw)`
290			`Physical resource: AVR_Core_cm4_Inst/GPRF_Inst/r29h<0>/SR`
291			`Logical resource: AVR_Core_cm4_Inst/GPRF_Inst/r29h_0/SR`
292			`Location pin: SLICE_X2Y60.SR`
293			`Clock network: ireset_IBUF`
294			`--------------------------------------------------------------------------------`
295
296
297			`All constraints were met.`
298
299
300			`Data Sheet report:`
301			`-----------------`
302			`All values displayed in nanoseconds (ns)`
303
304			`Clock to Setup on destination clock cp2`
305			`---------------+---------+---------+---------+---------+`
306			`\| Src:Rise\| Src:Fall\| Src:Rise\| Src:Fall\|`
307			`Source Clock \|Dest:Rise\|Dest:Rise\|Dest:Fall\|Dest:Fall\|`
308			`---------------+---------+---------+---------+---------+`
309			`cp2 \| 11.446\| \| \| \|`
310			`---------------+---------+---------+---------+---------+`
311
312
313			`Timing summary:`
314			`---------------`
315
316			`Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)`
317
318			`Constraints cover 145500 paths, 0 nets, and 9529 connections`
319
320			`Design statistics:`
321			`Minimum period: 11.446ns{1} (Maximum frequency: 87.367MHz)`
322
323
324			`------------------------------------Footnotes-----------------------------------`
325			`1) The minimum period statistic assumes all single cycle delays.`
326
327			`Analysis completed Sun Oct 03 11:38:16 2010`
328			`--------------------------------------------------------------------------------`
329
330			`Trace Settings:`
331			`-------------------------`
332			`Trace Settings`
333
334			`Peak Memory Usage: 163 MB`
335
336
337