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--------------------------------------------------------------------------------
Release 11.1 Trace  (nt)
Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
 
C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise
C:/EDAptability/coremultiplier/reference/avr/ise/ise_v5_cm2_one_syneda/ise_v5_cm2_one_syneda/ise_v5_cm2_one_syneda.ise
-intstyle ise -v 3 -s 3 -fastpaths -xml avr_core_cm2_top.twx
avr_core_cm2_top.ncd -o avr_core_cm2_top.twr avr_core_cm2_top.pcf -ucf
avr_core_cm2_top.ucf
 
Design file:              avr_core_cm2_top.ncd
Physical constraint file: avr_core_cm2_top.pcf
Device,package,speed:     xc5vlx50,ff324,-3 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)
Report level:             verbose report
 
Environment Variable      Effect
--------------------      ------
NONE                      No environment variables were set
--------------------------------------------------------------------------------
 
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
   a 50 Ohm transmission line loading model.  For the details of this model,
   and for more information on accounting for different loading conditions,
   please see the device datasheet.
 
================================================================================
Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 5.3 ns HIGH 50%;
 
 412450 paths analyzed, 2880 endpoints analyzed, 1 failing endpoint
 1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors)
 Minimum period is   5.302ns.
--------------------------------------------------------------------------------
Slack (setup path):     -0.002ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 (FF)
  Destination:          AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0 (FF)
  Requirement:          5.300ns
  Data Path Delay:      5.092ns (Levels of Logic = 6)
  Clock Path Skew:      -0.175ns (0.995 - 1.170)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.035ns
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns
 
  Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y84.AQ      Tcko                  0.326   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<14>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13
    SLICE_X12Y85.A1      net (fanout=10)       0.835   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>
    SLICE_X12Y85.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_1_or0000137
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_sleep_cmp_eq00001
    SLICE_X17Y90.A6      net (fanout=41)       0.634   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N74
    SLICE_X17Y90.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_2_or0000159
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or00011
    SLICE_X16Y86.D2      net (fanout=5)        0.754   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or0001
    SLICE_X16Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/alu_data_out<6>
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_6_or0000179
    SLICE_X17Y86.D2      net (fanout=2)        0.664   AVR_Core_cm2_Inst/alu_data_out<6>
    SLICE_X17Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq0000
    SLICE_X27Y70.B6      net (fanout=5)        0.981   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
    SLICE_X27Y70.B       Tilo                  0.080   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<10>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>1266
    SLICE_X27Y75.A5      net (fanout=19)       0.470   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N13
    SLICE_X27Y75.CLK     Tas                   0.028   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0_mux00011
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0
    -------------------------------------------------  ---------------------------
    Total                                      5.092ns (0.754ns logic, 4.338ns route)
                                                       (14.8% logic, 85.2% route)
 
--------------------------------------------------------------------------------
Slack (setup path):     0.014ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 (FF)
  Destination:          AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_13 (FF)
  Requirement:          5.300ns
  Data Path Delay:      5.053ns (Levels of Logic = 6)
  Clock Path Skew:      -0.198ns (0.972 - 1.170)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.035ns
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns
 
  Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y84.AQ      Tcko                  0.326   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<14>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13
    SLICE_X12Y85.A1      net (fanout=10)       0.835   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>
    SLICE_X12Y85.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_1_or0000137
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_sleep_cmp_eq00001
    SLICE_X17Y90.A6      net (fanout=41)       0.634   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N74
    SLICE_X17Y90.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_2_or0000159
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or00011
    SLICE_X16Y86.D2      net (fanout=5)        0.754   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or0001
    SLICE_X16Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/alu_data_out<6>
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_6_or0000179
    SLICE_X17Y86.D2      net (fanout=2)        0.664   AVR_Core_cm2_Inst/alu_data_out<6>
    SLICE_X17Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq0000
    SLICE_X27Y70.B6      net (fanout=5)        0.981   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
    SLICE_X27Y70.B       Tilo                  0.080   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<10>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>1266
    SLICE_X27Y68.C6      net (fanout=19)       0.429   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N13
    SLICE_X27Y68.CLK     Tas                   0.030   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<14>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<13>1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_13
    -------------------------------------------------  ---------------------------
    Total                                      5.053ns (0.756ns logic, 4.297ns route)
                                                       (15.0% logic, 85.0% route)
 
--------------------------------------------------------------------------------
Slack (setup path):     0.018ns (requirement - (data path - clock path skew + uncertainty))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 (FF)
  Destination:          AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_14 (FF)
  Requirement:          5.300ns
  Data Path Delay:      5.049ns (Levels of Logic = 6)
  Clock Path Skew:      -0.198ns (0.972 - 1.170)
  Source Clock:         cp2_BUFGP rising at 0.000ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.035ns
 
  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns
 
  Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y84.AQ      Tcko                  0.326   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<14>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13
    SLICE_X12Y85.A1      net (fanout=10)       0.835   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>
    SLICE_X12Y85.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_1_or0000137
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_sleep_cmp_eq00001
    SLICE_X17Y90.A6      net (fanout=41)       0.634   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N74
    SLICE_X17Y90.A       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_2_or0000159
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or00011
    SLICE_X16Y86.D2      net (fanout=5)        0.754   AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or0001
    SLICE_X16Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/alu_data_out<6>
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_6_or0000179
    SLICE_X17Y86.D2      net (fanout=2)        0.664   AVR_Core_cm2_Inst/alu_data_out<6>
    SLICE_X17Y86.D       Tilo                  0.080   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
                                                       AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq0000
    SLICE_X27Y70.B6      net (fanout=5)        0.981   AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int
    SLICE_X27Y70.B       Tilo                  0.080   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<10>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>1266
    SLICE_X27Y68.D6      net (fanout=19)       0.427   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N13
    SLICE_X27Y68.CLK     Tas                   0.028   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<14>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<14>1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_14
    -------------------------------------------------  ---------------------------
    Total                                      5.049ns (0.754ns logic, 4.295ns route)
                                                       (14.9% logic, 85.1% route)
 
--------------------------------------------------------------------------------
 
Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 5.3 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.239ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st (FF)
  Destination:          AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st_cml_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.388ns (Levels of Logic = 0)
  Clock Path Skew:      0.149ns (1.200 - 1.051)
  Source Clock:         cp2_BUFGP rising at 5.300ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.000ns
 
  Minimum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st_cml_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y78.AQ      Tcko                  0.318   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/brxx_st
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st
    SLICE_X11Y80.AX      net (fanout=2)        0.234   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st
    SLICE_X11Y80.CLK     Tckdi       (-Th)     0.164   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/brxx_st_cml_1
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st_cml_1
    -------------------------------------------------  ---------------------------
    Total                                      0.388ns (0.154ns logic, 0.234ns route)
                                                       (39.7% logic, 60.3% route)
 
--------------------------------------------------------------------------------
Slack (hold path):      0.240ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_4 (FF)
  Destination:          AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.247ns (Levels of Logic = 0)
  Clock Path Skew:      0.007ns (0.107 - 0.100)
  Source Clock:         cp2_BUFGP rising at 5.300ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.000ns
 
  Minimum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_4 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X25Y71.BQ      Tcko                  0.300   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr<6>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_4
    SLICE_X24Y71.AX      net (fanout=2)        0.120   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr<4>
    SLICE_X24Y71.CLK     Tckdi       (-Th)     0.173   AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1<7>
                                                       AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1_4
    -------------------------------------------------  ---------------------------
    Total                                      0.247ns (0.127ns logic, 0.120ns route)
                                                       (51.4% logic, 48.6% route)
 
--------------------------------------------------------------------------------
Slack (hold path):      0.240ns (requirement - (clock path skew + uncertainty - data path))
  Source:               AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2 (FF)
  Destination:          AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.250ns (Levels of Logic = 0)
  Clock Path Skew:      0.010ns (0.144 - 0.134)
  Source Clock:         cp2_BUFGP rising at 5.300ns
  Destination Clock:    cp2_BUFGP rising at 5.300ns
  Clock Uncertainty:    0.000ns
 
  Minimum Data Path: AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2 to AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y99.DQ      Tcko                  0.300   AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2
                                                       AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2
    SLICE_X12Y99.CX      net (fanout=3)        0.120   AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2
    SLICE_X12Y99.CLK     Tckdi       (-Th)     0.170   AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_3
                                                       AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_2
    -------------------------------------------------  ---------------------------
    Total                                      0.250ns (0.130ns logic, 0.120ns route)
                                                       (52.0% logic, 48.0% route)
 
--------------------------------------------------------------------------------
 
Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 5.3 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.246ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.300ns
  Low pulse: 2.650ns
  Low pulse limit: 0.527ns (Trpw)
  Physical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched<4>/SR
  Logical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched_4/SR
  Location pin: SLICE_X1Y74.SR
  Clock network: AVR_Core_cm2_Inst/BP_Inst/ireset_inv
--------------------------------------------------------------------------------
Slack: 4.246ns (period - (min high pulse limit / (high pulse / period)))
  Period: 5.300ns
  High pulse: 2.650ns
  High pulse limit: 0.527ns (Trpw)
  Physical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched<4>/SR
  Logical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched_4/SR
  Location pin: SLICE_X1Y74.SR
  Clock network: AVR_Core_cm2_Inst/BP_Inst/ireset_inv
--------------------------------------------------------------------------------
Slack: 4.246ns (period - (min low pulse limit / (low pulse / period)))
  Period: 5.300ns
  Low pulse: 2.650ns
  Low pulse limit: 0.527ns (Trpw)
  Physical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/ramadr_int<15>/SR
  Logical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/ramadr_int_15/SR
  Location pin: SLICE_X2Y69.SR
  Clock network: AVR_Core_cm2_Inst/BP_Inst/ireset_inv
--------------------------------------------------------------------------------
 
 
1 constraint not met.
 
 
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
 
Clock to Setup on destination clock cp2
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
cp2            |    5.302|         |         |         |
---------------+---------+---------+---------+---------+
 
 
Timing summary:
---------------
 
Timing errors: 1  Score: 2  (Setup/Max: 2, Hold: 0)
 
Constraints cover 412450 paths, 0 nets, and 7964 connections
 
Design statistics:
   Minimum period:   5.302ns{1}   (Maximum frequency: 188.608MHz)
 
 
------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.
 
Analysis completed Thu Oct 07 20:29:46 2010
--------------------------------------------------------------------------------
 
Trace Settings:
-------------------------
Trace Settings
 
Peak Memory Usage: 264 MB
 
 
 

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[/] [avr_hp/] [trunk/] [ise/] [ise_v5_cm2_one/] [avr_core_cm2_top.twr] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	tobil	`--------------------------------------------------------------------------------`
2			`Release 11.1 Trace (nt)`
3			`Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.`
4
5			`C:\Xilinx\11.1\ISE\bin\nt\unwrapped\trce.exe -ise`
6			`C:/EDAptability/coremultiplier/reference/avr/ise/ise_v5_cm2_one_syneda/ise_v5_cm2_one_syneda/ise_v5_cm2_one_syneda.ise`
7			`-intstyle ise -v 3 -s 3 -fastpaths -xml avr_core_cm2_top.twx`
8			`avr_core_cm2_top.ncd -o avr_core_cm2_top.twr avr_core_cm2_top.pcf -ucf`
9			`avr_core_cm2_top.ucf`
10
11			`Design file: avr_core_cm2_top.ncd`
12			`Physical constraint file: avr_core_cm2_top.pcf`
13			`Device,package,speed: xc5vlx50,ff324,-3 (PRODUCTION 1.64 2009-03-03, STEPPING level 0)`
14			`Report level: verbose report`
15
16			`Environment Variable Effect`
17			`-------------------- ------`
18			`NONE No environment variables were set`
19			`--------------------------------------------------------------------------------`
20
21			`INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths`
22			`option. All paths that are not constrained will be reported in the`
23			`unconstrained paths section(s) of the report.`
24			`INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on`
25			`a 50 Ohm transmission line loading model. For the details of this model,`
26			`and for more information on accounting for different loading conditions,`
27			`please see the device datasheet.`
28
29			`================================================================================`
30			`Timing constraint: TS_cp2 = PERIOD TIMEGRP "cp2" 5.3 ns HIGH 50%;`
31
32			`412450 paths analyzed, 2880 endpoints analyzed, 1 failing endpoint`
33			`1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors)`
34			`Minimum period is 5.302ns.`
35			`--------------------------------------------------------------------------------`
36			`Slack (setup path): -0.002ns (requirement - (data path - clock path skew + uncertainty))`
37			`Source: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 (FF)`
38			`Destination: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0 (FF)`
39			`Requirement: 5.300ns`
40			`Data Path Delay: 5.092ns (Levels of Logic = 6)`
41			`Clock Path Skew: -0.175ns (0.995 - 1.170)`
42			`Source Clock: cp2_BUFGP rising at 0.000ns`
43			`Destination Clock: cp2_BUFGP rising at 5.300ns`
44			`Clock Uncertainty: 0.035ns`
45
46			`Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE`
47			`Total System Jitter (TSJ): 0.070ns`
48			`Total Input Jitter (TIJ): 0.000ns`
49			`Discrete Jitter (DJ): 0.000ns`
50			`Phase Error (PE): 0.000ns`
51
52			`Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0`
53			`Location Delay type Delay(ns) Physical Resource`
54			`Logical Resource(s)`
55			`------------------------------------------------- -------------------`
56			`SLICE_X13Y84.AQ Tcko 0.326 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<14>`
57			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13`
58			`SLICE_X12Y85.A1 net (fanout=10) 0.835 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>`
59			`SLICE_X12Y85.A Tilo 0.080 AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_1_or0000137`
60			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_sleep_cmp_eq00001`
61			`SLICE_X17Y90.A6 net (fanout=41) 0.634 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N74`
62			`SLICE_X17Y90.A Tilo 0.080 AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_2_or0000159`
63			`AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or00011`
64			`SLICE_X16Y86.D2 net (fanout=5) 0.754 AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or0001`
65			`SLICE_X16Y86.D Tilo 0.080 AVR_Core_cm2_Inst/alu_data_out<6>`
66			`AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_6_or0000179`
67			`SLICE_X17Y86.D2 net (fanout=2) 0.664 AVR_Core_cm2_Inst/alu_data_out<6>`
68			`SLICE_X17Y86.D Tilo 0.080 AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int`
69			`AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq0000`
70			`SLICE_X27Y70.B6 net (fanout=5) 0.981 AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int`
71			`SLICE_X27Y70.B Tilo 0.080 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<10>`
72			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>1266`
73			`SLICE_X27Y75.A5 net (fanout=19) 0.470 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N13`
74			`SLICE_X27Y75.CLK Tas 0.028 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0`
75			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0_mux00011`
76			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/nirq_st0`
77			`------------------------------------------------- ---------------------------`
78			`Total 5.092ns (0.754ns logic, 4.338ns route)`
79			`(14.8% logic, 85.2% route)`
80
81			`--------------------------------------------------------------------------------`
82			`Slack (setup path): 0.014ns (requirement - (data path - clock path skew + uncertainty))`
83			`Source: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 (FF)`
84			`Destination: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_13 (FF)`
85			`Requirement: 5.300ns`
86			`Data Path Delay: 5.053ns (Levels of Logic = 6)`
87			`Clock Path Skew: -0.198ns (0.972 - 1.170)`
88			`Source Clock: cp2_BUFGP rising at 0.000ns`
89			`Destination Clock: cp2_BUFGP rising at 5.300ns`
90			`Clock Uncertainty: 0.035ns`
91
92			`Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE`
93			`Total System Jitter (TSJ): 0.070ns`
94			`Total Input Jitter (TIJ): 0.000ns`
95			`Discrete Jitter (DJ): 0.000ns`
96			`Phase Error (PE): 0.000ns`
97
98			`Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_13`
99			`Location Delay type Delay(ns) Physical Resource`
100			`Logical Resource(s)`
101			`------------------------------------------------- -------------------`
102			`SLICE_X13Y84.AQ Tcko 0.326 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<14>`
103			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13`
104			`SLICE_X12Y85.A1 net (fanout=10) 0.835 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>`
105			`SLICE_X12Y85.A Tilo 0.080 AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_1_or0000137`
106			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_sleep_cmp_eq00001`
107			`SLICE_X17Y90.A6 net (fanout=41) 0.634 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N74`
108			`SLICE_X17Y90.A Tilo 0.080 AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_2_or0000159`
109			`AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or00011`
110			`SLICE_X16Y86.D2 net (fanout=5) 0.754 AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or0001`
111			`SLICE_X16Y86.D Tilo 0.080 AVR_Core_cm2_Inst/alu_data_out<6>`
112			`AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_6_or0000179`
113			`SLICE_X17Y86.D2 net (fanout=2) 0.664 AVR_Core_cm2_Inst/alu_data_out<6>`
114			`SLICE_X17Y86.D Tilo 0.080 AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int`
115			`AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq0000`
116			`SLICE_X27Y70.B6 net (fanout=5) 0.981 AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int`
117			`SLICE_X27Y70.B Tilo 0.080 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<10>`
118			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>1266`
119			`SLICE_X27Y68.C6 net (fanout=19) 0.429 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N13`
120			`SLICE_X27Y68.CLK Tas 0.030 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<14>`
121			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<13>1`
122			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_13`
123			`------------------------------------------------- ---------------------------`
124			`Total 5.053ns (0.756ns logic, 4.297ns route)`
125			`(15.0% logic, 85.0% route)`
126
127			`--------------------------------------------------------------------------------`
128			`Slack (setup path): 0.018ns (requirement - (data path - clock path skew + uncertainty))`
129			`Source: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 (FF)`
130			`Destination: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_14 (FF)`
131			`Requirement: 5.300ns`
132			`Data Path Delay: 5.049ns (Levels of Logic = 6)`
133			`Clock Path Skew: -0.198ns (0.972 - 1.170)`
134			`Source Clock: cp2_BUFGP rising at 0.000ns`
135			`Destination Clock: cp2_BUFGP rising at 5.300ns`
136			`Clock Uncertainty: 0.035ns`
137
138			`Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE`
139			`Total System Jitter (TSJ): 0.070ns`
140			`Total Input Jitter (TIJ): 0.000ns`
141			`Discrete Jitter (DJ): 0.000ns`
142			`Phase Error (PE): 0.000ns`
143
144			`Maximum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_14`
145			`Location Delay type Delay(ns) Physical Resource`
146			`Logical Resource(s)`
147			`------------------------------------------------- -------------------`
148			`SLICE_X13Y84.AQ Tcko 0.326 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<14>`
149			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1_13`
150			`SLICE_X12Y85.A1 net (fanout=10) 0.835 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/instruction_code_reg_cml_1<13>`
151			`SLICE_X12Y85.A Tilo 0.080 AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_1_or0000137`
152			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/idc_sleep_cmp_eq00001`
153			`SLICE_X17Y90.A6 net (fanout=41) 0.634 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N74`
154			`SLICE_X17Y90.A Tilo 0.080 AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_2_or0000159`
155			`AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or00011`
156			`SLICE_X16Y86.D2 net (fanout=5) 0.754 AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_0_or0001`
157			`SLICE_X16Y86.D Tilo 0.080 AVR_Core_cm2_Inst/alu_data_out<6>`
158			`AVR_Core_cm2_Inst/ALU_Inst/alu_data_out_int_6_or0000179`
159			`SLICE_X17Y86.D2 net (fanout=2) 0.664 AVR_Core_cm2_Inst/alu_data_out<6>`
160			`SLICE_X17Y86.D Tilo 0.080 AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int`
161			`AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int_cmp_eq0000`
162			`SLICE_X27Y70.B6 net (fanout=5) 0.981 AVR_Core_cm2_Inst/ALU_Inst/alu_z_flag_out_int`
163			`SLICE_X27Y70.B Tilo 0.080 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<10>`
164			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<0>1266`
165			`SLICE_X27Y68.D6 net (fanout=19) 0.427 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/N13`
166			`SLICE_X27Y68.CLK Tas 0.028 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt<14>`
167			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_mux0002<14>1`
168			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/pc_for_interrupt_14`
169			`------------------------------------------------- ---------------------------`
170			`Total 5.049ns (0.754ns logic, 4.295ns route)`
171			`(14.9% logic, 85.1% route)`
172
173			`--------------------------------------------------------------------------------`
174
175			`Hold Paths: TS_cp2 = PERIOD TIMEGRP "cp2" 5.3 ns HIGH 50%;`
176			`--------------------------------------------------------------------------------`
177			`Slack (hold path): 0.239ns (requirement - (clock path skew + uncertainty - data path))`
178			`Source: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st (FF)`
179			`Destination: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st_cml_1 (FF)`
180			`Requirement: 0.000ns`
181			`Data Path Delay: 0.388ns (Levels of Logic = 0)`
182			`Clock Path Skew: 0.149ns (1.200 - 1.051)`
183			`Source Clock: cp2_BUFGP rising at 5.300ns`
184			`Destination Clock: cp2_BUFGP rising at 5.300ns`
185			`Clock Uncertainty: 0.000ns`
186
187			`Minimum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st_cml_1`
188			`Location Delay type Delay(ns) Physical Resource`
189			`Logical Resource(s)`
190			`------------------------------------------------- -------------------`
191			`SLICE_X10Y78.AQ Tcko 0.318 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/brxx_st`
192			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st`
193			`SLICE_X11Y80.AX net (fanout=2) 0.234 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st`
194			`SLICE_X11Y80.CLK Tckdi (-Th) 0.164 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/brxx_st_cml_1`
195			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/rjmp_st_cml_1`
196			`------------------------------------------------- ---------------------------`
197			`Total 0.388ns (0.154ns logic, 0.234ns route)`
198			`(39.7% logic, 60.3% route)`
199
200			`--------------------------------------------------------------------------------`
201			`Slack (hold path): 0.240ns (requirement - (clock path skew + uncertainty - data path))`
202			`Source: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_4 (FF)`
203			`Destination: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1_4 (FF)`
204			`Requirement: 0.000ns`
205			`Data Path Delay: 0.247ns (Levels of Logic = 0)`
206			`Clock Path Skew: 0.007ns (0.107 - 0.100)`
207			`Source Clock: cp2_BUFGP rising at 5.300ns`
208			`Destination Clock: cp2_BUFGP rising at 5.300ns`
209			`Clock Uncertainty: 0.000ns`
210
211			`Minimum Data Path: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_4 to AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1_4`
212			`Location Delay type Delay(ns) Physical Resource`
213			`Logical Resource(s)`
214			`------------------------------------------------- -------------------`
215			`SLICE_X25Y71.BQ Tcko 0.300 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr<6>`
216			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_4`
217			`SLICE_X24Y71.AX net (fanout=2) 0.120 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr<4>`
218			`SLICE_X24Y71.CLK Tckdi (-Th) 0.173 AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1<7>`
219			`AVR_Core_cm2_Inst/pm_fetch_dec_Inst/program_counter_high_fr_cml_1_4`
220			`------------------------------------------------- ---------------------------`
221			`Total 0.247ns (0.127ns logic, 0.120ns route)`
222			`(51.4% logic, 48.6% route)`
223
224			`--------------------------------------------------------------------------------`
225			`Slack (hold path): 0.240ns (requirement - (clock path skew + uncertainty - data path))`
226			`Source: AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2 (FF)`
227			`Destination: AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_2 (FF)`
228			`Requirement: 0.000ns`
229			`Data Path Delay: 0.250ns (Levels of Logic = 0)`
230			`Clock Path Skew: 0.010ns (0.144 - 0.134)`
231			`Source Clock: cp2_BUFGP rising at 5.300ns`
232			`Destination Clock: cp2_BUFGP rising at 5.300ns`
233			`Clock Uncertainty: 0.000ns`
234
235			`Minimum Data Path: AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2 to AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_2`
236			`Location Delay type Delay(ns) Physical Resource`
237			`Logical Resource(s)`
238			`------------------------------------------------- -------------------`
239			`SLICE_X13Y99.DQ Tcko 0.300 AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2`
240			`AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2`
241			`SLICE_X12Y99.CX net (fanout=3) 0.120 AVR_Core_cm2_Inst/GPRF_Inst/register_file_7_2`
242			`SLICE_X12Y99.CLK Tckdi (-Th) 0.170 AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_3`
243			`AVR_Core_cm2_Inst/GPRF_Inst/register_file_cml_1_7_2`
244			`------------------------------------------------- ---------------------------`
245			`Total 0.250ns (0.130ns logic, 0.120ns route)`
246			`(52.0% logic, 48.0% route)`
247
248			`--------------------------------------------------------------------------------`
249
250			`Component Switching Limit Checks: TS_cp2 = PERIOD TIMEGRP "cp2" 5.3 ns HIGH 50%;`
251			`--------------------------------------------------------------------------------`
252			`Slack: 4.246ns (period - (min low pulse limit / (low pulse / period)))`
253			`Period: 5.300ns`
254			`Low pulse: 2.650ns`
255			`Low pulse limit: 0.527ns (Trpw)`
256			`Physical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched<4>/SR`
257			`Logical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched_4/SR`
258			`Location pin: SLICE_X1Y74.SR`
259			`Clock network: AVR_Core_cm2_Inst/BP_Inst/ireset_inv`
260			`--------------------------------------------------------------------------------`
261			`Slack: 4.246ns (period - (min high pulse limit / (high pulse / period)))`
262			`Period: 5.300ns`
263			`High pulse: 2.650ns`
264			`High pulse limit: 0.527ns (Trpw)`
265			`Physical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched<4>/SR`
266			`Logical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/dex_adrreg_d_latched_4/SR`
267			`Location pin: SLICE_X1Y74.SR`
268			`Clock network: AVR_Core_cm2_Inst/BP_Inst/ireset_inv`
269			`--------------------------------------------------------------------------------`
270			`Slack: 4.246ns (period - (min low pulse limit / (low pulse / period)))`
271			`Period: 5.300ns`
272			`Low pulse: 2.650ns`
273			`Low pulse limit: 0.527ns (Trpw)`
274			`Physical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/ramadr_int<15>/SR`
275			`Logical resource: AVR_Core_cm2_Inst/pm_fetch_dec_Inst/ramadr_int_15/SR`
276			`Location pin: SLICE_X2Y69.SR`
277			`Clock network: AVR_Core_cm2_Inst/BP_Inst/ireset_inv`
278			`--------------------------------------------------------------------------------`
279
280
281			`1 constraint not met.`
282
283
284			`Data Sheet report:`
285			`-----------------`
286			`All values displayed in nanoseconds (ns)`
287
288			`Clock to Setup on destination clock cp2`
289			`---------------+---------+---------+---------+---------+`
290			`\| Src:Rise\| Src:Fall\| Src:Rise\| Src:Fall\|`
291			`Source Clock \|Dest:Rise\|Dest:Rise\|Dest:Fall\|Dest:Fall\|`
292			`---------------+---------+---------+---------+---------+`
293			`cp2 \| 5.302\| \| \| \|`
294			`---------------+---------+---------+---------+---------+`
295
296
297			`Timing summary:`
298			`---------------`
299
300			`Timing errors: 1 Score: 2 (Setup/Max: 2, Hold: 0)`
301
302			`Constraints cover 412450 paths, 0 nets, and 7964 connections`
303
304			`Design statistics:`
305			`Minimum period: 5.302ns{1} (Maximum frequency: 188.608MHz)`
306
307
308			`------------------------------------Footnotes-----------------------------------`
309			`1) The minimum period statistic assumes all single cycle delays.`
310
311			`Analysis completed Thu Oct 07 20:29:46 2010`
312			`--------------------------------------------------------------------------------`
313
314			`Trace Settings:`
315			`-------------------------`
316			`Trace Settings`
317
318			`Peak Memory Usage: 264 MB`
319
320
321