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[/] [avr_hp/] [trunk/] [rtl/] [rtl_s3_cm3/] [pm_fetch_dec.vhd] - Blame information for rev 2

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1 2 tobil 
--************************************************************************************************
2 
--  PM_FETCH_DEC(internal module) for AVR core
3 
--      Version 2.6! (Special version for the JTAG OCD)
4 
--  Designed by Ruslan Lepetenok 14.11.2001
5 
--  Modified 31.05.06
6 
--  Modification:
7 
--  Registered ramre/ramwe outputs
8 
--  cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt)
9 
--  SLEEP and CLRWDT instructions support was added
10 
--  V-flag bug fixed (AND/ANDI/OR/ORI/EOR)
11 
--  V-flag bug fixed (ADIW/SBIW)
12 
--  Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed.
13 
--  Output alu_data_d_in[7..0] was removed.
14 
--  Gloabal clock enable(cp2en) was added
15 
--  cpu_busy(push/pop) + irq bug was fixed 14.07.05
16 
--  BRXX+IRQ interaction was modified -> cpu_busy
17 
--  LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon)
18 
--************************************************************************************************
19 
 
20 
library IEEE;
21 
use IEEE.std_logic_1164.all;
22 
use IEEE.std_logic_unsigned.all;
23 
 
24 
use WORK.AVRuCPackage.all;
25 
 
26 
entity pm_fetch_dec_cm3 is port(
27 
                cp2_cml_1 : in std_logic;
28 
                cp2_cml_2 : in std_logic;
29 
 
30 
                              -- Clock and reset
31 
                              cp2              : in  std_logic;
32 
                                                          cp2en            : in  std_logic;
33 
                              ireset           : in  std_logic;
34 
                                                          -- JTAG OCD support
35 
                                                          valid_instr      : out  std_logic;
36 
                                                      insert_nop       : in   std_logic;
37 
                                                      block_irq        : in   std_logic;
38 
                                                      change_flow      : out  std_logic;
39 
                                                          -- Program memory
40 
                              pc               : out std_logic_vector (15 downto 0);
41 
                              inst             : in  std_logic_vector (15 downto 0);
42 
                              -- I/O control
43 
                              adr              : out std_logic_vector (5 downto 0);
44 
                              iore             : out std_logic;
45 
                              iowe             : out std_logic;
46 
                              -- Data memory control
47 
                              ramadr           : out std_logic_vector (15 downto 0);
48 
                              ramre            : out std_logic;
49 
                              ramwe            : out std_logic;
50 
                              cpuwait          : in  std_logic;
51 
                                                          -- Data paths
52 
                              dbusin           : in  std_logic_vector (7 downto 0);
53 
                              dbusout          : out std_logic_vector (7 downto 0);
54 
                              dbusout_int_route : out std_logic_vector (7 downto 0);
55 
                              -- Interrupt
56 
                              irqlines         : in  std_logic_vector (22 downto 0);
57 
                              irqack           : out std_logic;
58 
                              irqackad         : out std_logic_vector(4 downto 0);
59 
                                                      --Sleep
60 
                              sleepi           : out std_logic;
61 
                              irqok                : out std_logic;
62 
                              --Watchdog
63 
                              wdri                 : out std_logic;
64 
                                                          -- ALU interface(Data inputs)
65 
                              alu_data_r_in    : out std_logic_vector(7 downto 0);
66 
                                                          -- ALU interface(Instruction inputs)
67 
                                                          idc_add_out      : out std_logic;
68 
                              idc_adc_out      : out std_logic;
69 
                              idc_adiw_out     : out std_logic;
70 
                              idc_sub_out      : out std_logic;
71 
                              idc_subi_out     : out std_logic;
72 
                              idc_sbc_out      : out std_logic;
73 
                              idc_sbci_out     : out std_logic;
74 
                              idc_sbiw_out     : out std_logic;
75 
 
76 
                              adiw_st_out      : out std_logic;
77 
                              sbiw_st_out      : out std_logic;
78 
 
79 
                              idc_and_out      : out std_logic;
80 
                              idc_andi_out     : out std_logic;
81 
                              idc_or_out       : out std_logic;
82 
                              idc_ori_out      : out std_logic;
83 
                              idc_eor_out      : out std_logic;
84 
                              idc_com_out      : out std_logic;
85 
                              idc_neg_out      : out std_logic;
86 
 
87 
                              idc_inc_out      : out std_logic;
88 
                              idc_dec_out      : out std_logic;
89 
 
90 
                              idc_cp_out       : out std_logic;
91 
                              idc_cpc_out      : out std_logic;
92 
                              idc_cpi_out      : out std_logic;
93 
                              idc_cpse_out     : out std_logic;
94 
 
95 
                              idc_lsr_out      : out std_logic;
96 
                              idc_ror_out      : out std_logic;
97 
                              idc_asr_out      : out std_logic;
98 
                              idc_swap_out     : out std_logic;
99 
 
100 
                               -- ALU interface(Data output)
101 
                               alu_data_out    : in std_logic_vector(7 downto 0);
102 
 
103 
                               -- ALU interface(Flag outputs)
104 
                               alu_c_flag_out  : in std_logic;
105 
                               alu_z_flag_out  : in std_logic;
106 
                               alu_n_flag_out  : in std_logic;
107 
                               alu_v_flag_out  : in std_logic;
108 
                               alu_s_flag_out  : in std_logic;
109 
                               alu_h_flag_out  : in std_logic;
110 
 
111 
                                                           -- General purpose register file interface
112 
                               reg_rd_in       : out std_logic_vector  (7 downto 0);
113 
                               reg_rd_out      : in  std_logic_vector  (7 downto 0);
114 
                               reg_rd_out_int  : in std_logic_vector(7 downto 0);
115 
                               reg_rd_adr      : out std_logic_vector  (4 downto 0);
116 
                               reg_rd_adr_int      : out std_logic_vector  (4 downto 0);
117 
                               reg_rr_out      : in  std_logic_vector  (7 downto 0);
118 
                               reg_rr_adr      : out std_logic_vector  (4 downto 0);
119 
                               reg_rd_wr       : out std_logic;
120 
 
121 
                               post_inc        : out std_logic;                       -- POST INCREMENT FOR LD/ST INSTRUCTIONS
122 
                               pre_dec         : out std_logic;                        -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
123 
                               reg_h_wr        : out std_logic;
124 
                               reg_h_out       : in  std_logic_vector (15 downto 0);
125 
                               reg_h_adr       : out std_logic_vector (2 downto 0);    -- x,y,z
126 
                                       reg_z_out       : in  std_logic_vector (15 downto 0);  -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
127 
 
128 
                               -- I/O register file interface
129 
                               sreg_fl_in      : out std_logic_vector(7 downto 0);
130 
                               globint         : in  std_logic; -- SREG I flag
131 
 
132 
                               sreg_fl_wr_en   : out std_logic_vector(7 downto 0);   --FLAGS WRITE ENABLE SIGNALS
133 
 
134 
                               spl_out         : in  std_logic_vector(7 downto 0);
135 
                               sph_out         : in  std_logic_vector(7 downto 0);
136 
                               sp_ndown_up     : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
137 
                               sp_en           : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
138 
 
139 
                               rampz_out       : in  std_logic_vector(7 downto 0);
140 
 
141 
                                                           -- Bit processor interface
142 
                               bit_num_r_io    : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
143 
                               bitpr_io_out    : in  std_logic_vector(7 downto 0);  -- SBI/CBI OUT
144 
                               branch          : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION
145 
                               bit_pr_sreg_out : in  std_logic_vector(7 downto 0);  -- BCLR/BSET/BST(T-FLAG ONLY)
146 
                               bld_op_out      : in  std_logic_vector(7 downto 0);  -- BLD OUT (T FLAG)
147 
                               bit_test_op_out : in  std_logic;                     -- OUTPUT OF SBIC/SBIS/SBRS/SBRC
148 
 
149 
                               sbi_st_out      : out std_logic;
150 
                               cbi_st_out      : out std_logic;
151 
 
152 
                               idc_bst_out     : out std_logic;
153 
                               idc_bset_out    : out std_logic;
154 
                               idc_bclr_out    : out std_logic;
155 
 
156 
                               idc_sbic_out    : out std_logic;
157 
                               idc_sbis_out    : out std_logic;
158 
 
159 
                               idc_sbrs_out    : out std_logic;
160 
                               idc_sbrc_out    : out std_logic;
161 
 
162 
                               idc_brbs_out    : out std_logic;
163 
                               idc_brbc_out    : out std_logic;
164 
 
165 
                               idc_reti_out    : out std_logic);
166 
end pm_fetch_dec_cm3;
167 
 
168 
architecture RTL of pm_fetch_dec_cm3 is
169 
 
170 
-- COPIES OF OUTPUTS
171 
signal ramadr_reg_in  : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER
172 
signal ramadr_reg_en  : std_logic;                     -- ADRESS REGISTER CLOCK ENABLE SIGNAL
173 
 
174 
signal irqack_int     : std_logic;
175 
signal irqackad_int   : std_logic_vector(irqackad'range);
176 
 
177 
-- ####################################################
178 
-- INTERNAL SIGNALS
179 
-- ####################################################
180 
 
181 
-- NEW SIGNALS
182 
signal   two_word_inst       : std_logic;                    -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR
183 
 
184 
signal   ram_adr_int         : std_logic_vector (15 downto 0);
185 
constant const_ram_to_reg    : std_logic_vector := "00000000000";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19
186 
constant const_ram_to_io_a   : std_logic_vector := "00000000001";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
187 
constant const_ram_to_io_b   : std_logic_vector := "00000000010";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
188 
 
189 
-- LD/LDD/ST/STD SIGNALS
190 
signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0);
191 
signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0);
192 
 
193 
 
194 
-- PROGRAM COUNTER SIGNALS
195 
signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS
196 
signal program_counter     : std_logic_vector (15 downto 0);
197 
signal program_counter_in  : std_logic_vector (15 downto 0);
198 
signal program_counter_high_fr  : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL
199 
 
200 
signal pc_low       : std_logic_vector (7 downto 0);
201 
signal pc_high      : std_logic_vector (7 downto 0);
202 
 
203 
 
204 
signal pc_low_en       : std_logic;
205 
signal pc_high_en      : std_logic;
206 
 
207 
signal offset_brbx     : std_logic_vector (15 downto 0);    -- OFFSET FOR BRCS/BRCC   INSTRUCTION  !!CHECKED
208 
signal offset_rxx      : std_logic_vector (15 downto 0);    -- OFFSET FOR RJMP/RCALL  INSTRUCTION  !!CHECKED
209 
 
210 
signal pa15_pm         : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM)
211 
 
212 
signal alu_reg_wr      : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE
213 
 
214 
-- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC
215 
 
216 
--! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL
217 
-- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE !
218 
-- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS  AND INTERRUPT
219 
 
220 
signal reg_file_adr_space  : std_logic; -- ACCSESS TO THE REGISTER FILE
221 
signal io_file_adr_space   : std_logic; -- ACCSESS TO THE I/O FILE
222 
 
223 
-- STATE MACHINES SIGNALS
224 
signal irq_start      : std_logic;
225 
 
226 
signal nirq_st0       : std_logic;
227 
signal irq_st1        : std_logic;
228 
signal irq_st2        : std_logic;
229 
signal irq_st3        : std_logic;
230 
 
231 
signal ncall_st0      : std_logic;
232 
signal call_st1       : std_logic;
233 
signal call_st2       : std_logic;
234 
signal call_st3       : std_logic;
235 
 
236 
signal nrcall_st0     : std_logic;
237 
signal rcall_st1      : std_logic;
238 
signal rcall_st2      : std_logic;
239 
 
240 
signal nicall_st0     : std_logic;
241 
signal icall_st1      : std_logic;
242 
signal icall_st2      : std_logic;
243 
 
244 
signal njmp_st0       : std_logic;
245 
signal jmp_st1        : std_logic;
246 
signal jmp_st2        : std_logic;
247 
 
248 
signal ijmp_st        : std_logic;
249 
 
250 
signal rjmp_st        : std_logic;
251 
 
252 
signal nret_st0       : std_logic;
253 
signal ret_st1        : std_logic;
254 
signal ret_st2        : std_logic;
255 
signal ret_st3        : std_logic;
256 
 
257 
signal nreti_st0      : std_logic;
258 
signal reti_st1       : std_logic;
259 
signal reti_st2       : std_logic;
260 
signal reti_st3       : std_logic;
261 
 
262 
signal brxx_st        : std_logic;  -- BRANCHES
263 
 
264 
signal adiw_st        : std_logic;
265 
signal sbiw_st        : std_logic;
266 
 
267 
signal nskip_inst_st0 : std_logic;
268 
signal skip_inst_st1  : std_logic;
269 
signal skip_inst_st2  : std_logic;  -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE
270 
 
271 
signal skip_inst_start  : std_logic;
272 
 
273 
signal nlpm_st0       : std_logic;
274 
signal lpm_st1        : std_logic;
275 
signal lpm_st2        : std_logic;
276 
 
277 
signal nelpm_st0      : std_logic;
278 
signal elpm_st1       : std_logic;
279 
signal elpm_st2       : std_logic;
280 
 
281 
--signal nsts_st0       : std_logic;
282 
--signal sts_st1        : std_logic;
283 
--signal sts_st2        : std_logic;
284 
 
285 
signal sts_st         : std_logic;
286 
 
287 
--signal nlds_st0       : std_logic;
288 
--signal lds_st1        : std_logic;
289 
--signal lds_st2        : std_logic;
290 
 
291 
signal lds_st           : std_logic;
292 
 
293 
signal st_st          : std_logic;
294 
signal ld_st          : std_logic;
295 
 
296 
signal sbi_st         : std_logic;
297 
signal cbi_st         : std_logic;
298 
 
299 
signal push_st        : std_logic;
300 
signal pop_st         : std_logic;
301 
 
302 
-- INTERNAL STATE MACHINES
303 
signal nop_insert_st  : std_logic;
304 
signal cpu_busy       : std_logic;
305 
 
306 
-- INTERNAL COPIES OF OUTPUTS
307 
signal pc_int              : std_logic_vector (15 downto 0);
308 
signal adr_int             : std_logic_vector (5 downto 0);
309 
signal iore_int                    : std_logic;
310 
signal iowe_int            : std_logic;
311 
signal ramadr_int          : std_logic_vector (15 downto 0);
312 
signal ramre_int           : std_logic;
313 
signal ramwe_int           : std_logic;
314 
signal dbusout_int         : std_logic_vector (7 downto 0);
315 
 
316 
-- COMMAND REGISTER
317 
signal instruction_reg      : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER
318 
signal instruction_code_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTION
319 
signal instruction_reg_ena  : std_logic;                               -- CLOCK ENABLE
320 
 
321 
 
322 
-- IRQ INTERNAL LOGIC
323 
signal irq_int              : std_logic;
324 
signal irq_vector_adr       : std_logic_vector(15 downto 0);
325 
 
326 
-- INTERRUPT RELATING REGISTERS
327 
signal pc_for_interrupt : std_logic_vector(15 downto 0);
328 
 
329 
-- DATA EXTRACTOR SIGNALS
330 
signal dex_dat8_immed  : std_logic_vector (7 downto 0);  -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDI
331 
signal dex_dat6_immed  : std_logic_vector (5 downto 0);  -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIW
332 
signal dex_adr12mem_s  : std_logic_vector (11 downto 0); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMP
333 
signal dex_adr6port    : std_logic_vector (5 downto 0);  -- I/O PORT ADDRESS -> IN,OUT
334 
signal dex_adr5port    : std_logic_vector (4 downto 0);  -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBIS
335 
signal dex_adr_disp    : std_logic_vector (5 downto 0);  -- DISPLACEMENT FO ADDDRESS -> STD,LDD
336 
signal dex_condition   : std_logic_vector (2 downto 0);  -- CONDITION -> BRBC,BRBS
337 
signal dex_bitnum_sreg : std_logic_vector (2 downto 0);  -- NUMBER OF BIT IN SREG -> BCLR,BSET
338 
signal dex_adrreg_r    : std_logic_vector (4 downto 0);  -- SOURCE REGISTER ADDRESS -> .......
339 
signal dex_adrreg_d    : std_logic_vector (4 downto 0);  -- DESTINATION REGISTER ADDRESS -> ......
340 
signal dex_bitop_bitnum : std_logic_vector(2 downto 0);  -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKED
341 
signal dex_brxx_offset : std_logic_vector (6 downto 0);  -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKED
342 
signal dex_adiw_sbiw_reg_adr  : std_logic_vector (1 downto 0);  -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
343 
 
344 
signal dex_adrreg_d_latched : std_logic_vector (4 downto 0);   --  STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONS
345 
signal gp_reg_tmp           : std_logic_vector (7 downto 0);   --  STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONS
346 
signal cbi_sbi_io_adr_tmp   : std_logic_vector (4 downto 0);   --  STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
347 
signal cbi_sbi_bit_num_tmp  : std_logic_vector (2 downto 0);   --  STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
348 
 
349 
-- INSTRUCTIONS DECODER SIGNALS
350 
 
351 
signal idc_adc     : std_logic; -- INSTRUCTION ADC
352 
signal idc_add     : std_logic; -- INSTRUCTION ADD
353 
signal idc_adiw    : std_logic; -- INSTRUCTION ADIW
354 
signal idc_and     : std_logic; -- INSTRUCTION AND
355 
signal idc_andi    : std_logic; -- INSTRUCTION ANDI
356 
signal idc_asr     : std_logic; -- INSTRUCTION ASR
357 
 
358 
signal idc_bclr    : std_logic; -- INSTRUCTION BCLR
359 
signal idc_bld     : std_logic; -- INSTRUCTION BLD
360 
signal idc_brbc    : std_logic; -- INSTRUCTION BRBC
361 
signal idc_brbs    : std_logic; -- INSTRUCTION BRBS
362 
signal idc_bset    : std_logic; -- INSTRUCTION BSET
363 
signal idc_bst     : std_logic; -- INSTRUCTION BST
364 
 
365 
signal idc_call    : std_logic; -- INSTRUCTION CALL
366 
signal idc_cbi     : std_logic; -- INSTRUCTION CBI
367 
signal idc_com     : std_logic; -- INSTRUCTION COM
368 
signal idc_cp      : std_logic; -- INSTRUCTION CP
369 
signal idc_cpc     : std_logic; -- INSTRUCTION CPC
370 
signal idc_cpi     : std_logic; -- INSTRUCTION CPI
371 
signal idc_cpse    : std_logic; -- INSTRUCTION CPSE
372 
 
373 
signal idc_dec     : std_logic; -- INSTRUCTION DEC
374 
 
375 
signal idc_elpm    : std_logic; -- INSTRUCTION ELPM
376 
signal idc_eor     : std_logic; -- INSTRUCTION EOR
377 
 
378 
signal idc_icall   : std_logic; -- INSTRUCTION ICALL
379 
signal idc_ijmp    : std_logic; -- INSTRUCTION IJMP
380 
 
381 
signal idc_in      : std_logic; -- INSTRUCTION IN
382 
signal idc_inc     : std_logic; -- INSTRUCTION INC
383 
 
384 
signal idc_jmp     : std_logic; -- INSTRUCTION JMP
385 
 
386 
signal idc_ld_x    : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-X
387 
signal idc_ld_y    : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Y
388 
signal idc_ldd_y   : std_logic; -- INSTRUCTION LDD Rx,Y+q
389 
signal idc_ld_z    : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Z
390 
signal idc_ldd_z   : std_logic; -- INSTRUCTION LDD Rx,Z+q
391 
 
392 
signal idc_ldi     : std_logic; -- INSTRUCTION LDI
393 
signal idc_lds     : std_logic; -- INSTRUCTION LDS
394 
signal idc_lpm     : std_logic; -- INSTRUCTION LPM
395 
signal idc_lsr     : std_logic; -- INSTRUCTION LSR
396 
 
397 
signal idc_mov     : std_logic; -- INSTRUCTION MOV
398 
signal idc_mul     : std_logic; -- INSTRUCTION MUL
399 
 
400 
signal idc_neg     : std_logic; -- INSTRUCTION NEG
401 
signal idc_nop     : std_logic; -- INSTRUCTION NOP
402 
 
403 
signal idc_or      : std_logic; -- INSTRUCTION OR
404 
signal idc_ori     : std_logic; -- INSTRUCTION ORI
405 
signal idc_out     : std_logic; -- INSTRUCTION OUT
406 
 
407 
signal idc_pop     : std_logic; -- INSTRUCTION POP
408 
signal idc_push    : std_logic; -- INSTRUCTION PUSH
409 
 
410 
signal idc_rcall   : std_logic; -- INSTRUCTION RCALL
411 
signal idc_ret     : std_logic; -- INSTRUCTION RET
412 
signal idc_reti    : std_logic; -- INSTRUCTION RETI
413 
signal idc_rjmp    : std_logic; -- INSTRUCTION RJMP
414 
signal idc_ror     : std_logic; -- INSTRUCTION ROR
415 
 
416 
signal idc_sbc     : std_logic; -- INSTRUCTION SBC
417 
signal idc_sbci    : std_logic; -- INSTRUCTION SBCI
418 
signal idc_sbi     : std_logic; -- INSTRUCTION SBI
419 
signal idc_sbic    : std_logic; -- INSTRUCTION SBIC
420 
signal idc_sbis    : std_logic; -- INSTRUCTION SBIS
421 
signal idc_sbiw    : std_logic; -- INSTRUCTION SBIW
422 
signal idc_sbrc    : std_logic; -- INSTRUCTION SBRC
423 
signal idc_sbrs    : std_logic; -- INSTRUCTION SBRS
424 
signal idc_sleep   : std_logic; -- INSTRUCTION SLEEP
425 
 
426 
signal idc_st_x    : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rx
427 
signal idc_st_y    : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rx
428 
signal idc_std_y   : std_logic; -- INSTRUCTION LDD Y+q,Rx
429 
signal idc_st_z    : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rx
430 
signal idc_std_z   : std_logic; -- INSTRUCTION LDD Z+q,Rx
431 
 
432 
signal idc_sts     : std_logic; -- INSTRUCTION STS
433 
signal idc_sub     : std_logic; -- INSTRUCTION SUB
434 
signal idc_subi    : std_logic; -- INSTRUCTION SUBI
435 
signal idc_swap    : std_logic; -- INSTRUCTION SWAP
436 
 
437 
signal idc_wdr     : std_logic; -- INSTRUCTION WDR
438 
 
439 
-- ADDITIONAL SIGNALS
440 
signal idc_psinc   :  std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONS
441 
signal idc_prdec   :  std_logic; -- PRE DECREMENT  FLAG FOR LD,ST INSTRUCTIONS
442 
 
443 
-- ##################################################
444 
 
445 
-- SREG FLAGS WRITE ENABLE SIGNALS
446 
 
447 
--alias sreg_c_wr_en  : std_logic is sreg_fl_wr_en(0);
448 
--alias sreg_z_wr_en  : std_logic is sreg_fl_wr_en(1);
449 
--alias sreg_n_wr_en  : std_logic is sreg_fl_wr_en(2);
450 
--alias sreg_v_wr_en  : std_logic is sreg_fl_wr_en(3);
451 
--alias sreg_s_wr_en  : std_logic is sreg_fl_wr_en(4);
452 
--alias sreg_h_wr_en  : std_logic is sreg_fl_wr_en(5);
453 
--alias sreg_t_wr_en  : std_logic is sreg_fl_wr_en(6);
454 
--alias sreg_i_wr_en  : std_logic is sreg_fl_wr_en(7);
455 
 
456 
signal sreg_c_wr_en  : std_logic; --  is sreg_fl_wr_en(0);
457 
signal sreg_z_wr_en  : std_logic; --  is sreg_fl_wr_en(1);
458 
signal sreg_n_wr_en  : std_logic; --  is sreg_fl_wr_en(2);
459 
signal sreg_v_wr_en  : std_logic; --  is sreg_fl_wr_en(3);
460 
signal sreg_s_wr_en  : std_logic; --  is sreg_fl_wr_en(4);
461 
signal sreg_h_wr_en  : std_logic; --  is sreg_fl_wr_en(5);
462 
signal sreg_t_wr_en  : std_logic; --  is sreg_fl_wr_en(6);
463 
signal sreg_i_wr_en  : std_logic; --  is sreg_fl_wr_en(7);
464 
 
465 
signal sreg_bop_wr_en : std_logic_vector (7 downto 0);
466 
 
467 
signal sreg_adr_eq  : std_logic;
468 
-- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
469 
 
470 
signal inst_cml_2 :  std_logic_vector ( 15 downto 0 );
471 
signal inst_cml_1 :  std_logic_vector ( 15 downto 0 );
472 
signal sp_ndown_up_cml_out :  std_logic;
473 
signal sp_en_cml_out :  std_logic;
474 
signal cpuwait_cml_2 :  std_logic;
475 
signal cpuwait_cml_1 :  std_logic;
476 
signal reg_rd_in_cml_out :  std_logic_vector ( 7 downto 0 );
477 
signal dbusin_cml_2 :  std_logic_vector ( 7 downto 0 );
478 
signal irqlines_cml_2 :  std_logic_vector ( 22 downto 0 );
479 
signal irqlines_cml_1 :  std_logic_vector ( 22 downto 0 );
480 
signal reg_rd_out_cml_2 :  std_logic_vector ( 7 downto 0 );
481 
signal reg_rr_out_cml_2 :  std_logic_vector ( 7 downto 0 );
482 
signal reg_rr_out_cml_1 :  std_logic_vector ( 7 downto 0 );
483 
signal spl_out_cml_2 :  std_logic_vector ( 7 downto 0 );
484 
signal sph_out_cml_2 :  std_logic_vector ( 7 downto 0 );
485 
signal rampz_out_cml_2 :  std_logic_vector ( 7 downto 0 );
486 
signal bitpr_io_out_cml_1 :  std_logic_vector ( 7 downto 0 );
487 
signal bit_test_op_out_cml_2 :  std_logic;
488 
signal irqack_cml_out :  std_logic;
489 
signal irqack_int_cml_2 :  std_logic;
490 
signal irqack_int_cml_1 :  std_logic;
491 
signal irqackad_cml_out :  std_logic_vector ( 4 downto 0 );
492 
signal irqackad_int_cml_2 :  std_logic_vector ( irqackad 'range);
493 
signal irqackad_int_cml_1 :  std_logic_vector ( irqackad 'range);
494 
signal two_word_inst_cml_2 :  std_logic;
495 
signal adiw_sbiw_encoder_out_cml_2 :  std_logic_vector ( 4 downto 0 );
496 
signal adiw_sbiw_encoder_out_cml_1 :  std_logic_vector ( 4 downto 0 );
497 
signal adiw_sbiw_encoder_mux_out_cml_2 :  std_logic_vector ( 4 downto 0 );
498 
signal adiw_sbiw_encoder_mux_out_cml_1 :  std_logic_vector ( 4 downto 0 );
499 
signal program_counter_tmp_cml_2 :  std_logic_vector ( 15 downto 0 );
500 
signal program_counter_tmp_cml_1 :  std_logic_vector ( 15 downto 0 );
501 
signal program_counter_cml_2 :  std_logic_vector ( 15 downto 0 );
502 
signal program_counter_cml_1 :  std_logic_vector ( 15 downto 0 );
503 
signal program_counter_high_fr_cml_2 :  std_logic_vector ( 7 downto 0 );
504 
signal program_counter_high_fr_cml_1 :  std_logic_vector ( 7 downto 0 );
505 
signal pc_low_cml_2 :  std_logic_vector ( 7 downto 0 );
506 
signal pc_low_cml_1 :  std_logic_vector ( 7 downto 0 );
507 
signal pc_high_cml_2 :  std_logic_vector ( 7 downto 0 );
508 
signal pc_high_cml_1 :  std_logic_vector ( 7 downto 0 );
509 
signal reg_rd_wr_cml_out :  std_logic;
510 
signal reg_file_adr_space_cml_2 :  std_logic;
511 
signal reg_file_adr_space_cml_1 :  std_logic;
512 
signal io_file_adr_space_cml_2 :  std_logic;
513 
signal io_file_adr_space_cml_1 :  std_logic;
514 
signal nirq_st0_cml_2 :  std_logic;
515 
signal nirq_st0_cml_1 :  std_logic;
516 
signal irq_st1_cml_2 :  std_logic;
517 
signal irq_st1_cml_1 :  std_logic;
518 
signal irq_st2_cml_2 :  std_logic;
519 
signal irq_st2_cml_1 :  std_logic;
520 
signal irq_st3_cml_2 :  std_logic;
521 
signal irq_st3_cml_1 :  std_logic;
522 
signal ncall_st0_cml_2 :  std_logic;
523 
signal ncall_st0_cml_1 :  std_logic;
524 
signal call_st1_cml_2 :  std_logic;
525 
signal call_st1_cml_1 :  std_logic;
526 
signal call_st2_cml_2 :  std_logic;
527 
signal call_st2_cml_1 :  std_logic;
528 
signal call_st3_cml_2 :  std_logic;
529 
signal call_st3_cml_1 :  std_logic;
530 
signal nrcall_st0_cml_2 :  std_logic;
531 
signal nrcall_st0_cml_1 :  std_logic;
532 
signal rcall_st1_cml_2 :  std_logic;
533 
signal rcall_st1_cml_1 :  std_logic;
534 
signal rcall_st2_cml_2 :  std_logic;
535 
signal rcall_st2_cml_1 :  std_logic;
536 
signal nicall_st0_cml_2 :  std_logic;
537 
signal nicall_st0_cml_1 :  std_logic;
538 
signal icall_st1_cml_2 :  std_logic;
539 
signal icall_st1_cml_1 :  std_logic;
540 
signal icall_st2_cml_2 :  std_logic;
541 
signal icall_st2_cml_1 :  std_logic;
542 
signal njmp_st0_cml_2 :  std_logic;
543 
signal njmp_st0_cml_1 :  std_logic;
544 
signal jmp_st1_cml_2 :  std_logic;
545 
signal jmp_st1_cml_1 :  std_logic;
546 
signal jmp_st2_cml_2 :  std_logic;
547 
signal jmp_st2_cml_1 :  std_logic;
548 
signal ijmp_st_cml_2 :  std_logic;
549 
signal ijmp_st_cml_1 :  std_logic;
550 
signal rjmp_st_cml_2 :  std_logic;
551 
signal rjmp_st_cml_1 :  std_logic;
552 
signal nret_st0_cml_2 :  std_logic;
553 
signal nret_st0_cml_1 :  std_logic;
554 
signal ret_st1_cml_2 :  std_logic;
555 
signal ret_st1_cml_1 :  std_logic;
556 
signal ret_st2_cml_2 :  std_logic;
557 
signal ret_st2_cml_1 :  std_logic;
558 
signal ret_st3_cml_2 :  std_logic;
559 
signal ret_st3_cml_1 :  std_logic;
560 
signal nreti_st0_cml_2 :  std_logic;
561 
signal nreti_st0_cml_1 :  std_logic;
562 
signal reti_st1_cml_2 :  std_logic;
563 
signal reti_st1_cml_1 :  std_logic;
564 
signal reti_st2_cml_2 :  std_logic;
565 
signal reti_st2_cml_1 :  std_logic;
566 
signal sreg_fl_in_cml_out :  std_logic_vector ( 7 downto 0 );
567 
signal reti_st3_cml_2 :  std_logic;
568 
signal reti_st3_cml_1 :  std_logic;
569 
signal brxx_st_cml_2 :  std_logic;
570 
signal brxx_st_cml_1 :  std_logic;
571 
signal adiw_st_cml_2 :  std_logic;
572 
signal adiw_st_cml_1 :  std_logic;
573 
signal sbiw_st_cml_2 :  std_logic;
574 
signal sbiw_st_cml_1 :  std_logic;
575 
signal nskip_inst_st0_cml_2 :  std_logic;
576 
signal nskip_inst_st0_cml_1 :  std_logic;
577 
signal skip_inst_st1_cml_2 :  std_logic;
578 
signal skip_inst_st1_cml_1 :  std_logic;
579 
signal skip_inst_st2_cml_2 :  std_logic;
580 
signal skip_inst_st2_cml_1 :  std_logic;
581 
signal nlpm_st0_cml_2 :  std_logic;
582 
signal nlpm_st0_cml_1 :  std_logic;
583 
signal lpm_st1_cml_2 :  std_logic;
584 
signal lpm_st1_cml_1 :  std_logic;
585 
signal lpm_st2_cml_2 :  std_logic;
586 
signal lpm_st2_cml_1 :  std_logic;
587 
signal sts_st_cml_2 :  std_logic;
588 
signal sts_st_cml_1 :  std_logic;
589 
signal lds_st_cml_2 :  std_logic;
590 
signal lds_st_cml_1 :  std_logic;
591 
signal st_st_cml_2 :  std_logic;
592 
signal st_st_cml_1 :  std_logic;
593 
signal ld_st_cml_2 :  std_logic;
594 
signal ld_st_cml_1 :  std_logic;
595 
signal sbi_st_cml_2 :  std_logic;
596 
signal sbi_st_cml_1 :  std_logic;
597 
signal cbi_st_cml_2 :  std_logic;
598 
signal cbi_st_cml_1 :  std_logic;
599 
signal push_st_cml_2 :  std_logic;
600 
signal push_st_cml_1 :  std_logic;
601 
signal pop_st_cml_2 :  std_logic;
602 
signal pop_st_cml_1 :  std_logic;
603 
signal iowe_cml_out :  std_logic;
604 
signal iowe_int_cml_2 :  std_logic;
605 
signal ramadr_int_cml_2 :  std_logic_vector ( 15 downto 0 );
606 
signal ramadr_int_cml_1 :  std_logic_vector ( 15 downto 0 );
607 
signal ramre_int_cml_2 :  std_logic;
608 
signal ramre_int_cml_1 :  std_logic;
609 
signal ramwe_int_cml_2 :  std_logic;
610 
signal ramwe_int_cml_1 :  std_logic;
611 
signal dbusout_int_route_cml_out :  std_logic_vector ( 7 downto 0 );
612 
signal dbusout_int_cml_2 :  std_logic_vector ( 7 downto 0 );
613 
signal instruction_reg_cml_2 :  std_logic_vector ( 15 downto 0 );
614 
signal instruction_reg_cml_1 :  std_logic_vector ( 15 downto 0 );
615 
signal instruction_code_reg_cml_2 :  std_logic_vector ( 15 downto 0 );
616 
signal instruction_code_reg_cml_1 :  std_logic_vector ( 15 downto 0 );
617 
signal pc_for_interrupt_cml_2 :  std_logic_vector ( 15 downto 0 );
618 
signal pc_for_interrupt_cml_1 :  std_logic_vector ( 15 downto 0 );
619 
signal dex_dat8_immed_cml_2 :  std_logic_vector ( 7 downto 0 );
620 
signal dex_dat8_immed_cml_1 :  std_logic_vector ( 7 downto 0 );
621 
signal dex_adr5port_cml_2 :  std_logic_vector ( 4 downto 0 );
622 
signal dex_adrreg_d_cml_2 :  std_logic_vector ( 4 downto 0 );
623 
signal dex_adrreg_d_cml_1 :  std_logic_vector ( 4 downto 0 );
624 
signal dex_bitop_bitnum_cml_2 :  std_logic_vector ( 2 downto 0 );
625 
signal dex_bitop_bitnum_cml_1 :  std_logic_vector ( 2 downto 0 );
626 
signal dex_adrreg_d_latched_cml_2 :  std_logic_vector ( 4 downto 0 );
627 
signal dex_adrreg_d_latched_cml_1 :  std_logic_vector ( 4 downto 0 );
628 
signal gp_reg_tmp_cml_2 :  std_logic_vector ( 7 downto 0 );
629 
signal gp_reg_tmp_cml_1 :  std_logic_vector ( 7 downto 0 );
630 
signal cbi_sbi_io_adr_tmp_cml_2 :  std_logic_vector ( 4 downto 0 );
631 
signal cbi_sbi_io_adr_tmp_cml_1 :  std_logic_vector ( 4 downto 0 );
632 
signal cbi_sbi_bit_num_tmp_cml_2 :  std_logic_vector ( 2 downto 0 );
633 
signal cbi_sbi_bit_num_tmp_cml_1 :  std_logic_vector ( 2 downto 0 );
634 
signal idc_adc_cml_2 :  std_logic;
635 
signal idc_adc_cml_1 :  std_logic;
636 
signal idc_add_cml_2 :  std_logic;
637 
signal idc_adiw_out_cml_out :  std_logic;
638 
signal idc_adiw_cml_2 :  std_logic;
639 
signal idc_adiw_cml_1 :  std_logic;
640 
signal idc_and_cml_2 :  std_logic;
641 
signal idc_andi_out_cml_out :  std_logic;
642 
signal idc_andi_cml_2 :  std_logic;
643 
signal idc_andi_cml_1 :  std_logic;
644 
signal idc_asr_cml_2 :  std_logic;
645 
signal idc_bclr_out_cml_out :  std_logic;
646 
signal idc_bclr_cml_2 :  std_logic;
647 
signal idc_brbc_cml_2 :  std_logic;
648 
signal idc_brbs_cml_2 :  std_logic;
649 
signal idc_bset_out_cml_out :  std_logic;
650 
signal idc_bset_cml_2 :  std_logic;
651 
signal idc_call_cml_2 :  std_logic;
652 
signal idc_cbi_cml_2 :  std_logic;
653 
signal idc_cbi_cml_1 :  std_logic;
654 
signal idc_com_cml_2 :  std_logic;
655 
signal idc_cp_cml_2 :  std_logic;
656 
signal idc_cp_cml_1 :  std_logic;
657 
signal idc_cpc_cml_2 :  std_logic;
658 
signal idc_cpc_cml_1 :  std_logic;
659 
signal idc_cpi_cml_2 :  std_logic;
660 
signal idc_cpi_cml_1 :  std_logic;
661 
signal idc_cpse_cml_2 :  std_logic;
662 
signal idc_cpse_cml_1 :  std_logic;
663 
signal idc_dec_cml_2 :  std_logic;
664 
signal idc_eor_cml_2 :  std_logic;
665 
signal idc_icall_cml_2 :  std_logic;
666 
signal idc_icall_cml_1 :  std_logic;
667 
signal idc_ijmp_cml_2 :  std_logic;
668 
signal idc_in_cml_2 :  std_logic;
669 
signal idc_in_cml_1 :  std_logic;
670 
signal idc_inc_cml_2 :  std_logic;
671 
signal idc_jmp_cml_2 :  std_logic;
672 
signal reg_h_wr_cml_out :  std_logic;
673 
signal idc_ld_x_cml_2 :  std_logic;
674 
signal idc_ld_y_cml_2 :  std_logic;
675 
signal idc_ldd_y_cml_2 :  std_logic;
676 
signal idc_ld_z_cml_2 :  std_logic;
677 
signal idc_ldd_z_cml_2 :  std_logic;
678 
signal idc_ldi_cml_2 :  std_logic;
679 
signal idc_ldi_cml_1 :  std_logic;
680 
signal idc_lds_cml_2 :  std_logic;
681 
signal idc_lpm_cml_2 :  std_logic;
682 
signal idc_lsr_cml_2 :  std_logic;
683 
signal idc_neg_cml_2 :  std_logic;
684 
signal idc_or_cml_2 :  std_logic;
685 
signal idc_ori_out_cml_out :  std_logic;
686 
signal idc_ori_cml_2 :  std_logic;
687 
signal idc_ori_cml_1 :  std_logic;
688 
signal idc_out_cml_1 :  std_logic;
689 
signal idc_pop_cml_2 :  std_logic;
690 
signal idc_push_cml_2 :  std_logic;
691 
signal idc_push_cml_1 :  std_logic;
692 
signal idc_rcall_cml_2 :  std_logic;
693 
signal idc_rcall_cml_1 :  std_logic;
694 
signal idc_ret_cml_2 :  std_logic;
695 
signal idc_reti_out_cml_out :  std_logic;
696 
signal idc_reti_cml_2 :  std_logic;
697 
signal idc_rjmp_cml_2 :  std_logic;
698 
signal idc_ror_cml_2 :  std_logic;
699 
signal idc_ror_cml_1 :  std_logic;
700 
signal idc_sbc_cml_2 :  std_logic;
701 
signal idc_sbc_cml_1 :  std_logic;
702 
signal idc_sbci_cml_2 :  std_logic;
703 
signal idc_sbci_cml_1 :  std_logic;
704 
signal idc_sbi_cml_2 :  std_logic;
705 
signal idc_sbi_cml_1 :  std_logic;
706 
signal idc_sbic_out_cml_out :  std_logic;
707 
signal idc_sbic_cml_2 :  std_logic;
708 
signal idc_sbic_cml_1 :  std_logic;
709 
signal idc_sbis_out_cml_out :  std_logic;
710 
signal idc_sbis_cml_2 :  std_logic;
711 
signal idc_sbis_cml_1 :  std_logic;
712 
signal idc_sbiw_cml_2 :  std_logic;
713 
signal idc_sbiw_cml_1 :  std_logic;
714 
signal idc_sbrc_cml_2 :  std_logic;
715 
signal idc_sbrs_cml_2 :  std_logic;
716 
signal reg_h_adr_cml_out :  std_logic_vector ( 2 downto 0 );
717 
signal idc_st_x_cml_2 :  std_logic;
718 
signal idc_st_x_cml_1 :  std_logic;
719 
signal idc_st_y_cml_2 :  std_logic;
720 
signal idc_st_y_cml_1 :  std_logic;
721 
signal idc_std_y_cml_2 :  std_logic;
722 
signal idc_std_y_cml_1 :  std_logic;
723 
signal idc_st_z_cml_2 :  std_logic;
724 
signal idc_st_z_cml_1 :  std_logic;
725 
signal idc_std_z_cml_2 :  std_logic;
726 
signal idc_std_z_cml_1 :  std_logic;
727 
signal idc_sts_cml_2 :  std_logic;
728 
signal idc_sts_cml_1 :  std_logic;
729 
signal idc_sub_cml_2 :  std_logic;
730 
signal idc_sub_cml_1 :  std_logic;
731 
signal idc_subi_cml_2 :  std_logic;
732 
signal idc_subi_cml_1 :  std_logic;
733 
signal idc_swap_cml_2 :  std_logic;
734 
signal pre_dec_cml_out :  std_logic;
735 
signal idc_prdec_cml_2 :  std_logic;
736 
signal sreg_bop_wr_en_cml_2 :  std_logic_vector ( 7 downto 0 );
737 
signal sreg_adr_eq_cml_2 :  std_logic;
738 
 
739 
begin
740 
 
741 
 
742 
 
743 
process(cp2_cml_1) begin
744 
if (cp2_cml_1 = '1' and cp2_cml_1'event) then
745 
        inst_cml_1 <= inst;
746 
        cpuwait_cml_1 <= cpuwait;
747 
        irqlines_cml_1 <= irqlines;
748 
        reg_rr_out_cml_1 <= reg_rr_out;
749 
        bitpr_io_out_cml_1 <= bitpr_io_out;
750 
        irqack_int_cml_1 <= irqack_int;
751 
        irqackad_int_cml_1 <= irqackad_int;
752 
        adiw_sbiw_encoder_out_cml_1 <= adiw_sbiw_encoder_out;
753 
        adiw_sbiw_encoder_mux_out_cml_1 <= adiw_sbiw_encoder_mux_out;
754 
        program_counter_tmp_cml_1 <= program_counter_tmp;
755 
        program_counter_cml_1 <= program_counter;
756 
        program_counter_high_fr_cml_1 <= program_counter_high_fr;
757 
        pc_low_cml_1 <= pc_low;
758 
        pc_high_cml_1 <= pc_high;
759 
        reg_file_adr_space_cml_1 <= reg_file_adr_space;
760 
        io_file_adr_space_cml_1 <= io_file_adr_space;
761 
        nirq_st0_cml_1 <= nirq_st0;
762 
        irq_st1_cml_1 <= irq_st1;
763 
        irq_st2_cml_1 <= irq_st2;
764 
        irq_st3_cml_1 <= irq_st3;
765 
        ncall_st0_cml_1 <= ncall_st0;
766 
        call_st1_cml_1 <= call_st1;
767 
        call_st2_cml_1 <= call_st2;
768 
        call_st3_cml_1 <= call_st3;
769 
        nrcall_st0_cml_1 <= nrcall_st0;
770 
        rcall_st1_cml_1 <= rcall_st1;
771 
        rcall_st2_cml_1 <= rcall_st2;
772 
        nicall_st0_cml_1 <= nicall_st0;
773 
        icall_st1_cml_1 <= icall_st1;
774 
        icall_st2_cml_1 <= icall_st2;
775 
        njmp_st0_cml_1 <= njmp_st0;
776 
        jmp_st1_cml_1 <= jmp_st1;
777 
        jmp_st2_cml_1 <= jmp_st2;
778 
        ijmp_st_cml_1 <= ijmp_st;
779 
        rjmp_st_cml_1 <= rjmp_st;
780 
        nret_st0_cml_1 <= nret_st0;
781 
        ret_st1_cml_1 <= ret_st1;
782 
        ret_st2_cml_1 <= ret_st2;
783 
        ret_st3_cml_1 <= ret_st3;
784 
        nreti_st0_cml_1 <= nreti_st0;
785 
        reti_st1_cml_1 <= reti_st1;
786 
        reti_st2_cml_1 <= reti_st2;
787 
        reti_st3_cml_1 <= reti_st3;
788 
        brxx_st_cml_1 <= brxx_st;
789 
        adiw_st_cml_1 <= adiw_st;
790 
        sbiw_st_cml_1 <= sbiw_st;
791 
        nskip_inst_st0_cml_1 <= nskip_inst_st0;
792 
        skip_inst_st1_cml_1 <= skip_inst_st1;
793 
        skip_inst_st2_cml_1 <= skip_inst_st2;
794 
        nlpm_st0_cml_1 <= nlpm_st0;
795 
        lpm_st1_cml_1 <= lpm_st1;
796 
        lpm_st2_cml_1 <= lpm_st2;
797 
        sts_st_cml_1 <= sts_st;
798 
        lds_st_cml_1 <= lds_st;
799 
        st_st_cml_1 <= st_st;
800 
        ld_st_cml_1 <= ld_st;
801 
        sbi_st_cml_1 <= sbi_st;
802 
        cbi_st_cml_1 <= cbi_st;
803 
        push_st_cml_1 <= push_st;
804 
        pop_st_cml_1 <= pop_st;
805 
        ramadr_int_cml_1 <= ramadr_int;
806 
        ramre_int_cml_1 <= ramre_int;
807 
        ramwe_int_cml_1 <= ramwe_int;
808 
        instruction_reg_cml_1 <= instruction_reg;
809 
        instruction_code_reg_cml_1 <= instruction_code_reg;
810 
        pc_for_interrupt_cml_1 <= pc_for_interrupt;
811 
        dex_dat8_immed_cml_1 <= dex_dat8_immed;
812 
        dex_adrreg_d_cml_1 <= dex_adrreg_d;
813 
        dex_bitop_bitnum_cml_1 <= dex_bitop_bitnum;
814 
        dex_adrreg_d_latched_cml_1 <= dex_adrreg_d_latched;
815 
        gp_reg_tmp_cml_1 <= gp_reg_tmp;
816 
        cbi_sbi_io_adr_tmp_cml_1 <= cbi_sbi_io_adr_tmp;
817 
        cbi_sbi_bit_num_tmp_cml_1 <= cbi_sbi_bit_num_tmp;
818 
        idc_adc_cml_1 <= idc_adc;
819 
        idc_adiw_cml_1 <= idc_adiw;
820 
        idc_andi_cml_1 <= idc_andi;
821 
        idc_cbi_cml_1 <= idc_cbi;
822 
        idc_cp_cml_1 <= idc_cp;
823 
        idc_cpc_cml_1 <= idc_cpc;
824 
        idc_cpi_cml_1 <= idc_cpi;
825 
        idc_cpse_cml_1 <= idc_cpse;
826 
        idc_icall_cml_1 <= idc_icall;
827 
        idc_in_cml_1 <= idc_in;
828 
        idc_ldi_cml_1 <= idc_ldi;
829 
        idc_ori_cml_1 <= idc_ori;
830 
        idc_out_cml_1 <= idc_out;
831 
        idc_push_cml_1 <= idc_push;
832 
        idc_rcall_cml_1 <= idc_rcall;
833 
        idc_ror_cml_1 <= idc_ror;
834 
        idc_sbc_cml_1 <= idc_sbc;
835 
        idc_sbci_cml_1 <= idc_sbci;
836 
        idc_sbi_cml_1 <= idc_sbi;
837 
        idc_sbic_cml_1 <= idc_sbic;
838 
        idc_sbis_cml_1 <= idc_sbis;
839 
        idc_sbiw_cml_1 <= idc_sbiw;
840 
        idc_st_x_cml_1 <= idc_st_x;
841 
        idc_st_y_cml_1 <= idc_st_y;
842 
        idc_std_y_cml_1 <= idc_std_y;
843 
        idc_st_z_cml_1 <= idc_st_z;
844 
        idc_std_z_cml_1 <= idc_std_z;
845 
        idc_sts_cml_1 <= idc_sts;
846 
        idc_sub_cml_1 <= idc_sub;
847 
        idc_subi_cml_1 <= idc_subi;
848 
end if;
849 
end process;
850 
 
851 
process(cp2_cml_2) begin
852 
if (cp2_cml_2 = '1' and cp2_cml_2'event) then
853 
        inst_cml_2 <= inst_cml_1;
854 
        cpuwait_cml_2 <= cpuwait_cml_1;
855 
        dbusin_cml_2 <= dbusin;
856 
        irqlines_cml_2 <= irqlines_cml_1;
857 
        reg_rd_out_cml_2 <= reg_rd_out;
858 
        reg_rr_out_cml_2 <= reg_rr_out_cml_1;
859 
        spl_out_cml_2 <= spl_out;
860 
        sph_out_cml_2 <= sph_out;
861 
        rampz_out_cml_2 <= rampz_out;
862 
        bit_test_op_out_cml_2 <= bit_test_op_out;
863 
        irqack_int_cml_2 <= irqack_int_cml_1;
864 
        irqackad_int_cml_2 <= irqackad_int_cml_1;
865 
        two_word_inst_cml_2 <= two_word_inst;
866 
        adiw_sbiw_encoder_out_cml_2 <= adiw_sbiw_encoder_out_cml_1;
867 
        adiw_sbiw_encoder_mux_out_cml_2 <= adiw_sbiw_encoder_mux_out_cml_1;
868 
        program_counter_tmp_cml_2 <= program_counter_tmp_cml_1;
869 
        program_counter_cml_2 <= program_counter_cml_1;
870 
        program_counter_high_fr_cml_2 <= program_counter_high_fr_cml_1;
871 
        pc_low_cml_2 <= pc_low_cml_1;
872 
        pc_high_cml_2 <= pc_high_cml_1;
873 
        reg_file_adr_space_cml_2 <= reg_file_adr_space_cml_1;
874 
        io_file_adr_space_cml_2 <= io_file_adr_space_cml_1;
875 
        nirq_st0_cml_2 <= nirq_st0_cml_1;
876 
        irq_st1_cml_2 <= irq_st1_cml_1;
877 
        irq_st2_cml_2 <= irq_st2_cml_1;
878 
        irq_st3_cml_2 <= irq_st3_cml_1;
879 
        ncall_st0_cml_2 <= ncall_st0_cml_1;
880 
        call_st1_cml_2 <= call_st1_cml_1;
881 
        call_st2_cml_2 <= call_st2_cml_1;
882 
        call_st3_cml_2 <= call_st3_cml_1;
883 
        nrcall_st0_cml_2 <= nrcall_st0_cml_1;
884 
        rcall_st1_cml_2 <= rcall_st1_cml_1;
885 
        rcall_st2_cml_2 <= rcall_st2_cml_1;
886 
        nicall_st0_cml_2 <= nicall_st0_cml_1;
887 
        icall_st1_cml_2 <= icall_st1_cml_1;
888 
        icall_st2_cml_2 <= icall_st2_cml_1;
889 
        njmp_st0_cml_2 <= njmp_st0_cml_1;
890 
        jmp_st1_cml_2 <= jmp_st1_cml_1;
891 
        jmp_st2_cml_2 <= jmp_st2_cml_1;
892 
        ijmp_st_cml_2 <= ijmp_st_cml_1;
893 
        rjmp_st_cml_2 <= rjmp_st_cml_1;
894 
        nret_st0_cml_2 <= nret_st0_cml_1;
895 
        ret_st1_cml_2 <= ret_st1_cml_1;
896 
        ret_st2_cml_2 <= ret_st2_cml_1;
897 
        ret_st3_cml_2 <= ret_st3_cml_1;
898 
        nreti_st0_cml_2 <= nreti_st0_cml_1;
899 
        reti_st1_cml_2 <= reti_st1_cml_1;
900 
        reti_st2_cml_2 <= reti_st2_cml_1;
901 
        reti_st3_cml_2 <= reti_st3_cml_1;
902 
        brxx_st_cml_2 <= brxx_st_cml_1;
903 
        adiw_st_cml_2 <= adiw_st_cml_1;
904 
        sbiw_st_cml_2 <= sbiw_st_cml_1;
905 
        nskip_inst_st0_cml_2 <= nskip_inst_st0_cml_1;
906 
        skip_inst_st1_cml_2 <= skip_inst_st1_cml_1;
907 
        skip_inst_st2_cml_2 <= skip_inst_st2_cml_1;
908 
        nlpm_st0_cml_2 <= nlpm_st0_cml_1;
909 
        lpm_st1_cml_2 <= lpm_st1_cml_1;
910 
        lpm_st2_cml_2 <= lpm_st2_cml_1;
911 
        sts_st_cml_2 <= sts_st_cml_1;
912 
        lds_st_cml_2 <= lds_st_cml_1;
913 
        st_st_cml_2 <= st_st_cml_1;
914 
        ld_st_cml_2 <= ld_st_cml_1;
915 
        sbi_st_cml_2 <= sbi_st_cml_1;
916 
        cbi_st_cml_2 <= cbi_st_cml_1;
917 
        push_st_cml_2 <= push_st_cml_1;
918 
        pop_st_cml_2 <= pop_st_cml_1;
919 
        iowe_int_cml_2 <= iowe_int;
920 
        ramadr_int_cml_2 <= ramadr_int_cml_1;
921 
        ramre_int_cml_2 <= ramre_int_cml_1;
922 
        ramwe_int_cml_2 <= ramwe_int_cml_1;
923 
        dbusout_int_cml_2 <= dbusout_int;
924 
        instruction_reg_cml_2 <= instruction_reg_cml_1;
925 
        instruction_code_reg_cml_2 <= instruction_code_reg_cml_1;
926 
        pc_for_interrupt_cml_2 <= pc_for_interrupt_cml_1;
927 
        dex_dat8_immed_cml_2 <= dex_dat8_immed_cml_1;
928 
        dex_adr5port_cml_2 <= dex_adr5port;
929 
        dex_adrreg_d_cml_2 <= dex_adrreg_d_cml_1;
930 
        dex_bitop_bitnum_cml_2 <= dex_bitop_bitnum_cml_1;
931 
        dex_adrreg_d_latched_cml_2 <= dex_adrreg_d_latched_cml_1;
932 
        gp_reg_tmp_cml_2 <= gp_reg_tmp_cml_1;
933 
        cbi_sbi_io_adr_tmp_cml_2 <= cbi_sbi_io_adr_tmp_cml_1;
934 
        cbi_sbi_bit_num_tmp_cml_2 <= cbi_sbi_bit_num_tmp_cml_1;
935 
        idc_adc_cml_2 <= idc_adc_cml_1;
936 
        idc_add_cml_2 <= idc_add;
937 
        idc_adiw_cml_2 <= idc_adiw_cml_1;
938 
        idc_and_cml_2 <= idc_and;
939 
        idc_andi_cml_2 <= idc_andi_cml_1;
940 
        idc_asr_cml_2 <= idc_asr;
941 
        idc_bclr_cml_2 <= idc_bclr;
942 
        idc_brbc_cml_2 <= idc_brbc;
943 
        idc_brbs_cml_2 <= idc_brbs;
944 
        idc_bset_cml_2 <= idc_bset;
945 
        idc_call_cml_2 <= idc_call;
946 
        idc_cbi_cml_2 <= idc_cbi_cml_1;
947 
        idc_com_cml_2 <= idc_com;
948 
        idc_cp_cml_2 <= idc_cp_cml_1;
949 
        idc_cpc_cml_2 <= idc_cpc_cml_1;
950 
        idc_cpi_cml_2 <= idc_cpi_cml_1;
951 
        idc_cpse_cml_2 <= idc_cpse_cml_1;
952 
        idc_dec_cml_2 <= idc_dec;
953 
        idc_eor_cml_2 <= idc_eor;
954 
        idc_icall_cml_2 <= idc_icall_cml_1;
955 
        idc_ijmp_cml_2 <= idc_ijmp;
956 
        idc_in_cml_2 <= idc_in_cml_1;
957 
        idc_inc_cml_2 <= idc_inc;
958 
        idc_jmp_cml_2 <= idc_jmp;
959 
        idc_ld_x_cml_2 <= idc_ld_x;
960 
        idc_ld_y_cml_2 <= idc_ld_y;
961 
        idc_ldd_y_cml_2 <= idc_ldd_y;
962 
        idc_ld_z_cml_2 <= idc_ld_z;
963 
        idc_ldd_z_cml_2 <= idc_ldd_z;
964 
        idc_ldi_cml_2 <= idc_ldi_cml_1;
965 
        idc_lds_cml_2 <= idc_lds;
966 
        idc_lpm_cml_2 <= idc_lpm;
967 
        idc_lsr_cml_2 <= idc_lsr;
968 
        idc_neg_cml_2 <= idc_neg;
969 
        idc_or_cml_2 <= idc_or;
970 
        idc_ori_cml_2 <= idc_ori_cml_1;
971 
        idc_pop_cml_2 <= idc_pop;
972 
        idc_push_cml_2 <= idc_push_cml_1;
973 
        idc_rcall_cml_2 <= idc_rcall_cml_1;
974 
        idc_ret_cml_2 <= idc_ret;
975 
        idc_reti_cml_2 <= idc_reti;
976 
        idc_rjmp_cml_2 <= idc_rjmp;
977 
        idc_ror_cml_2 <= idc_ror_cml_1;
978 
        idc_sbc_cml_2 <= idc_sbc_cml_1;
979 
        idc_sbci_cml_2 <= idc_sbci_cml_1;
980 
        idc_sbi_cml_2 <= idc_sbi_cml_1;
981 
        idc_sbic_cml_2 <= idc_sbic_cml_1;
982 
        idc_sbis_cml_2 <= idc_sbis_cml_1;
983 
        idc_sbiw_cml_2 <= idc_sbiw_cml_1;
984 
        idc_sbrc_cml_2 <= idc_sbrc;
985 
        idc_sbrs_cml_2 <= idc_sbrs;
986 
        idc_st_x_cml_2 <= idc_st_x_cml_1;
987 
        idc_st_y_cml_2 <= idc_st_y_cml_1;
988 
        idc_std_y_cml_2 <= idc_std_y_cml_1;
989 
        idc_st_z_cml_2 <= idc_st_z_cml_1;
990 
        idc_std_z_cml_2 <= idc_std_z_cml_1;
991 
        idc_sts_cml_2 <= idc_sts_cml_1;
992 
        idc_sub_cml_2 <= idc_sub_cml_1;
993 
        idc_subi_cml_2 <= idc_subi_cml_1;
994 
        idc_swap_cml_2 <= idc_swap;
995 
        idc_prdec_cml_2 <= idc_prdec;
996 
        sreg_bop_wr_en_cml_2 <= sreg_bop_wr_en;
997 
        sreg_adr_eq_cml_2 <= sreg_adr_eq;
998 
end if;
999 
end process;
1000 
sp_ndown_up <= sp_ndown_up_cml_out;
1001 
sp_en <= sp_en_cml_out;
1002 
reg_rd_in <= reg_rd_in_cml_out;
1003 
irqack <= irqack_cml_out;
1004 
irqackad <= irqackad_cml_out;
1005 
reg_rd_wr <= reg_rd_wr_cml_out;
1006 
sreg_fl_in <= sreg_fl_in_cml_out;
1007 
iowe <= iowe_cml_out;
1008 
dbusout_int_route <= dbusout_int_route_cml_out;
1009 
idc_adiw_out <= idc_adiw_out_cml_out;
1010 
idc_andi_out <= idc_andi_out_cml_out;
1011 
idc_bclr_out <= idc_bclr_out_cml_out;
1012 
idc_bset_out <= idc_bset_out_cml_out;
1013 
reg_h_wr <= reg_h_wr_cml_out;
1014 
idc_ori_out <= idc_ori_out_cml_out;
1015 
idc_reti_out <= idc_reti_out_cml_out;
1016 
idc_sbic_out <= idc_sbic_out_cml_out;
1017 
idc_sbis_out <= idc_sbis_out_cml_out;
1018 
reg_h_adr <= reg_h_adr_cml_out;
1019 
pre_dec <= pre_dec_cml_out;
1020 
 
1021 
 
1022 
sreg_fl_wr_en <= sreg_i_wr_en & sreg_t_wr_en & sreg_h_wr_en & sreg_s_wr_en & sreg_v_wr_en & sreg_n_wr_en & sreg_z_wr_en & sreg_c_wr_en;
1023 
 
1024 
 
1025 
-- INSTRUCTION FETCH
1026 
instruction_reg_ena <= '1'; -- FOR TEST
1027 
 
1028 
-- SynEDA CoreMultiplier
1029 
-- assignment(s): instruction_reg
1030 
-- replace(s): inst, instruction_reg
1031 
 
1032 
instruction_fetch:process(cp2,ireset)
1033 
begin
1034 
if ireset='0' then                              -- RESET
1035 
instruction_reg <= (others => '0');
1036 
elsif (cp2='1' and cp2'event) then instruction_reg <= instruction_reg_cml_2;            -- CLOCK
1037 
 if (cp2en='1') then                                                      -- Clock enable
1038 
  if instruction_reg_ena='1' then
1039 
   instruction_reg <= inst_cml_2;
1040 
  end if;
1041 
 end if;
1042 
end if;
1043 
end process;
1044 
 
1045 
-- SynEDA CoreMultiplier
1046 
-- assignment(s): two_word_inst
1047 
-- replace(s): instruction_reg
1048 
 
1049 
-- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
1050 
two_word_inst <= '1' when
1051 
((instruction_reg_cml_1(15 downto 9)&instruction_reg_cml_1(3 downto 1)="1001010111") or    -- CALL
1052 
 (instruction_reg_cml_1(15 downto 9)&instruction_reg_cml_1(3 downto 1)="1001010110")) or   -- JMP
1053 
 (instruction_reg_cml_1(15 downto 9)&instruction_reg_cml_1(3 downto 0) = "10010000000") or -- LDS
1054 
 (instruction_reg_cml_1(15 downto 9)&instruction_reg_cml_1(3 downto 0) = "10010010000")    -- STS
1055 
   else '0';  -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE
1056 
 
1057 
 
1058 
 
1059 
-- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
1060 
dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0);
1061 
dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0);
1062 
-- SynEDA CoreMultiplier
1063 
-- assignment(s): dex_adr12mem_s
1064 
-- replace(s): instruction_reg
1065 
 
1066 
dex_adr12mem_s <= instruction_reg_cml_2(11 downto 0);
1067 
-- SynEDA CoreMultiplier
1068 
-- assignment(s): dex_adr6port
1069 
-- replace(s): instruction_reg
1070 
 
1071 
dex_adr6port <= instruction_reg_cml_1(10 downto 9) & instruction_reg_cml_1(3 downto 0);
1072 
-- SynEDA CoreMultiplier
1073 
-- assignment(s): dex_adr5port
1074 
-- replace(s): instruction_reg
1075 
 
1076 
dex_adr5port <= instruction_reg_cml_1(7 downto 3);
1077 
-- SynEDA CoreMultiplier
1078 
-- assignment(s): dex_adr_disp
1079 
-- replace(s): instruction_reg
1080 
 
1081 
dex_adr_disp <= instruction_reg_cml_2(13) & instruction_reg_cml_2(11 downto 10) & instruction_reg_cml_2(2 downto 0);
1082 
-- SynEDA CoreMultiplier
1083 
-- assignment(s): dex_condition
1084 
-- replace(s): instruction_reg
1085 
 
1086 
dex_condition <= instruction_reg_cml_1(2 downto 0);
1087 
-- SynEDA CoreMultiplier
1088 
-- assignment(s): dex_bitnum_sreg
1089 
-- replace(s): instruction_reg
1090 
 
1091 
dex_bitop_bitnum <= instruction_reg(2 downto 0);      -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTION
1092 
dex_bitnum_sreg <= instruction_reg_cml_1(6 downto 4);
1093 
dex_adrreg_r  <=  instruction_reg(9) & instruction_reg(3 downto 0);
1094 
dex_adrreg_d  <= instruction_reg(8 downto 4);
1095 
-- SynEDA CoreMultiplier
1096 
-- assignment(s): dex_brxx_offset
1097 
-- replace(s): instruction_reg
1098 
 
1099 
dex_brxx_offset <= instruction_reg_cml_2(9 downto 3);       -- OFFSET FOR BRBC/BRBS
1100 
dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
1101 
--dex_adrindreg <= instruction_reg(3 downto 2);
1102 
 
1103 
-- SynEDA CoreMultiplier
1104 
-- assignment(s): dex_adrreg_d_latched
1105 
-- replace(s): dex_adrreg_d, dex_adrreg_d_latched, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1106 
 
1107 
-- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONS
1108 
latcht_rd_adr:process(cp2,ireset)
1109 
begin
1110 
if ireset ='0' then
1111 
dex_adrreg_d_latched <= (others => '0');
1112 
elsif (cp2='1' and cp2'event) then dex_adrreg_d_latched <= dex_adrreg_d_latched_cml_2;
1113 
 if (cp2en='1') then                                                      -- Clock enable
1114 
  if ((idc_ld_x_cml_2 or idc_ld_y_cml_2 or idc_ldd_y_cml_2 or idc_ld_z_cml_2 or idc_ldd_z_cml_2) or idc_sts_cml_2 or
1115 
          (idc_st_x_cml_2  or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2)or idc_lds_cml_2 or
1116 
           idc_pop_cml_2)='1' then
1117 
   dex_adrreg_d_latched <= dex_adrreg_d_cml_2;
1118 
  end if;
1119 
 end if;
1120 
end if;
1121 
end process;
1122 
-- +++++++++++++++++++++++++++++++++++++++++++++++++
1123 
 
1124 
 
1125 
-- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW  ADDRESS CONTROL LOGIC
1126 
adiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0';
1127 
 
1128 
-- SynEDA CoreMultiplier
1129 
-- assignment(s): adiw_sbiw_encoder_mux_out
1130 
-- replace(s): adiw_sbiw_encoder_out, adiw_sbiw_encoder_mux_out
1131 
 
1132 
adiw_sbiw_high_reg_adr:process(cp2,ireset)
1133 
begin
1134 
if ireset ='0' then
1135 
adiw_sbiw_encoder_mux_out <= (others=>'0');
1136 
elsif(cp2='1' and cp2'event) then adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_mux_out_cml_2;
1137 
 if (cp2en='1') then                                                      -- Clock enable
1138 
  adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out_cml_2 +1;
1139 
 end if;
1140 
end if;
1141 
end process;
1142 
 
1143 
-- ##########################
1144 
 
1145 
-- NOP INSERTION
1146 
 
1147 
--instruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0');
1148 
instruction_code_reg <= (others => '0') when (nop_insert_st='1') else -- NOP
1149 
                        instruction_reg;                                                                                                -- Instruction
1150 
 
1151 
 
1152 
nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or
1153 
              brxx_st or ld_st or st_st or ncall_st0 or nirq_st0 or nret_st0 or nreti_st0 or nlpm_st0 or njmp_st0 or
1154 
              nrcall_st0 or nicall_st0 or sts_st or lds_st or nskip_inst_st0;
1155 
 
1156 
 
1157 
-- INSTRUCTION DECODER (CONNECTED AFTER NOP INSERTION LOGIC)
1158 
 
1159 
-- SynEDA CoreMultiplier
1160 
-- assignment(s): idc_add
1161 
-- replace(s): instruction_code_reg
1162 
 
1163 
idc_adc  <= '1' when instruction_code_reg(15 downto 10) = "000111" else '0'; -- 000111XXXXXXXXXX
1164 
idc_add  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "000011" else '0'; -- 000011XXXXXXXXXX
1165 
 
1166 
idc_adiw <= '1' when instruction_code_reg(15 downto 8) = "10010110" else '0'; -- 10010110XXXXXXXX
1167 
 
1168 
-- SynEDA CoreMultiplier
1169 
-- assignment(s): idc_and
1170 
-- replace(s): instruction_code_reg
1171 
 
1172 
idc_and  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001000" else '0'; -- 001000XXXXXXXXXX
1173 
idc_andi <= '1' when instruction_code_reg(15 downto 12) = "0111" else '0'; -- 0111XXXXXXXXXXXX
1174 
 
1175 
-- SynEDA CoreMultiplier
1176 
-- assignment(s): idc_asr
1177 
-- replace(s): instruction_code_reg
1178 
 
1179 
idc_asr  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100101" else '0'; -- 1001010XXXXX0101
1180 
 
1181 
-- SynEDA CoreMultiplier
1182 
-- assignment(s): idc_bclr
1183 
-- replace(s): instruction_code_reg
1184 
 
1185 
idc_bclr <= '1' when instruction_code_reg_cml_1(15 downto 7)&instruction_code_reg_cml_1(3 downto 0) = "1001010011000" else '0'; -- 100101001XXX1000
1186 
 
1187 
-- SynEDA CoreMultiplier
1188 
-- assignment(s): idc_bld
1189 
-- replace(s): instruction_code_reg
1190 
 
1191 
idc_bld  <= '1' when instruction_code_reg_cml_2(15 downto 9)&instruction_code_reg_cml_2(3) = "11111000" else '0'; -- 1111100XXXXX0XXX
1192 
 
1193 
-- SynEDA CoreMultiplier
1194 
-- assignment(s): idc_brbs
1195 
-- replace(s): instruction_code_reg
1196 
 
1197 
-- SynEDA CoreMultiplier
1198 
-- assignment(s): idc_brbc
1199 
-- replace(s): instruction_code_reg
1200 
 
1201 
idc_brbc <= '1' when instruction_code_reg_cml_1(15 downto 10) = "111101" else '0'; -- 111101XXXXXXXXXX
1202 
idc_brbs <= '1' when instruction_code_reg_cml_1(15 downto 10) = "111100" else '0'; -- 111100XXXXXXXXXX
1203 
 
1204 
-- SynEDA CoreMultiplier
1205 
-- assignment(s): idc_bset
1206 
-- replace(s): instruction_code_reg
1207 
 
1208 
idc_bset <= '1' when instruction_code_reg_cml_1(15 downto 7)&instruction_code_reg_cml_1(3 downto 0) = "1001010001000" else '0'; -- 100101000XXX1000
1209 
 
1210 
-- SynEDA CoreMultiplier
1211 
-- assignment(s): idc_bst
1212 
-- replace(s): instruction_code_reg
1213 
 
1214 
idc_bst  <= '1' when instruction_code_reg_cml_2(15 downto 9) = "1111101" else '0'; -- 1111101XXXXXXXXX
1215 
 
1216 
-- SynEDA CoreMultiplier
1217 
-- assignment(s): idc_call
1218 
-- replace(s): instruction_code_reg
1219 
 
1220 
idc_call <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 1) = "1001010111" else '0'; -- 1001010XXXXX111X
1221 
 
1222 
idc_cbi  <= '1' when instruction_code_reg(15 downto 8) = "10011000" else '0'; -- 10011000XXXXXXXX
1223 
 
1224 
-- SynEDA CoreMultiplier
1225 
-- assignment(s): idc_com
1226 
-- replace(s): instruction_code_reg
1227 
 
1228 
idc_com  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100000" else '0'; -- 1001010XXXXX0000
1229 
 
1230 
idc_cp   <= '1' when instruction_code_reg(15 downto 10) = "000101" else '0'; -- 000101XXXXXXXXXX
1231 
 
1232 
idc_cpc  <= '1' when instruction_code_reg(15 downto 10) = "000001" else '0'; -- 000001XXXXXXXXXX
1233 
 
1234 
idc_cpi  <= '1' when instruction_code_reg(15 downto 12) = "0011" else '0'; -- 0011XXXXXXXXXXXX
1235 
 
1236 
idc_cpse <= '1' when instruction_code_reg(15 downto 10) = "000100" else '0'; -- 000100XXXXXXXXXX
1237 
 
1238 
-- SynEDA CoreMultiplier
1239 
-- assignment(s): idc_dec
1240 
-- replace(s): instruction_code_reg
1241 
 
1242 
idc_dec  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010101010" else '0'; -- 1001010XXXXX1010
1243 
 
1244 
-- SynEDA CoreMultiplier
1245 
-- assignment(s): idc_elpm
1246 
-- replace(s): instruction_code_reg
1247 
 
1248 
idc_elpm <= '1' when instruction_code_reg_cml_2 = "1001010111011000" else '0'; -- 1001010111011000
1249 
 
1250 
-- SynEDA CoreMultiplier
1251 
-- assignment(s): idc_eor
1252 
-- replace(s): instruction_code_reg
1253 
 
1254 
idc_eor  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001001" else '0'; -- 001001XXXXXXXXXX
1255 
 
1256 
idc_icall<= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101011001" else '0'; -- 10010101XXXX1001
1257 
 
1258 
-- SynEDA CoreMultiplier
1259 
-- assignment(s): idc_ijmp
1260 
-- replace(s): instruction_code_reg
1261 
 
1262 
idc_ijmp <= '1' when instruction_code_reg_cml_1(15 downto 8)&instruction_code_reg_cml_1(3 downto 0) = "100101001001" else '0'; -- 10010100XXXX1001
1263 
 
1264 
idc_in   <= '1' when instruction_code_reg(15 downto 11) = "10110" else '0'; -- 10110XXXXXXXXXXX
1265 
 
1266 
-- SynEDA CoreMultiplier
1267 
-- assignment(s): idc_inc
1268 
-- replace(s): instruction_code_reg
1269 
 
1270 
idc_inc  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100011" else '0'; -- 1001010XXXXX0011
1271 
 
1272 
-- SynEDA CoreMultiplier
1273 
-- assignment(s): idc_jmp
1274 
-- replace(s): instruction_code_reg
1275 
 
1276 
idc_jmp  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 1) = "1001010110" else '0'; -- 1001010XXXXX110X
1277 
 
1278 
 
1279 
-- SynEDA CoreMultiplier
1280 
-- assignment(s): idc_ld_x
1281 
-- replace(s): instruction_code_reg
1282 
 
1283 
-- LD,LDD
1284 
idc_ld_x <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010001100" or
1285 
                     instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010001101"      or
1286 
                                         instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010001110" else '0';
1287 
 
1288 
-- SynEDA CoreMultiplier
1289 
-- assignment(s): idc_ld_y
1290 
-- replace(s): instruction_code_reg
1291 
 
1292 
idc_ld_y <= '1' when (instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0)="10010001001" or
1293 
                                          instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0)="10010001010") else '0';
1294 
 
1295 
-- SynEDA CoreMultiplier
1296 
-- assignment(s): idc_ldd_y
1297 
-- replace(s): instruction_code_reg
1298 
 
1299 
idc_ldd_y<= '1' when instruction_code_reg_cml_1(15 downto 14)&instruction_code_reg_cml_1(12)&instruction_code_reg_cml_1(9)&instruction_code_reg_cml_1(3) = "10001" else '0'; -- 10X0XX0XXXXX1XXX
1300 
 
1301 
-- SynEDA CoreMultiplier
1302 
-- assignment(s): idc_ld_z
1303 
-- replace(s): instruction_code_reg
1304 
 
1305 
idc_ld_z <= '1' when (instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0)="10010000001" or
1306 
                                          instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0)="10010000010") else '0';
1307 
 
1308 
-- SynEDA CoreMultiplier
1309 
-- assignment(s): idc_ldd_z
1310 
-- replace(s): instruction_code_reg
1311 
 
1312 
idc_ldd_z<= '1' when instruction_code_reg_cml_1(15 downto 14)&instruction_code_reg_cml_1(12)&instruction_code_reg_cml_1(9)&instruction_code_reg_cml_1(3) = "10000" else '0'; -- 10X0XX0XXXXX0XXX
1313 
-- ######
1314 
 
1315 
 
1316 
idc_ldi <= '1' when instruction_code_reg(15 downto 12) = "1110" else '0'; -- 1110XXXXXXXXXXXX
1317 
 
1318 
-- SynEDA CoreMultiplier
1319 
-- assignment(s): idc_lds
1320 
-- replace(s): instruction_code_reg
1321 
 
1322 
idc_lds <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010000000" else '0'; -- 1001000XXXXX0000
1323 
 
1324 
-- SynEDA CoreMultiplier
1325 
-- assignment(s): idc_lpm
1326 
-- replace(s): instruction_code_reg
1327 
 
1328 
idc_lpm <= '1' when instruction_code_reg_cml_1 = "1001010111001000" else '0'; -- 1001010111001000
1329 
 
1330 
-- SynEDA CoreMultiplier
1331 
-- assignment(s): idc_lsr
1332 
-- replace(s): instruction_code_reg
1333 
 
1334 
idc_lsr <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100110" else '0'; -- 1001010XXXXX0110
1335 
 
1336 
-- SynEDA CoreMultiplier
1337 
-- assignment(s): idc_mov
1338 
-- replace(s): instruction_code_reg
1339 
 
1340 
idc_mov <= '1' when instruction_code_reg_cml_2(15 downto 10) = "001011" else '0'; -- 001011XXXXXXXXXX
1341 
 
1342 
idc_mul <= '1' when instruction_code_reg(15 downto 10) = "100111" else '0'; -- 100111XXXXXXXXXX
1343 
 
1344 
-- SynEDA CoreMultiplier
1345 
-- assignment(s): idc_neg
1346 
-- replace(s): instruction_code_reg
1347 
 
1348 
idc_neg <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100001" else '0'; -- 1001010XXXXX0001
1349 
 
1350 
idc_nop <= '1' when instruction_code_reg = "0000000000000000" else '0'; -- 0000000000000000
1351 
 
1352 
-- SynEDA CoreMultiplier
1353 
-- assignment(s): idc_or
1354 
-- replace(s): instruction_code_reg
1355 
 
1356 
idc_or  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001010" else '0'; -- 001010XXXXXXXXXX
1357 
 
1358 
idc_ori <= '1' when instruction_code_reg(15 downto 12) = "0110" else '0'; -- 0110XXXXXXXXXXXX
1359 
 
1360 
idc_out <= '1' when instruction_code_reg(15 downto 11) = "10111" else '0'; -- 10111XXXXXXXXXXX
1361 
 
1362 
-- SynEDA CoreMultiplier
1363 
-- assignment(s): idc_pop
1364 
-- replace(s): instruction_code_reg
1365 
 
1366 
idc_pop <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010001111" else '0'; -- 1001000XXXXX1111
1367 
 
1368 
idc_push<= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011111" else '0'; -- 1001001XXXXX1111
1369 
 
1370 
idc_rcall<= '1' when instruction_code_reg(15 downto 12) = "1101" else '0'; -- 1101XXXXXXXXXXXX
1371 
 
1372 
-- SynEDA CoreMultiplier
1373 
-- assignment(s): idc_ret
1374 
-- replace(s): instruction_code_reg
1375 
 
1376 
idc_ret  <= '1' when instruction_code_reg_cml_1(15 downto 7)&instruction_code_reg_cml_1(4 downto 0) = "10010101001000" else '0'; -- 100101010XX01000
1377 
 
1378 
-- SynEDA CoreMultiplier
1379 
-- assignment(s): idc_reti
1380 
-- replace(s): instruction_code_reg
1381 
 
1382 
idc_reti <= '1' when instruction_code_reg_cml_1(15 downto 7)&instruction_code_reg_cml_1(4 downto 0) = "10010101011000" else '0'; -- 100101010XX11000
1383 
 
1384 
-- SynEDA CoreMultiplier
1385 
-- assignment(s): idc_rjmp
1386 
-- replace(s): instruction_code_reg
1387 
 
1388 
idc_rjmp <= '1' when instruction_code_reg_cml_1(15 downto 12) = "1100" else '0'; -- 1100XXXXXXXXXXXX
1389 
 
1390 
idc_ror  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100111" else '0'; -- 1001010XXXXX0111
1391 
 
1392 
idc_sbc  <= '1' when instruction_code_reg(15 downto 10) = "000010" else '0'; -- 000010XXXXXXXXXX
1393 
 
1394 
idc_sbci <= '1' when instruction_code_reg(15 downto 12) = "0100" else '0'; -- 0100XXXXXXXXXXXX
1395 
 
1396 
idc_sbi  <= '1' when instruction_code_reg(15 downto 8) = "10011010" else '0'; -- 10011010XXXXXXXX
1397 
 
1398 
idc_sbic <= '1' when instruction_code_reg(15 downto 8) = "10011001" else '0'; -- 10011001XXXXXXXX
1399 
 
1400 
idc_sbis <= '1' when instruction_code_reg(15 downto 8) = "10011011" else '0'; -- 10011011XXXXXXXX
1401 
 
1402 
idc_sbiw <= '1' when instruction_code_reg(15 downto 8) = "10010111" else '0'; -- 10010111XXXXXXXX
1403 
 
1404 
-- SynEDA CoreMultiplier
1405 
-- assignment(s): idc_sbrc
1406 
-- replace(s): instruction_code_reg
1407 
 
1408 
idc_sbrc <= '1' when instruction_code_reg_cml_1(15 downto 9) = "1111110" else '0'; -- 1111110XXXXXXXXX
1409 
 
1410 
-- SynEDA CoreMultiplier
1411 
-- assignment(s): idc_sbrs
1412 
-- replace(s): instruction_code_reg
1413 
 
1414 
idc_sbrs <= '1' when instruction_code_reg_cml_1(15 downto 9) = "1111111" else '0'; -- 1111111XXXXXXXXX
1415 
 
1416 
-- SynEDA CoreMultiplier
1417 
-- assignment(s): idc_sleep
1418 
-- replace(s): instruction_code_reg
1419 
 
1420 
idc_sleep<= '1' when instruction_code_reg_cml_2(15 downto 5)&instruction_code_reg_cml_2(3 downto 0) = "100101011001000" else '0'; -- 10010101100X1000
1421 
 
1422 
 
1423 
-- ST,STD
1424 
idc_st_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011100" or
1425 
                     instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011101" or
1426 
                     instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011110" else '0';
1427 
 
1428 
idc_st_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011001" or
1429 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011010") else '0';
1430 
 
1431 
idc_std_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10011" else '0'; -- 10X0XX1XXXXX1XXX
1432 
 
1433 
idc_st_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010001" or
1434 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010010") else '0';
1435 
 
1436 
idc_std_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10010" else '0'; -- 10X0XX1XXXXX0XXX
1437 
-- ######
1438 
 
1439 
idc_sts  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010010000" else '0'; -- 1001001XXXXX0000
1440 
 
1441 
idc_sub  <= '1' when instruction_code_reg(15 downto 10) = "000110" else '0'; -- 000110XXXXXXXXXX
1442 
 
1443 
idc_subi <= '1' when instruction_code_reg(15 downto 12) = "0101" else '0'; -- 0101XXXXXXXXXXXX
1444 
 
1445 
-- SynEDA CoreMultiplier
1446 
-- assignment(s): idc_swap
1447 
-- replace(s): instruction_code_reg
1448 
 
1449 
idc_swap <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100010" else '0'; -- 1001010XXXXX0010
1450 
 
1451 
-- SynEDA CoreMultiplier
1452 
-- assignment(s): idc_wdr
1453 
-- replace(s): instruction_code_reg
1454 
 
1455 
idc_wdr  <= '1' when instruction_code_reg_cml_2(15 downto 5)&instruction_code_reg_cml_2(3 downto 0) = "100101011011000" else '0'; -- 10010101101X1000
1456 
 
1457 
-- SynEDA CoreMultiplier
1458 
-- assignment(s): idc_psinc
1459 
-- replace(s): instruction_code_reg, idc_ld_x, idc_ld_y, idc_ld_z, idc_st_x, idc_st_y, idc_st_z
1460 
 
1461 
-- ADDITIONAL SIGNALS
1462 
idc_psinc <= '1' when (instruction_code_reg_cml_2(1 downto 0) = "01" and
1463 
 (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_st_z_cml_2 or idc_ld_x_cml_2 or idc_ld_y_cml_2 or idc_ld_z_cml_2)='1') else '0';  -- POST INCREMENT FOR LD/ST INSTRUCTIONS
1464 
 
1465 
-- SynEDA CoreMultiplier
1466 
-- assignment(s): idc_prdec
1467 
-- replace(s): instruction_code_reg, idc_st_x, idc_st_y, idc_st_z
1468 
 
1469 
idc_prdec <= '1' when (instruction_code_reg_cml_1(1 downto 0)    = "10" and
1470 
 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1 or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0';  -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
1471 
 
1472 
 
1473 
-- ##########################################################################################################
1474 
 
1475 
-- SynEDA CoreMultiplier
1476 
-- assignment(s): ramadr_reg_en
1477 
-- replace(s): cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1478 
 
1479 
-- WRITE ENABLE SIGNALS FOR ramadr_reg
1480 
ramadr_reg_en <= idc_ld_x_cml_2 or idc_ld_y_cml_2 or idc_ldd_y_cml_2 or idc_ld_z_cml_2 or idc_ldd_z_cml_2 or idc_lds_cml_2 or    -- LD/LDD/LDS(two cycle execution)
1481 
                 idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2 or idc_sts_cml_2 or    -- ST/STS/STS(two cycle execution)
1482 
                                 idc_push_cml_2 or idc_pop_cml_2 or
1483 
                                 idc_rcall_cml_2 or (rcall_st1_cml_2 and not cpuwait_cml_2) or idc_icall_cml_2 or (icall_st1_cml_2 and not cpuwait_cml_2) or -- RCALL/ICALL
1484 
                                 call_st1_cml_2 or  (call_st2_cml_2 and not cpuwait_cml_2) or irq_st1_cml_2 or (irq_st2_cml_2 and not cpuwait_cml_2) or      -- CALL/IRQ
1485 
                                 idc_ret_cml_2 or (ret_st1_cml_2 and not cpuwait_cml_2 ) or idc_reti_cml_2 or (reti_st1_cml_2 and not cpuwait_cml_2);            -- RET/RETI  -- ??
1486 
 
1487 
 
1488 
-- SynEDA CoreMultiplier
1489 
-- assignment(s): ramadr_reg_in
1490 
-- replace(s): inst, cpuwait, spl_out, sph_out, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_ld_x, idc_ld_y, idc_ld_z, idc_lds, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_st_x, idc_st_y, idc_st_z, idc_sts
1491 
 
1492 
-- RAMADR MUX
1493 
ramadr_reg_in <= sph_out_cml_2&spl_out_cml_2 when
1494 
  (idc_rcall_cml_2 or (rcall_st1_cml_2 and not cpuwait_cml_2)or idc_icall_cml_2 or (icall_st1_cml_2 and not cpuwait_cml_2)or  -- RCALL/ICALL
1495 
   call_st1_cml_2  or (call_st2_cml_2 and not cpuwait_cml_2) or irq_st1_cml_2   or (irq_st2_cml_2 and not cpuwait_cml_2)  or  -- CALL/IRQ
1496 
   idc_push_cml_2 )='1' else                                                                      -- PUSH
1497 
   (sph_out_cml_2&spl_out_cml_2)+1 when (idc_ret_cml_2 or (ret_st1_cml_2 and not cpuwait_cml_2)  or idc_reti_cml_2  or (reti_st1_cml_2 and not cpuwait_cml_2) or idc_pop_cml_2)='1' else  -- RET/RETI/POP
1498 
   inst_cml_2 when (idc_lds_cml_2 or idc_sts_cml_2) ='1' else     -- LDS/STS (two cycle execution)
1499 
   reg_h_out when (idc_ld_x_cml_2 or idc_ld_y_cml_2 or idc_ld_z_cml_2 or idc_st_x_cml_2 or idc_st_y_cml_2 or idc_st_z_cml_2)='1' else  -- LD/ST
1500 
   (reg_h_out + ("000000000"&dex_adr_disp));                                                       -- LDD/STD
1501 
 
1502 
 
1503 
-- SynEDA CoreMultiplier
1504 
-- assignment(s): ramadr_int
1505 
-- replace(s): ramadr_int
1506 
 
1507 
-- ADDRESS REGISTER
1508 
ramadr_reg:process(cp2,ireset)
1509 
begin
1510 
if ireset='0' then
1511 
ramadr_int <= (others => '0');
1512 
elsif(cp2='1' and cp2'event) then ramadr_int <= ramadr_int_cml_2;
1513 
 if (cp2en='1') then                                                      -- Clock enable
1514 
  if (ramadr_reg_en='1') then
1515 
   ramadr_int <= ramadr_reg_in;
1516 
  end if;
1517 
 end if;
1518 
end if;
1519 
end process;
1520 
 
1521 
ramadr <= ramadr_int;
1522 
 
1523 
-- SynEDA CoreMultiplier
1524 
-- assignment(s): reg_file_adr_space
1525 
-- replace(s): reg_file_adr_space
1526 
 
1527 
-- GENERAL PURPOSE REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
1528 
gp_reg_adr:process(cp2,ireset)
1529 
begin
1530 
if ireset='0' then
1531 
reg_file_adr_space <='0';
1532 
elsif(cp2='1' and cp2'event) then reg_file_adr_space <= reg_file_adr_space_cml_2;
1533 
 if (cp2en='1') then                                                      -- Clock enable
1534 
  if (ramadr_reg_en='1') then
1535 
   if (ramadr_reg_in(15 downto 5)=const_ram_to_reg) then
1536 
    reg_file_adr_space <= '1';                             -- ADRESS RANGE 0x0000-0x001F -> REGISTERS (R0-R31)
1537 
   else
1538 
    reg_file_adr_space <= '0';
1539 
   end if;
1540 
  end if;
1541 
 end if;
1542 
end if;
1543 
end process;
1544 
 
1545 
-- SynEDA CoreMultiplier
1546 
-- assignment(s): io_file_adr_space
1547 
-- replace(s): io_file_adr_space
1548 
 
1549 
-- I/O REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
1550 
io_reg_adr:process(cp2,ireset)
1551 
begin
1552 
if ireset='0' then io_file_adr_space<='0';
1553 
elsif(cp2='1' and cp2'event) then io_file_adr_space <= io_file_adr_space_cml_2;
1554 
 if (cp2en='1') then                                                      -- Clock enable
1555 
  if (ramadr_reg_en='1') then
1556 
   if (ramadr_reg_in(15 downto 5)=const_ram_to_io_a or ramadr_reg_in(15 downto 5)=const_ram_to_io_b) then
1557 
    io_file_adr_space <= '1';                             -- ADRESS RANGE 0x0020-0x005F -> I/O PORTS (0x00-0x3F)
1558 
   else
1559 
    io_file_adr_space <= '0';
1560 
   end if;
1561 
  end if;
1562 
 end if;
1563 
end if;
1564 
end process;
1565 
 
1566 
 
1567 
 
1568 
-- ##########################################################################################################
1569 
 
1570 
 
1571 
-- REGRE/REGWE LOGIC (5 BIT ADDSRESS BUS (INTERNAL ONLY) 32 LOCATIONS (R0-R31))
1572 
 
1573 
-- SynEDA CoreMultiplier
1574 
-- assignment(s): alu_reg_wr
1575 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_and, idc_andi, idc_asr, idc_com, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi, idc_swap
1576 
 
1577 
-- WRITE ENABLE FOR Rd REGISTERS
1578 
alu_reg_wr <= idc_adc_cml_2 or idc_add_cml_2 or idc_adiw_cml_2 or adiw_st_cml_2 or idc_sub_cml_2 or idc_subi_cml_2 or idc_sbc_cml_2 or idc_sbci_cml_2 or
1579 
              idc_sbiw_cml_2 or  sbiw_st_cml_2 or idc_and_cml_2 or idc_andi_cml_2 or idc_or_cml_2 or idc_ori_cml_2 or idc_eor_cml_2 or idc_com_cml_2 or
1580 
                          idc_neg_cml_2 or idc_inc_cml_2 or idc_dec_cml_2 or idc_lsr_cml_2 or idc_ror_cml_2 or idc_asr_cml_2 or idc_swap_cml_2;
1581 
 
1582 
 
1583 
-- SynEDA CoreMultiplier
1584 
-- assignment(s): reg_rd_wr
1585 
-- replace(s): reg_file_adr_space, lpm_st2, sts_st, lds_st, st_st, ld_st, pop_st, idc_in, idc_ldi
1586 
 
1587 
reg_rd_wr_cml_out <= idc_in_cml_2 or alu_reg_wr or idc_bld or             -- ALU INSTRUCTIONS + IN/BLD INSRTRUCTION
1588 
 (pop_st_cml_2 or ld_st_cml_2 or lds_st_cml_2)or                                            -- POP/LD/LDD/LDS INSTRUCTIONS
1589 
 ((st_st_cml_2 or sts_st_cml_2) and reg_file_adr_space_cml_2)or              -- ST/STD/STS INSTRUCTION
1590 
  lpm_st2_cml_2 or idc_ldi_cml_2 or idc_mov;                            -- LPM/LDI/MOV INSTRUCTION
1591 
 
1592 
 
1593 
  reg_rd_adr <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else
1594 
                           "00000" when lpm_st2='1' else
1595 
               adiw_sbiw_encoder_out     when (idc_adiw or idc_sbiw)='1' else
1596 
               adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else
1597 
                           dex_adrreg_d_latched      when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else
1598 
               ramadr_int(4 downto 0)    when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
1599 
                           dex_adrreg_d;
1600 
 
1601 
  reg_rd_adr_int <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else
1602 
                           "00000" when lpm_st2='1' else
1603 
               adiw_sbiw_encoder_out     when (idc_adiw or idc_sbiw)='1' else
1604 
               adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else
1605 
                           dex_adrreg_d_latched      when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else
1606 
               ramadr_int(4 downto 0)    when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
1607 
                           dex_adrreg_d;
1608 
 
1609 
reg_rr_adr <= ramadr_int(4 downto 0) when ((ld_st or lds_st) and reg_file_adr_space)='1'else --!!??
1610 
                  dex_adrreg_d_latched   when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
1611 
                  dex_adrreg_r;
1612 
 
1613 
-- SynEDA CoreMultiplier
1614 
-- assignment(s): reg_rd_in
1615 
-- replace(s): dbusin, reg_rr_out, reg_file_adr_space, lpm_st2, sts_st, lds_st, st_st, ld_st, pop_st, instruction_reg, dex_dat8_immed, gp_reg_tmp, idc_in, idc_ldi
1616 
 
1617 
-- MULTIPLEXER FOR REGISTER FILE Rd INPUT
1618 
reg_rd_in_cml_out <= dbusin_cml_2 when (idc_in_cml_2 or ((lds_st_cml_2 or ld_st_cml_2)and not reg_file_adr_space_cml_2) or pop_st_cml_2)='1' else -- FROM INPUT DATA BUS
1619 
                         reg_rr_out_cml_2 when ((lds_st_cml_2 or ld_st_cml_2)  and reg_file_adr_space_cml_2)='1' else
1620 
             gp_reg_tmp_cml_2 when ((st_st_cml_2 or sts_st_cml_2)  and reg_file_adr_space_cml_2)='1' else -- ST/STD/STS &  ADDRESS FROM 0 TO 31 (REGISTER FILE)
1621 
                         bld_op_out when (idc_bld='1')else                                     -- FROM BIT PROCESSOR BLD COMMAND
1622 
             reg_rr_out_cml_2 when (idc_mov='1')else                                     -- FOR MOV INSTRUCTION
1623 
                         instruction_reg_cml_2(15 downto 8) when (lpm_st2_cml_2='1' and reg_z_out(0)='1') else -- LPM/ELPM
1624 
                         instruction_reg_cml_2(7 downto 0) when  (lpm_st2_cml_2='1' and reg_z_out(0)='0') else -- LPM/ELPM
1625 
             dex_dat8_immed_cml_2 when idc_ldi_cml_2='1' else
1626 
                         alu_data_out;                                               -- FROM ALU DATA OUT
1627 
 
1628 
-- SynEDA CoreMultiplier
1629 
-- assignment(s): iowe_int
1630 
-- replace(s): io_file_adr_space, sts_st, st_st, sbi_st, cbi_st, idc_out
1631 
 
1632 
-- SynEDA CoreMultiplier
1633 
-- assignment(s): iore_int
1634 
-- replace(s): io_file_adr_space, lds_st, ld_st, idc_cbi, idc_in, idc_sbi, idc_sbic, idc_sbis
1635 
 
1636 
-- IORE/IOWE LOGIC (6 BIT ADDRESS adr[5..0] FOR I/O PORTS(64 LOCATIONS))
1637 
iore_int <= idc_in_cml_1 or idc_sbi_cml_1 or idc_cbi_cml_1 or idc_sbic_cml_1 or idc_sbis_cml_1 or ((ld_st_cml_1 or lds_st_cml_1) and io_file_adr_space_cml_1);   -- IN/SBI/CBI
1638 
iowe_int <= '1' when ((idc_out_cml_1 or sbi_st_cml_1 or cbi_st_cml_1) or
1639 
                     ((st_st_cml_1 or sts_st_cml_1) and io_file_adr_space_cml_1))='1' else '0'; -- OUT/SBI/CBI + !! ST/STS/STD
1640 
 
1641 
 
1642 
-- SynEDA CoreMultiplier
1643 
-- assignment(s): adr_int
1644 
-- replace(s): sbi_st, cbi_st, ramadr_int, cbi_sbi_io_adr_tmp, idc_cbi, idc_in, idc_out, idc_sbi, idc_sbic, idc_sbis
1645 
 
1646 
-- adr[5..0] BUS MULTIPLEXER
1647 
adr_int <= dex_adr6port when (idc_in_cml_1 or idc_out_cml_1) = '1' else                          -- IN/OUT INSTRUCTIONS
1648 
           '0'&dex_adr5port when (idc_cbi_cml_1 or idc_sbi_cml_1 or idc_sbic_cml_1 or idc_sbis_cml_1) ='1'    else  -- CBI/SBI (READ PHASE) + SBIS/SBIC
1649 
                   '0'&cbi_sbi_io_adr_tmp_cml_1 when (cbi_st_cml_1 or sbi_st_cml_1)='1' else     -- CBI/SBI (WRITE PHASE)
1650 
                    ramadr_int_cml_1(6)&ramadr_int_cml_1(4 downto 0);                                                   -- LD/LDS/LDD/ST/STS/STD
1651 
 
1652 
-- ramre LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
1653 
--ramre_int <= not(reg_file_adr_space or io_file_adr_space) and
1654 
--            (ld_st or lds_st2 or pop_st or                    -- LD/LDD/LDS/POP/
1655 
--             ret_st1 or ret_st2 or reti_st1 or reti_st2);     -- RET/RETI
1656 
 
1657 
-- SynEDA CoreMultiplier
1658 
-- assignment(s): ramre_int
1659 
-- replace(s): cpuwait, ret_st2, reti_st2, lds_st, ld_st, pop_st, ramre_int, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_ret, idc_reti
1660 
 
1661 
DataMemoryRead:process(cp2,ireset)
1662 
begin
1663 
if ireset='0' then -- Reset
1664 
 ramre_int <= '0';
1665 
elsif (cp2='1' and cp2'event) then ramre_int <= ramre_int_cml_2; -- Clock
1666 
 if (cp2en='1') then                                                      -- Clock enable
1667 
  case ramre_int_cml_2 is
1668 
   when '0' =>
1669 
    if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and
1670 
           ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and
1671 
       ramadr_reg_in(15 downto 5)/=const_ram_to_reg  and
1672 
      (idc_ld_x_cml_2 or idc_ld_y_cml_2 or idc_ldd_y_cml_2 or idc_ld_z_cml_2 or idc_ldd_z_cml_2 or  -- LD/LDD instruction
1673 
           idc_lds_cml_2 or                                                     -- LDS instruction(two cycle execution)
1674 
           idc_pop_cml_2 or                                                     -- POP instruction
1675 
       idc_ret_cml_2 or                                                         -- RET instruction
1676 
           idc_reti_cml_2)='1')                                                                                                     -- RETI instruction
1677 
           then ramre_int <='1';
1678 
    end if;
1679 
   when '1' =>
1680 
    if ((ld_st_cml_2 or lds_st_cml_2 or pop_st_cml_2 or ret_st2_cml_2 or reti_st2_cml_2)and not cpuwait_cml_2)='1' then
1681 
     ramre_int <='0';
1682 
    end if;
1683 
   when others  =>      null;
1684 
  end case;
1685 
 end if;
1686 
end if;
1687 
end process;
1688 
 
1689 
-- ramwe LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
1690 
--ramwe_int <= not(reg_file_adr_space or io_file_adr_space) and
1691 
--            (st_st or sts_st2 or push_st or rcall_st1 or rcall_st2 or -- ST/STD/STS/PUSH/RCALL
1692 
--                                                      icall_st1 or icall_st2 or -- ICALL
1693 
--                                                      call_st2 or call_st3 or   -- CALL
1694 
--                                                                                      irq_st2 or irq_st3);      -- INTERRUPT
1695 
 
1696 
-- SynEDA CoreMultiplier
1697 
-- assignment(s): ramwe_int
1698 
-- replace(s): cpuwait, irq_st1, irq_st3, call_st1, call_st3, rcall_st2, icall_st2, sts_st, st_st, push_st, ramwe_int, idc_icall, idc_push, idc_rcall, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1699 
 
1700 
DataMemoryWrite:process(cp2,ireset)
1701 
begin
1702 
if ireset='0' then -- Reset
1703 
 ramwe_int <= '0';
1704 
elsif (cp2='1' and cp2'event) then ramwe_int <= ramwe_int_cml_2; -- Clock
1705 
 if (cp2en='1') then                                                      -- Clock enable
1706 
  case ramwe_int_cml_2 is
1707 
   when '0' =>
1708 
    if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and
1709 
           ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and
1710 
       ramadr_reg_in(15 downto 5)/=const_ram_to_reg  and
1711 
      (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2 or  -- ST/STD instruction
1712 
           idc_sts_cml_2 or                                                     -- STS instruction (two cycle execution)
1713 
           idc_push_cml_2 or                                                    -- PUSH instruction
1714 
           idc_rcall_cml_2 or                                                                                                     -- RCALL instruction
1715 
           idc_icall_cml_2 or                                                                                                     -- ICALL instruction
1716 
           call_st1_cml_2 or                                                    -- CALL instruction
1717 
           irq_st1_cml_2)='1')                                                  -- Interrupt
1718 
          then ramwe_int <='1';
1719 
    end if;
1720 
   when '1' =>
1721 
    if ((st_st_cml_2 or sts_st_cml_2 or push_st_cml_2 or rcall_st2_cml_2 or
1722 
             icall_st2_cml_2 or call_st3_cml_2 or irq_st3_cml_2)and not cpuwait_cml_2)='1' then ramwe_int <='0';
1723 
    end if;
1724 
   when others  =>      null;
1725 
  end case;
1726 
end if;
1727 
end if;
1728 
end process;
1729 
 
1730 
-- DBUSOUT MULTIPLEXER
1731 
--dbusout_mux_logic: for i in dbusout_int'range generate
1732 
--dbusout_int(i)<= (reg_rd_out(i) and (idc_push or idc_sts or
1733 
--                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1734 
--                               (gp_reg_tmp(i) and (st_st or sts_st))or                            -- NEW
1735 
--                               (bitpr_io_out(i) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1736 
--                 (program_counter(i)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC                 (program_counter_high_fr(i) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1737 
--                 (pc_for_interrupt(i) and irq_st1) or
1738 
--                               (pc_for_interrupt(8) and irq_st2) or
1739 
--                               (reg_rd_out(i) and  idc_out); -- OUT
1740 
--end generate;
1741 
 
1742 
dbusout_int(0)<= (reg_rd_out(0) and (idc_push_cml_1 or idc_sts_cml_1 or
1743 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1744 
                                 (gp_reg_tmp_cml_1(0) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1745 
                                 (bitpr_io_out_cml_1(0) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1746 
                 (program_counter_cml_1(0)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1747 
                 (program_counter_high_fr_cml_1(0) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1748 
                 (pc_for_interrupt_cml_1(0) and irq_st1_cml_1) or
1749 
                                 (pc_for_interrupt_cml_1(8) and irq_st2_cml_1) or
1750 
                                 (reg_rd_out(0) and  idc_out_cml_1); -- OUT
1751 
 
1752 
dbusout_int(1)<= (reg_rd_out(1) and (idc_push_cml_1 or idc_sts_cml_1 or
1753 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1754 
                                 (gp_reg_tmp_cml_1(1) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1755 
                                 (bitpr_io_out_cml_1(1) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1756 
                 (program_counter_cml_1(1)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1757 
                 (program_counter_high_fr_cml_1(1) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1758 
                 (pc_for_interrupt_cml_1(1) and irq_st1_cml_1) or
1759 
                                 (pc_for_interrupt_cml_1(9) and irq_st2_cml_1) or
1760 
                                 (reg_rd_out(1) and  idc_out_cml_1); -- OUT
1761 
 
1762 
dbusout_int(2)<= (reg_rd_out(2) and (idc_push_cml_1 or idc_sts_cml_1 or
1763 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1764 
                                 (gp_reg_tmp_cml_1(2) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1765 
                                 (bitpr_io_out_cml_1(2) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1766 
                 (program_counter_cml_1(2)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1767 
                 (program_counter_high_fr_cml_1(2) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1768 
                 (pc_for_interrupt_cml_1(2) and irq_st1_cml_1) or
1769 
                                 (pc_for_interrupt_cml_1(10) and irq_st2_cml_1) or
1770 
                                 (reg_rd_out(2) and  idc_out_cml_1); -- OUT
1771 
 
1772 
dbusout_int(3)<= (reg_rd_out(3) and (idc_push_cml_1 or idc_sts_cml_1 or
1773 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1774 
                                 (gp_reg_tmp_cml_1(3) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1775 
                                 (bitpr_io_out_cml_1(3) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1776 
                 (program_counter_cml_1(3)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1777 
                 (program_counter_high_fr_cml_1(3) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1778 
                 (pc_for_interrupt_cml_1(3) and irq_st1_cml_1) or
1779 
                                 (pc_for_interrupt_cml_1(11) and irq_st2_cml_1) or
1780 
                                 (reg_rd_out(3) and  idc_out_cml_1); -- OUT
1781 
 
1782 
dbusout_int(4)<= (reg_rd_out(4) and (idc_push_cml_1 or idc_sts_cml_1 or
1783 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1784 
                                 (gp_reg_tmp_cml_1(4) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1785 
                                 (bitpr_io_out_cml_1(4) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1786 
                 (program_counter_cml_1(4)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1787 
                 (program_counter_high_fr_cml_1(4) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1788 
                 (pc_for_interrupt_cml_1(4) and irq_st1_cml_1) or
1789 
                                 (pc_for_interrupt_cml_1(12) and irq_st2_cml_1) or
1790 
                                 (reg_rd_out(4) and  idc_out_cml_1); -- OUT
1791 
 
1792 
dbusout_int(5)<= (reg_rd_out(5) and (idc_push_cml_1 or idc_sts_cml_1 or
1793 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1794 
                                 (gp_reg_tmp_cml_1(5) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1795 
                                 (bitpr_io_out_cml_1(5) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1796 
                 (program_counter_cml_1(5)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1797 
                 (program_counter_high_fr_cml_1(5) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1798 
                 (pc_for_interrupt_cml_1(5) and irq_st1_cml_1) or
1799 
                                 (pc_for_interrupt_cml_1(13) and irq_st2_cml_1) or
1800 
                                 (reg_rd_out(5) and  idc_out_cml_1); -- OUT
1801 
 
1802 
dbusout_int(6)<= (reg_rd_out(6) and (idc_push_cml_1 or idc_sts_cml_1 or
1803 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1804 
                                 (gp_reg_tmp_cml_1(6) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1805 
                                 (bitpr_io_out_cml_1(6) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1806 
                 (program_counter_cml_1(6)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1807 
                 (program_counter_high_fr_cml_1(6) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1808 
                 (pc_for_interrupt_cml_1(6) and irq_st1_cml_1) or
1809 
                                 (pc_for_interrupt_cml_1(14) and irq_st2_cml_1) or
1810 
                                 (reg_rd_out(6) and  idc_out_cml_1); -- OUT
1811 
 
1812 
-- SynEDA CoreMultiplier
1813 
-- assignment(s): dbusout_int
1814 
-- replace(s): bitpr_io_out, program_counter, program_counter_high_fr, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, sts_st, st_st, sbi_st, cbi_st, pc_for_interrupt, gp_reg_tmp, idc_icall, idc_out, idc_push, idc_rcall, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1815 
 
1816 
dbusout_int(7)<= (reg_rd_out(7) and (idc_push_cml_1 or idc_sts_cml_1 or
1817 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1818 
                                 (gp_reg_tmp_cml_1(7) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1819 
                                 (bitpr_io_out_cml_1(7) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1820 
                 (program_counter_cml_1(7)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1821 
                 (program_counter_high_fr_cml_1(7) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1822 
                 (pc_for_interrupt_cml_1(7) and irq_st1_cml_1) or
1823 
                                 (pc_for_interrupt_cml_1(15) and irq_st2_cml_1) or
1824 
                                 (reg_rd_out(7) and  idc_out_cml_1); -- OUT
1825 
 
1826 
-- SynEDA CoreMultiplier
1827 
-- assignment(s): dbusout_int_route
1828 
-- replace(s): dbusout_int
1829 
 
1830 
dbusout_int_route_cml_out <= dbusout_int_cml_2;
1831 
 
1832 
dbusout(0)<= (reg_rd_out_int(0) and (idc_push or idc_sts or
1833 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1834 
                                 (gp_reg_tmp(0) and (st_st or sts_st))or                            -- NEW
1835 
                                 (bitpr_io_out(0) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1836 
                 (program_counter(0)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1837 
                 (program_counter_high_fr(0) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1838 
                 (pc_for_interrupt(0) and irq_st1) or
1839 
                                 (pc_for_interrupt(8) and irq_st2) or
1840 
                                 (reg_rd_out_int(0) and  idc_out); -- OUT
1841 
 
1842 
dbusout(1)<= (reg_rd_out_int(1) and (idc_push or idc_sts or
1843 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1844 
                                 (gp_reg_tmp(1) and (st_st or sts_st))or                            -- NEW
1845 
                                 (bitpr_io_out(1) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1846 
                 (program_counter(1)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1847 
                 (program_counter_high_fr(1) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1848 
                 (pc_for_interrupt(1) and irq_st1) or
1849 
                                 (pc_for_interrupt(9) and irq_st2) or
1850 
                                 (reg_rd_out_int(1) and  idc_out); -- OUT
1851 
 
1852 
dbusout(2)<= (reg_rd_out_int(2) and (idc_push or idc_sts or
1853 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1854 
                                 (gp_reg_tmp(2) and (st_st or sts_st))or                            -- NEW
1855 
                                 (bitpr_io_out(2) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1856 
                 (program_counter(2)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1857 
                 (program_counter_high_fr(2) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1858 
                 (pc_for_interrupt(2) and irq_st1) or
1859 
                                 (pc_for_interrupt(10) and irq_st2) or
1860 
                                 (reg_rd_out_int(2) and  idc_out); -- OUT
1861 
 
1862 
dbusout(3)<= (reg_rd_out_int(3) and (idc_push or idc_sts or
1863 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1864 
                                 (gp_reg_tmp(3) and (st_st or sts_st))or                            -- NEW
1865 
                                 (bitpr_io_out(3) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1866 
                 (program_counter(3)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1867 
                 (program_counter_high_fr(3) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1868 
                 (pc_for_interrupt(3) and irq_st1) or
1869 
                                 (pc_for_interrupt(11) and irq_st2) or
1870 
                                 (reg_rd_out_int(3) and  idc_out); -- OUT
1871 
 
1872 
dbusout(4)<= (reg_rd_out_int(4) and (idc_push or idc_sts or
1873 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1874 
                                 (gp_reg_tmp(4) and (st_st or sts_st))or                            -- NEW
1875 
                                 (bitpr_io_out(4) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1876 
                 (program_counter(4)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1877 
                 (program_counter_high_fr(4) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1878 
                 (pc_for_interrupt(4) and irq_st1) or
1879 
                                 (pc_for_interrupt(12) and irq_st2) or
1880 
                                 (reg_rd_out_int(4) and  idc_out); -- OUT
1881 
 
1882 
dbusout(5)<= (reg_rd_out_int(5) and (idc_push or idc_sts or
1883 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1884 
                                 (gp_reg_tmp(5) and (st_st or sts_st))or                            -- NEW
1885 
                                 (bitpr_io_out(5) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1886 
                 (program_counter(5)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1887 
                 (program_counter_high_fr(5) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1888 
                 (pc_for_interrupt(5) and irq_st1) or
1889 
                                 (pc_for_interrupt(13) and irq_st2) or
1890 
                                 (reg_rd_out_int(5) and  idc_out); -- OUT
1891 
 
1892 
dbusout(6)<= (reg_rd_out_int(6) and (idc_push or idc_sts or
1893 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1894 
                                 (gp_reg_tmp(6) and (st_st or sts_st))or                            -- NEW
1895 
                                 (bitpr_io_out(6) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1896 
                 (program_counter(6)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1897 
                 (program_counter_high_fr(6) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1898 
                 (pc_for_interrupt(6) and irq_st1) or
1899 
                                 (pc_for_interrupt(14) and irq_st2) or
1900 
                                 (reg_rd_out_int(6) and  idc_out); -- OUT
1901 
 
1902 
dbusout(7)<= (reg_rd_out_int(7) and (idc_push or idc_sts or
1903 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1904 
                                 (gp_reg_tmp(7) and (st_st or sts_st))or                            -- NEW
1905 
                                 (bitpr_io_out(7) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1906 
                 (program_counter(7)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1907 
                 (program_counter_high_fr(7) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1908 
                 (pc_for_interrupt(7) and irq_st1) or
1909 
                                 (pc_for_interrupt(15) and irq_st2) or
1910 
                                 (reg_rd_out_int(7) and  idc_out); -- OUT
1911 
 
1912 
 
1913 
-- ALU CONNECTION
1914 
 
1915 
-- ALU Rr INPUT MUX
1916 
alu_data_r_in <= dex_dat8_immed       when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi)='1' else
1917 
                 "00"&dex_dat6_immed  when (idc_adiw or idc_sbiw) ='1' else
1918 
                 "00000000"           when (adiw_st or sbiw_st) ='1' else
1919 
                 reg_rr_out;
1920 
 
1921 
 
1922 
-- SynEDA CoreMultiplier
1923 
-- assignment(s): gp_reg_tmp
1924 
-- replace(s): reg_rd_out, gp_reg_tmp, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1925 
 
1926 
-- gp_reg_tmp STORES TEMPREOARY THE VALUE OF SOURCE REGISTER DURING ST/STD/STS INSTRUCTION
1927 
gp_registers_trig:process(cp2,ireset)
1928 
begin
1929 
if (ireset='0') then
1930 
gp_reg_tmp <= (others=>'0');
1931 
elsif (cp2='1' and cp2'event) then gp_reg_tmp <= gp_reg_tmp_cml_2;
1932 
 if (cp2en='1') then                                                      -- Clock enable
1933 
  -- if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or sts_st1)='1' then  -- CLOCK ENABLE
1934 
  if ((idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2) or idc_sts_cml_2)='1' then  -- CLOCK ENABLE
1935 
     gp_reg_tmp <= reg_rd_out_cml_2;
1936 
  end if;
1937 
 end if;
1938 
end if;
1939 
end process;
1940 
 
1941 
-- **********************************************************************************************************
1942 
 
1943 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1944 
-- +++++++++++++++++++++++++++++++++++++++ PROGRAM COUNTER ++++++++++++++++++++++++++++++++++++++++++++++++++
1945 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1946 
 
1947 
-- SynEDA CoreMultiplier
1948 
-- assignment(s): program_counter_high_fr
1949 
-- replace(s): program_counter, program_counter_high_fr, irq_st1, call_st1, idc_icall, idc_rcall
1950 
 
1951 
program_counter_high_store:process(cp2,ireset)
1952 
begin
1953 
if ireset='0' then                         -- RESET
1954 
program_counter_high_fr <=(others => '0');
1955 
elsif (cp2='1' and cp2'event) then program_counter_high_fr <= program_counter_high_fr_cml_2;       -- CLOCK
1956 
 if (cp2en='1') then                                                      -- Clock enable
1957 
  if (idc_rcall_cml_2 or idc_icall_cml_2 or call_st1_cml_2 or irq_st1_cml_2) ='1' then
1958 
   program_counter_high_fr <= program_counter_cml_2(15 downto 8);       -- STORE HIGH BYTE OF THE PROGRAMM COUNTER FOR RCALL/ICALL/CALL INSTRUCTIONS AND INTERRUPTS
1959 
  end if;
1960 
 end if;
1961 
end if;
1962 
end process;
1963 
 
1964 
 
1965 
-- SynEDA CoreMultiplier
1966 
-- assignment(s): program_counter_tmp
1967 
-- replace(s): program_counter_tmp, program_counter, idc_lpm
1968 
 
1969 
program_counter_for_lpm_elpm:process(cp2,ireset)
1970 
begin
1971 
if ireset='0' then                         -- RESET
1972 
program_counter_tmp<=(others => '0');
1973 
elsif (cp2='1' and cp2'event) then program_counter_tmp <= program_counter_tmp_cml_2;       -- CLOCK
1974 
 if (cp2en='1') then                                                      -- Clock enable
1975 
  if (idc_lpm_cml_2 or idc_elpm) ='1' then
1976 
   program_counter_tmp <= program_counter_cml_2;
1977 
  end if;
1978 
 end if;
1979 
end if;
1980 
end process;
1981 
 
1982 
-- SynEDA CoreMultiplier
1983 
-- assignment(s): pa15_pm
1984 
-- replace(s): rampz_out
1985 
 
1986 
pa15_pm <= rampz_out_cml_2(0) and idc_elpm; -- '0' WHEN LPM INSTRUCTIONS  RAMPZ(0) WHEN ELPM INSTRUCTION
1987 
 
1988 
-- OFFSET FOR BRBC/BRBS INSTRUCTIONS +63/-64
1989 
offset_brbx <= "0000000000"&dex_brxx_offset(5 downto 0) when (dex_brxx_offset(6)='0') else -- +
1990 
               "1111111111"&dex_brxx_offset(5 downto 0);                                   -- -
1991 
 
1992 
-- OFFSET FOR RJMP/RCALL INSTRUCTIONS +2047/-2048
1993 
offset_rxx <= "00000"&dex_adr12mem_s(10 downto 0) when (dex_adr12mem_s(11)='0') else       -- +
1994 
              "11111"&dex_adr12mem_s(10 downto 0);                                          -- -
1995 
 
1996 
program_counter <= pc_high&pc_low;
1997 
 
1998 
-- SynEDA CoreMultiplier
1999 
-- assignment(s): program_counter_in
2000 
-- replace(s): dbusin, bit_test_op_out, irqackad_int, program_counter_tmp, program_counter, irq_st1, call_st1, jmp_st1, ret_st1, ret_st2, reti_st1, reti_st2, lpm_st1, instruction_reg, idc_brbc, idc_brbs, idc_icall, idc_ijmp, idc_lpm, idc_rcall, idc_rjmp
2001 
 
2002 
program_counter_in <= program_counter_cml_2 + offset_brbx when ((idc_brbc_cml_2 or idc_brbs_cml_2) and  bit_test_op_out_cml_2) ='1'else  -- BRBC/BRBS
2003 
                      program_counter_cml_2 + offset_rxx when (idc_rjmp_cml_2 or idc_rcall_cml_2)='1'else     -- RJMP/RCALL
2004 
                      reg_z_out when (idc_ijmp_cml_2 or idc_icall_cml_2)='1'else                        -- IJMP/ICALL
2005 
                      pa15_pm&reg_z_out(15 downto 1) when (idc_lpm_cml_2 or idc_elpm) ='1'else    -- LPM/ELPM
2006 
                      instruction_reg_cml_2  when (jmp_st1_cml_2 or call_st1_cml_2)='1'else                    -- JMP/CALL
2007 
                      "0000000000"&irqackad_int_cml_2&'0' when irq_st1_cml_2 ='1' else                 -- INTERRUPT
2008 
                      dbusin_cml_2&"00000000"  when (ret_st1_cml_2 or reti_st1_cml_2)='1' else                 -- RET/RETI -> PC HIGH BYTE
2009 
                      "00000000"&dbusin_cml_2  when (ret_st2_cml_2 or reti_st2_cml_2)='1' else                 -- RET/RETI -> PC LOW BYTE
2010 
                      program_counter_tmp_cml_2 when (lpm_st1_cml_2)='1'                                 -- AFTER LPM/ELPM INSTRUCTION
2011 
                      else program_counter_cml_2+1;      -- THE MOST USUAL CASE
2012 
 
2013 
 
2014 
 
2015 
-- SynEDA CoreMultiplier
2016 
-- assignment(s): pc_low_en
2017 
-- replace(s): cpuwait, irq_st2, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, sts_st, lds_st, idc_adiw, idc_cbi, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_pop, idc_push, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
2018 
 
2019 
pc_low_en  <= not (idc_ld_x_cml_2 or idc_ld_y_cml_2 or idc_ld_z_cml_2 or idc_ldd_y_cml_2 or idc_ldd_z_cml_2 or
2020 
                       idc_st_x_cml_2 or idc_st_y_cml_2 or idc_st_z_cml_2 or idc_std_y_cml_2 or idc_std_z_cml_2 or
2021 
                                   ((sts_st_cml_2 or lds_st_cml_2) and cpuwait_cml_2)or
2022 
                                   idc_adiw_cml_2 or idc_sbiw_cml_2 or
2023 
                                   idc_push_cml_2 or idc_pop_cml_2 or
2024 
                                   idc_cbi_cml_2 or idc_sbi_cml_2 or
2025 
                                   rcall_st1_cml_2 or icall_st1_cml_2 or call_st2_cml_2 or irq_st2_cml_2 or cpuwait_cml_2 or
2026 
                                   ret_st1_cml_2 or reti_st1_cml_2);
2027 
 
2028 
 
2029 
-- SynEDA CoreMultiplier
2030 
-- assignment(s): pc_high_en
2031 
-- replace(s): cpuwait, irq_st2, call_st2, rcall_st1, icall_st1, ret_st2, reti_st2, sts_st, lds_st, idc_adiw, idc_cbi, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_pop, idc_push, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
2032 
 
2033 
pc_high_en <= not (idc_ld_x_cml_2 or idc_ld_y_cml_2 or idc_ld_z_cml_2 or idc_ldd_y_cml_2 or idc_ldd_z_cml_2 or
2034 
                       idc_st_x_cml_2 or idc_st_y_cml_2 or idc_st_z_cml_2 or idc_std_y_cml_2 or idc_std_z_cml_2 or
2035 
                                   ((sts_st_cml_2 or lds_st_cml_2) and cpuwait_cml_2) or
2036 
                                   idc_adiw_cml_2 or idc_sbiw_cml_2 or
2037 
                                   idc_push_cml_2 or idc_pop_cml_2 or
2038 
                                   idc_cbi_cml_2 or idc_sbi_cml_2 or
2039 
                                   rcall_st1_cml_2 or icall_st1_cml_2 or call_st2_cml_2 or irq_st2_cml_2 or cpuwait_cml_2 or
2040 
                                   ret_st2_cml_2 or reti_st2_cml_2);
2041 
 
2042 
-- SynEDA CoreMultiplier
2043 
-- assignment(s): pc_low
2044 
-- replace(s): pc_low
2045 
 
2046 
program_counter_low:process(cp2,ireset)
2047 
begin
2048 
if ireset='0' then                              -- RESET
2049 
pc_low<=(others => '0');
2050 
elsif (cp2='1' and cp2'event) then pc_low <= pc_low_cml_2;              -- CLOCK
2051 
 if (cp2en='1') then                                                    -- Clock enable
2052 
  if pc_low_en ='1' then
2053 
   pc_low <= program_counter_in(7 downto 0);
2054 
  end if;
2055 
 end if;
2056 
end if;
2057 
end process;
2058 
 
2059 
-- SynEDA CoreMultiplier
2060 
-- assignment(s): pc_high
2061 
-- replace(s): pc_high
2062 
 
2063 
program_counter_high:process(cp2,ireset)
2064 
begin
2065 
if ireset='0' then                               -- RESET
2066 
pc_high<=(others => '0');
2067 
elsif (cp2='1' and cp2'event) then pc_high <= pc_high_cml_2;               -- CLOCK
2068 
 if (cp2en='1') then                                                     -- Clock enable
2069 
  if pc_high_en ='1' then
2070 
   pc_high <= program_counter_in(15 downto 8);
2071 
  end if;
2072 
 end if;
2073 
end if;
2074 
end process;
2075 
 
2076 
pc <= program_counter;
2077 
 
2078 
 
2079 
-- SynEDA CoreMultiplier
2080 
-- assignment(s): pc_for_interrupt
2081 
-- replace(s): program_counter, pc_for_interrupt
2082 
 
2083 
program_counter_for_interrupt:process(cp2,ireset)
2084 
begin
2085 
if ireset='0' then                                 -- RESET
2086 
pc_for_interrupt <=(others => '0');
2087 
elsif (cp2='1' and cp2'event) then pc_for_interrupt <= pc_for_interrupt_cml_2;               -- CLOCK
2088 
 if (cp2en='1') then                                                     -- Clock enable
2089 
  if irq_start ='1' then
2090 
   pc_for_interrupt <= program_counter_cml_2;
2091 
  end if;
2092 
 end if;
2093 
end if;
2094 
end process;
2095 
 
2096 
-- END OF PROGRAM COUNTER
2097 
 
2098 
-- STATE MACHINES
2099 
 
2100 
-- SynEDA CoreMultiplier
2101 
-- assignment(s): skip_inst_start
2102 
-- replace(s): bit_test_op_out, idc_cpse, idc_sbic, idc_sbis, idc_sbrc, idc_sbrs
2103 
 
2104 
skip_inst_start <= ((idc_sbrc_cml_2 or idc_sbrs_cml_2 or idc_sbic_cml_2 or idc_sbis_cml_2) and bit_test_op_out_cml_2)or
2105 
                   (idc_cpse_cml_2 and alu_z_flag_out);
2106 
 
2107 
-- SynEDA CoreMultiplier
2108 
-- assignment(s): nskip_inst_st0, skip_inst_st1, skip_inst_st2
2109 
-- replace(s): two_word_inst, nskip_inst_st0, skip_inst_st1, skip_inst_st2
2110 
 
2111 
skip_instruction_sm:process(cp2,ireset)
2112 
begin
2113 
if ireset='0' then                       -- RESET
2114 
nskip_inst_st0 <= '0';
2115 
skip_inst_st1  <= '0';
2116 
skip_inst_st2  <= '0';
2117 
elsif (cp2='1' and cp2'event) then skip_inst_st2 <= skip_inst_st2_cml_2; skip_inst_st1 <= skip_inst_st1_cml_2; nskip_inst_st0 <= nskip_inst_st0_cml_2;       -- CLOCK
2118 
 if (cp2en='1') then                                 -- Clock enable
2119 
  nskip_inst_st0 <= (not nskip_inst_st0_cml_2 and skip_inst_start) or
2120 
                    (nskip_inst_st0_cml_2 and not((skip_inst_st1_cml_2 and not two_word_inst_cml_2) or skip_inst_st2_cml_2));
2121 
  skip_inst_st1  <= (not skip_inst_st1_cml_2 and not nskip_inst_st0_cml_2 and skip_inst_start);
2122 
  skip_inst_st2  <=  not skip_inst_st2_cml_2 and skip_inst_st1_cml_2 and two_word_inst_cml_2;
2123 
 end if;
2124 
end if;
2125 
end process;
2126 
 
2127 
 
2128 
 
2129 
-- SynEDA CoreMultiplier
2130 
-- assignment(s): adiw_st, sbiw_st
2131 
-- replace(s): adiw_st, idc_adiw, sbiw_st, idc_sbiw
2132 
 
2133 
alu_state_machines:process(cp2,ireset)
2134 
begin
2135 
if ireset='0' then                       -- RESET
2136 
adiw_st <= '0';
2137 
sbiw_st <= '0';
2138 
elsif (cp2='1' and cp2'event) then sbiw_st <= sbiw_st_cml_2; adiw_st <= adiw_st_cml_2;       -- CLOCK
2139 
 if (cp2en='1') then                                     -- Clock enable
2140 
  adiw_st <= not adiw_st_cml_2 and idc_adiw_cml_2;
2141 
  sbiw_st <= not sbiw_st_cml_2 and idc_sbiw_cml_2;
2142 
 end if;
2143 
end if;
2144 
end process;
2145 
 
2146 
 
2147 
-- SynEDA CoreMultiplier
2148 
-- assignment(s): nlpm_st0, lpm_st1, lpm_st2
2149 
-- replace(s): nlpm_st0, lpm_st2, idc_lpm, lpm_st1
2150 
 
2151 
lpm_state_machine:process(cp2,ireset)
2152 
begin
2153 
if ireset='0' then                       -- RESET
2154 
nlpm_st0 <= '0';
2155 
lpm_st1 <= '0';
2156 
lpm_st2 <= '0';
2157 
elsif (cp2='1' and cp2'event) then lpm_st2 <= lpm_st2_cml_2; lpm_st1 <= lpm_st1_cml_2; nlpm_st0 <= nlpm_st0_cml_2;       -- CLOCK
2158 
 if (cp2en='1') then                                                      -- Clock enable
2159 
  nlpm_st0 <= (not nlpm_st0_cml_2 and (idc_lpm_cml_2 or idc_elpm)) or (nlpm_st0_cml_2 and not lpm_st2_cml_2);
2160 
  lpm_st1  <= (not lpm_st1_cml_2 and not nlpm_st0_cml_2 and (idc_lpm_cml_2 or idc_elpm)); -- ??
2161 
  lpm_st2  <=  not lpm_st2_cml_2 and lpm_st1_cml_2;
2162 
 end if;
2163 
end if;
2164 
end process;
2165 
 
2166 
 
2167 
-- SynEDA CoreMultiplier
2168 
-- assignment(s): lds_st
2169 
-- replace(s): cpuwait, lds_st, idc_lds
2170 
 
2171 
lds_state_machine:process(cp2,ireset)
2172 
begin
2173 
if ireset='0' then                       -- RESET
2174 
 lds_st <= '0';
2175 
elsif (cp2='1' and cp2'event) then lds_st <= lds_st_cml_2;       -- CLOCK
2176 
 if (cp2en='1') then                                                      -- Clock enable
2177 
  lds_st  <= (not lds_st_cml_2 and idc_lds_cml_2) or (lds_st_cml_2 and cpuwait_cml_2);
2178 
 end if;
2179 
end if;
2180 
end process;
2181 
 
2182 
 
2183 
-- SynEDA CoreMultiplier
2184 
-- assignment(s): sts_st
2185 
-- replace(s): cpuwait, sts_st, idc_sts
2186 
 
2187 
sts_state_machine:process(cp2,ireset)
2188 
begin
2189 
if ireset='0' then                       -- RESET
2190 
 sts_st <= '0';
2191 
elsif (cp2='1' and cp2'event) then sts_st <= sts_st_cml_2;       -- CLOCK
2192 
 if (cp2en='1') then                                                      -- Clock enable
2193 
  sts_st  <= (not sts_st_cml_2 and idc_sts_cml_2) or (sts_st_cml_2 and cpuwait_cml_2);
2194 
 end if;
2195 
end if;
2196 
end process;
2197 
 
2198 
-- SynEDA CoreMultiplier
2199 
-- assignment(s): njmp_st0, jmp_st1, jmp_st2
2200 
-- replace(s): njmp_st0, jmp_st2, idc_jmp, jmp_st1
2201 
 
2202 
jmp_state_machine:process(cp2,ireset)
2203 
begin
2204 
if ireset='0' then                       -- RESET
2205 
njmp_st0 <= '0';
2206 
jmp_st1 <= '0';
2207 
jmp_st2 <= '0';
2208 
elsif (cp2='1' and cp2'event) then jmp_st2 <= jmp_st2_cml_2; jmp_st1 <= jmp_st1_cml_2; njmp_st0 <= njmp_st0_cml_2;       -- CLOCK
2209 
 if (cp2en='1') then                                                      -- Clock enable
2210 
  njmp_st0 <= (not njmp_st0_cml_2 and idc_jmp_cml_2) or (njmp_st0_cml_2 and not jmp_st2_cml_2);
2211 
  jmp_st1  <= not jmp_st1_cml_2 and not njmp_st0_cml_2 and idc_jmp_cml_2; -- ??
2212 
  jmp_st2  <= not jmp_st2_cml_2 and jmp_st1_cml_2;
2213 
 end if;
2214 
end if;
2215 
end process;
2216 
 
2217 
-- SynEDA CoreMultiplier
2218 
-- assignment(s): nrcall_st0, rcall_st1, rcall_st2
2219 
-- replace(s): cpuwait, nrcall_st0, rcall_st2, idc_rcall, rcall_st1
2220 
 
2221 
rcall_state_machine:process(cp2,ireset)
2222 
begin
2223 
if ireset='0' then                       -- RESET
2224 
nrcall_st0 <= '0';
2225 
rcall_st1 <= '0';
2226 
rcall_st2 <= '0';
2227 
elsif (cp2='1' and cp2'event) then rcall_st2 <= rcall_st2_cml_2; rcall_st1 <= rcall_st1_cml_2; nrcall_st0 <= nrcall_st0_cml_2;       -- CLOCK
2228 
 if (cp2en='1') then                                                      -- Clock enable
2229 
  nrcall_st0 <= (not nrcall_st0_cml_2 and idc_rcall_cml_2) or (nrcall_st0_cml_2 and not (rcall_st2_cml_2 and not cpuwait_cml_2));
2230 
  rcall_st1  <= (not rcall_st1_cml_2 and not nrcall_st0_cml_2 and idc_rcall_cml_2) or (rcall_st1_cml_2 and cpuwait_cml_2);
2231 
  rcall_st2  <= (not rcall_st2_cml_2 and rcall_st1_cml_2 and not cpuwait_cml_2) or (rcall_st2_cml_2 and cpuwait_cml_2);
2232 
 end if;
2233 
end if;
2234 
end process;
2235 
 
2236 
-- SynEDA CoreMultiplier
2237 
-- assignment(s): nicall_st0, icall_st1, icall_st2
2238 
-- replace(s): cpuwait, nicall_st0, icall_st2, idc_icall, icall_st1
2239 
 
2240 
icall_state_machine:process(cp2,ireset)
2241 
begin
2242 
if ireset='0' then                       -- RESET
2243 
nicall_st0 <= '0';
2244 
icall_st1 <= '0';
2245 
icall_st2 <= '0';
2246 
elsif (cp2='1' and cp2'event) then icall_st2 <= icall_st2_cml_2; icall_st1 <= icall_st1_cml_2; nicall_st0 <= nicall_st0_cml_2;       -- CLOCK
2247 
 if (cp2en='1') then                                                      -- Clock enable
2248 
  nicall_st0 <= (not nicall_st0_cml_2 and idc_icall_cml_2) or (nicall_st0_cml_2 and not (icall_st2_cml_2 and not cpuwait_cml_2));
2249 
  icall_st1  <= (not icall_st1_cml_2 and not nicall_st0_cml_2 and idc_icall_cml_2) or (icall_st1_cml_2 and cpuwait_cml_2);
2250 
  icall_st2  <= (not icall_st2_cml_2 and icall_st1_cml_2 and not cpuwait_cml_2) or (icall_st2_cml_2 and cpuwait_cml_2);
2251 
 end if;
2252 
end if;
2253 
end process;
2254 
 
2255 
-- SynEDA CoreMultiplier
2256 
-- assignment(s): ncall_st0, call_st1, call_st2, call_st3
2257 
-- replace(s): cpuwait, ncall_st0, call_st3, idc_call, call_st1, call_st2
2258 
 
2259 
call_state_machine:process(cp2,ireset)
2260 
begin
2261 
if ireset='0' then                       -- RESET
2262 
ncall_st0 <= '0';
2263 
call_st1 <= '0';
2264 
call_st2 <= '0';
2265 
call_st3  <= '0';
2266 
elsif (cp2='1' and cp2'event) then call_st3 <= call_st3_cml_2; call_st2 <= call_st2_cml_2; call_st1 <= call_st1_cml_2; ncall_st0 <= ncall_st0_cml_2;       -- CLOCK
2267 
 if (cp2en='1') then                                                      -- Clock enable
2268 
  ncall_st0 <= (not ncall_st0_cml_2 and idc_call_cml_2) or (ncall_st0_cml_2 and not( call_st3_cml_2 and not cpuwait_cml_2));
2269 
  call_st1  <= not call_st1_cml_2 and not ncall_st0_cml_2 and idc_call_cml_2;
2270 
  call_st2  <= (not call_st2_cml_2 and call_st1_cml_2) or (call_st2_cml_2 and cpuwait_cml_2);
2271 
  call_st3  <= (not call_st3_cml_2 and call_st2_cml_2 and not cpuwait_cml_2) or (call_st3_cml_2 and cpuwait_cml_2);
2272 
 end if;
2273 
end if;
2274 
end process;
2275 
 
2276 
-- SynEDA CoreMultiplier
2277 
-- assignment(s): nret_st0, ret_st1, ret_st2, ret_st3
2278 
-- replace(s): nret_st0, ret_st3, idc_ret, cpuwait, ret_st1, ret_st2
2279 
 
2280 
ret_state_machine:process(cp2,ireset)
2281 
begin
2282 
if ireset='0' then                       -- RESET
2283 
nret_st0 <= '0';
2284 
ret_st1 <= '0';
2285 
ret_st2 <= '0';
2286 
ret_st3  <= '0';
2287 
elsif (cp2='1' and cp2'event) then ret_st3 <= ret_st3_cml_2; ret_st2 <= ret_st2_cml_2; ret_st1 <= ret_st1_cml_2; nret_st0 <= nret_st0_cml_2;       -- CLOCK
2288 
 if (cp2en='1') then                                                      -- Clock enable
2289 
  nret_st0 <= (not nret_st0_cml_2 and idc_ret_cml_2) or (nret_st0_cml_2 and not ret_st3_cml_2);
2290 
  ret_st1  <= (not ret_st1_cml_2 and not nret_st0_cml_2 and idc_ret_cml_2) or (ret_st1_cml_2 and cpuwait_cml_2);
2291 
  ret_st2  <= (not ret_st2_cml_2 and ret_st1_cml_2 and not cpuwait_cml_2) or (ret_st2_cml_2 and cpuwait_cml_2) ;
2292 
  ret_st3  <= not ret_st3_cml_2 and ret_st2_cml_2 and not cpuwait_cml_2;
2293 
 end if;
2294 
end if;
2295 
end process;
2296 
 
2297 
-- SynEDA CoreMultiplier
2298 
-- assignment(s): nreti_st0, reti_st1, reti_st2, reti_st3
2299 
-- replace(s): nreti_st0, reti_st3, idc_reti, cpuwait, reti_st1, reti_st2
2300 
 
2301 
reti_state_machine:process(cp2,ireset)
2302 
begin
2303 
if ireset='0' then                       -- RESET
2304 
nreti_st0 <= '0';
2305 
reti_st1 <= '0';
2306 
reti_st2 <= '0';
2307 
reti_st3  <= '0';
2308 
elsif (cp2='1' and cp2'event) then reti_st3 <= reti_st3_cml_2; reti_st2 <= reti_st2_cml_2; reti_st1 <= reti_st1_cml_2; nreti_st0 <= nreti_st0_cml_2;       -- CLOCK
2309 
 if (cp2en='1') then                                                      -- Clock enable
2310 
  nreti_st0 <= (not nreti_st0_cml_2 and idc_reti_cml_2) or (nreti_st0_cml_2 and not reti_st3_cml_2);
2311 
  reti_st1  <= (not reti_st1_cml_2 and not nreti_st0_cml_2 and idc_reti_cml_2) or (reti_st1_cml_2 and cpuwait_cml_2);
2312 
  reti_st2  <= (not reti_st2_cml_2 and reti_st1_cml_2 and not cpuwait_cml_2) or (reti_st2_cml_2 and cpuwait_cml_2) ;
2313 
  reti_st3  <= not reti_st3_cml_2 and reti_st2_cml_2 and not cpuwait_cml_2;
2314 
 end if;
2315 
end if;
2316 
end process;
2317 
 
2318 
 
2319 
-- INTERRUPT LOGIC AND STATE MACHINE
2320 
 
2321 
-- SynEDA CoreMultiplier
2322 
-- assignment(s): irq_int
2323 
-- replace(s): irqlines
2324 
 
2325 
irq_int <= '0' when      irqlines_cml_2="00000000000000000000000" else '1';
2326 
 
2327 
irq_vector_adr(15 downto 6)<=(others => '0');
2328 
irq_vector_adr(0) <= '0';
2329 
-- SynEDA CoreMultiplier
2330 
-- assignment(s): irq_vector_adr
2331 
-- replace(s): irqlines
2332 
 
2333 
-- PRIORITY ENCODER
2334 
irq_vector_adr(5 downto 1) <= "00001" when irqlines_cml_2(0)='1'  else -- 0x0002
2335 
                              "00010" when irqlines_cml_2(1)='1'  else -- 0x0004
2336 
                              "00011" when irqlines_cml_2(2)='1'  else -- 0x0006
2337 
                              "00100" when irqlines_cml_2(3)='1'  else -- 0x0008
2338 
                              "00101" when irqlines_cml_2(4)='1'  else -- 0x000A
2339 
                              "00110" when irqlines_cml_2(5)='1'  else -- 0x000C
2340 
                              "00111" when irqlines_cml_2(6)='1'  else -- 0x000E
2341 
                              "01000" when irqlines_cml_2(7)='1'  else -- 0x0010
2342 
                              "01001" when irqlines_cml_2(8)='1'  else -- 0x0012
2343 
                              "01010" when irqlines_cml_2(9)='1'  else -- 0x0014
2344 
                              "01011" when irqlines_cml_2(10)='1' else -- 0x0016
2345 
                              "01100" when irqlines_cml_2(11)='1' else -- 0x0018
2346 
                              "01101" when irqlines_cml_2(12)='1' else -- 0x001A
2347 
                              "01110" when irqlines_cml_2(13)='1' else -- 0x001C
2348 
                              "01111" when irqlines_cml_2(14)='1' else -- 0x001E
2349 
                              "10000" when irqlines_cml_2(15)='1' else -- 0x0020
2350 
                              "10001" when irqlines_cml_2(16)='1' else -- 0x0022
2351 
                              "10010" when irqlines_cml_2(17)='1' else -- 0x0024
2352 
                              "10011" when irqlines_cml_2(18)='1' else -- 0x0026
2353 
                              "10100" when irqlines_cml_2(19)='1' else -- 0x0028
2354 
                              "10101" when irqlines_cml_2(20)='1' else -- 0x002A
2355 
                              "10110" when irqlines_cml_2(21)='1' else -- 0x002C
2356 
                              "10111" when irqlines_cml_2(22)='1' else -- 0x002E
2357 
                                                          "00000";
2358 
 
2359 
-- SynEDA CoreMultiplier
2360 
-- assignment(s): cpu_busy
2361 
-- replace(s): cpuwait, bit_test_op_out, two_word_inst, nirq_st0, call_st1, call_st2, call_st3, rcall_st1, rcall_st2, icall_st1, icall_st2, jmp_st1, ret_st1, ret_st2, reti_st1, reti_st2, skip_inst_st1, lpm_st1, sts_st, lds_st, st_st, ld_st, push_st, pop_st, iowe_int, dbusout_int, idc_adiw, idc_bclr, idc_brbc, idc_brbs, idc_call, idc_cbi, idc_icall, idc_ijmp, idc_jmp, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_lpm, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_rjmp, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts, sreg_bop_wr_en, sreg_adr_eq
2362 
 
2363 
-- MULTI CYCLE INSTRUCTION FLAG FOR IRQ
2364 
cpu_busy <= idc_adiw_cml_2 or idc_sbiw_cml_2 or idc_cbi_cml_2 or idc_sbi_cml_2 or
2365 
            idc_rjmp_cml_2 or idc_ijmp_cml_2 or
2366 
                        idc_jmp_cml_2 or jmp_st1_cml_2 or
2367 
--                      idc_brbs or idc_brbc or -- Old variant
2368 
            ((idc_brbc_cml_2 or idc_brbs_cml_2) and  bit_test_op_out_cml_2) or
2369 
                        idc_lpm_cml_2 or lpm_st1_cml_2 or
2370 
                        skip_inst_start or (skip_inst_st1_cml_2 and two_word_inst_cml_2) or
2371 
                        idc_ld_x_cml_2 or idc_ld_y_cml_2 or idc_ldd_y_cml_2 or idc_ld_z_cml_2 or idc_ldd_z_cml_2 or (ld_st_cml_2 and cpuwait_cml_2) or
2372 
                        idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2 or (st_st_cml_2 and cpuwait_cml_2) or
2373 
                        idc_lds_cml_2 or (lds_st_cml_2 and cpuwait_cml_2) or
2374 
                        idc_sts_cml_2 or (sts_st_cml_2 and cpuwait_cml_2) or
2375 
                        idc_rcall_cml_2 or rcall_st1_cml_2 or (rcall_st2_cml_2 and cpuwait_cml_2) or           -- RCALL
2376 
                        idc_icall_cml_2 or icall_st1_cml_2 or (icall_st2_cml_2 and cpuwait_cml_2) or               -- ICALL
2377 
                        idc_call_cml_2 or call_st1_cml_2 or call_st2_cml_2 or (call_st3_cml_2 and cpuwait_cml_2) or  -- CALL
2378 
                        idc_push_cml_2 or (push_st_cml_2 and cpuwait_cml_2) or                           -- PUSH (added 14.07.05)
2379 
                        idc_pop_cml_2 or (pop_st_cml_2 and cpuwait_cml_2) or                             -- POP  (added 14.07.05)
2380 
                    (idc_bclr_cml_2 and sreg_bop_wr_en_cml_2(7)) or                 -- ??? CLI
2381 
                    (iowe_int_cml_2 and sreg_adr_eq_cml_2 and not dbusout_int_cml_2(7))or -- ??? Writing '0' to I flag (OUT/STD/ST/STD)
2382 
                        nirq_st0_cml_2 or
2383 
--                      idc_ret  or nret_st0 or                             -- Old variant
2384 
                        idc_ret_cml_2 or ret_st1_cml_2 or ret_st2_cml_2 or
2385 
--                      idc_reti or nreti_st0;                              -- At least one instruction must be executed after RETI and before the new interrupt.
2386 
                        idc_reti_cml_2 or reti_st1_cml_2 or reti_st2_cml_2;
2387 
 
2388 
sreg_adr_eq <= '1' when adr_int=SREG_Address else '0';
2389 
 
2390 
--irq_start <= irq_int and not cpu_busy and globint;
2391 
irq_start <= irq_int and not cpu_busy and globint;
2392 
 
2393 
-- SynEDA CoreMultiplier
2394 
-- assignment(s): nirq_st0, irq_st1, irq_st2, irq_st3
2395 
-- replace(s): cpuwait, nirq_st0, irq_st3, irq_st1, irq_st2
2396 
 
2397 
irq_state_machine:process(cp2,ireset)
2398 
begin
2399 
if ireset='0' then                       -- RESET
2400 
nirq_st0 <= '0';
2401 
irq_st1 <= '0';
2402 
irq_st2 <= '0';
2403 
irq_st3 <= '0';
2404 
elsif (cp2='1' and cp2'event) then irq_st3 <= irq_st3_cml_2; irq_st2 <= irq_st2_cml_2; irq_st1 <= irq_st1_cml_2; nirq_st0 <= nirq_st0_cml_2;       -- CLOCK
2405 
 if (cp2en='1') then                                                      -- Clock enable
2406 
  nirq_st0 <= (not nirq_st0_cml_2 and irq_start) or (nirq_st0_cml_2 and not (irq_st3_cml_2 and not cpuwait_cml_2));
2407 
  irq_st1  <= (not irq_st1_cml_2 and not nirq_st0_cml_2 and irq_start);
2408 
  irq_st2  <= (not irq_st2_cml_2 and irq_st1_cml_2) or (irq_st2_cml_2 and cpuwait_cml_2);
2409 
  irq_st3  <= (not irq_st3_cml_2 and irq_st2_cml_2 and not cpuwait_cml_2) or (irq_st3_cml_2 and cpuwait_cml_2);
2410 
 end if;
2411 
end if;
2412 
end process;
2413 
 
2414 
-- SynEDA CoreMultiplier
2415 
-- assignment(s): irqack_int
2416 
-- replace(s): irqack_int
2417 
 
2418 
irqack_reg:process(cp2,ireset)
2419 
begin
2420 
if ireset='0' then                       -- RESET
2421 
irqack_int<='0';
2422 
elsif (cp2='1' and cp2'event) then irqack_int <= irqack_int_cml_2;       -- CLOCK
2423 
 if (cp2en='1') then                                                      -- Clock enable
2424 
  irqack_int<= not irqack_int_cml_2 and irq_start;
2425 
 end if;
2426 
end if;
2427 
end process;
2428 
-- SynEDA CoreMultiplier
2429 
-- assignment(s): irqack
2430 
-- replace(s): irqack_int
2431 
 
2432 
irqack_cml_out <= irqack_int_cml_2;
2433 
 
2434 
-- SynEDA CoreMultiplier
2435 
-- assignment(s): irqackad_int
2436 
-- replace(s): irqackad_int
2437 
 
2438 
irqackad_reg:process(cp2,ireset)
2439 
begin
2440 
if ireset='0' then                                -- RESET
2441 
irqackad_int<=(others=>'0');
2442 
elsif (cp2='1' and cp2'event) then irqackad_int <= irqackad_int_cml_2;              -- CLOCK
2443 
 if (cp2en='1') then                                                      -- Clock enable
2444 
  irqackad_int <= irq_vector_adr(5 downto 1);
2445 
 end if;
2446 
end if;
2447 
end process;
2448 
-- SynEDA CoreMultiplier
2449 
-- assignment(s): irqackad
2450 
-- replace(s): irqackad_int
2451 
 
2452 
irqackad_cml_out <= irqackad_int_cml_2;
2453 
 
2454 
-- *******************************************************************************************
2455 
 
2456 
-- SynEDA CoreMultiplier
2457 
-- assignment(s): ijmp_st, rjmp_st, brxx_st, push_st, pop_st
2458 
-- replace(s): ijmp_st, idc_ijmp, rjmp_st, idc_rjmp, bit_test_op_out, brxx_st, idc_brbc, idc_brbs, cpuwait, push_st, idc_push, pop_st, idc_pop
2459 
 
2460 
rjmp_push_pop_ijmp_state_brxx_machine:process(cp2,ireset)
2461 
begin
2462 
if ireset='0' then                       -- RESET
2463 
rjmp_st <= '0';
2464 
ijmp_st <= '0';
2465 
push_st <= '0';
2466 
pop_st <= '0';
2467 
brxx_st <= '0';
2468 
elsif (cp2='1' and cp2'event) then pop_st <= pop_st_cml_2; push_st <= push_st_cml_2; brxx_st <= brxx_st_cml_2; rjmp_st <= rjmp_st_cml_2; ijmp_st <= ijmp_st_cml_2;       -- CLOCK
2469 
 if (cp2en='1') then                                                      -- Clock enable
2470 
  rjmp_st <= idc_rjmp_cml_2;    -- ??
2471 
  ijmp_st <= idc_ijmp_cml_2;
2472 
  push_st <= (not push_st_cml_2 and idc_push_cml_2) or (push_st_cml_2 and cpuwait_cml_2);
2473 
  pop_st  <= (not pop_st_cml_2  and idc_pop_cml_2) or (pop_st_cml_2 and cpuwait_cml_2);
2474 
  brxx_st <= not brxx_st_cml_2 and (idc_brbc_cml_2 or idc_brbs_cml_2) and bit_test_op_out_cml_2;
2475 
 end if;
2476 
end if;
2477 
end process;
2478 
 
2479 
-- SynEDA CoreMultiplier
2480 
-- assignment(s): st_st, ld_st
2481 
-- replace(s): cpuwait, st_st, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, ld_st, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z
2482 
 
2483 
-- LD/LDD/ST/STD
2484 
ld_st_state_machine:process(cp2,ireset)
2485 
begin
2486 
if ireset='0' then                       -- RESET
2487 
ld_st <= '0';
2488 
st_st <= '0';
2489 
elsif (cp2='1' and cp2'event) then ld_st <= ld_st_cml_2; st_st <= st_st_cml_2;       -- CLOCK
2490 
 if (cp2en='1') then                                                      -- Clock enable
2491 
  ld_st <= (not ld_st_cml_2 and (idc_ld_x_cml_2 or idc_ld_y_cml_2 or idc_ldd_y_cml_2 or idc_ld_z_cml_2 or idc_ldd_z_cml_2)) or (ld_st_cml_2 and cpuwait_cml_2);
2492 
  st_st <= (not st_st_cml_2 and (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_std_y_cml_2 or idc_st_z_cml_2 or idc_std_z_cml_2)) or (st_st_cml_2 and cpuwait_cml_2);
2493 
 end if;
2494 
end if;
2495 
end process;
2496 
 
2497 
-- SynEDA CoreMultiplier
2498 
-- assignment(s): sbi_st, cbi_st, cbi_sbi_io_adr_tmp, cbi_sbi_bit_num_tmp
2499 
-- replace(s): sbi_st, idc_sbi, cbi_st, idc_cbi, dex_adr5port, cbi_sbi_io_adr_tmp, dex_bitop_bitnum, cbi_sbi_bit_num_tmp
2500 
 
2501 
-- SBI/CBI
2502 
sbi_cbi_machine:process(cp2,ireset)
2503 
begin
2504 
if ireset='0' then                       -- RESET
2505 
sbi_st <= '0';
2506 
cbi_st <= '0';
2507 
cbi_sbi_io_adr_tmp  <= (others => '0');
2508 
cbi_sbi_bit_num_tmp     <= (others => '0');
2509 
elsif (cp2='1' and cp2'event) then cbi_sbi_bit_num_tmp <= cbi_sbi_bit_num_tmp_cml_2; cbi_sbi_io_adr_tmp <= cbi_sbi_io_adr_tmp_cml_2; cbi_st <= cbi_st_cml_2; sbi_st <= sbi_st_cml_2;       -- CLOCK
2510 
 if (cp2en='1') then                                                      -- Clock enable
2511 
  sbi_st <= not sbi_st_cml_2 and idc_sbi_cml_2;
2512 
  cbi_st <= not cbi_st_cml_2 and idc_cbi_cml_2;
2513 
  cbi_sbi_io_adr_tmp <= dex_adr5port_cml_2;
2514 
  cbi_sbi_bit_num_tmp <= dex_bitop_bitnum_cml_2;
2515 
 end if;
2516 
end if;
2517 
end process;
2518 
 
2519 
-- ########################################################################################
2520 
 
2521 
-- SREG FLAGS WRITE ENABLE LOGIC
2522 
 
2523 
--bclr_bset_op_en_logic:for i in sreg_bop_wr_en'range generate
2524 
--sreg_bop_wr_en(i) <= '1' when (dex_bitnum_sreg=i and (idc_bclr or idc_bset)='1') else '0';
2525 
--end generate;
2526 
 
2527 
sreg_bop_wr_en(0) <= '1' when (dex_bitnum_sreg=0 and (idc_bclr or idc_bset)='1') else '0';
2528 
sreg_bop_wr_en(1) <= '1' when (dex_bitnum_sreg=1 and (idc_bclr or idc_bset)='1') else '0';
2529 
sreg_bop_wr_en(2) <= '1' when (dex_bitnum_sreg=2 and (idc_bclr or idc_bset)='1') else '0';
2530 
sreg_bop_wr_en(3) <= '1' when (dex_bitnum_sreg=3 and (idc_bclr or idc_bset)='1') else '0';
2531 
sreg_bop_wr_en(4) <= '1' when (dex_bitnum_sreg=4 and (idc_bclr or idc_bset)='1') else '0';
2532 
sreg_bop_wr_en(5) <= '1' when (dex_bitnum_sreg=5 and (idc_bclr or idc_bset)='1') else '0';
2533 
sreg_bop_wr_en(6) <= '1' when (dex_bitnum_sreg=6 and (idc_bclr or idc_bset)='1') else '0';
2534 
sreg_bop_wr_en(7) <= '1' when (dex_bitnum_sreg=7 and (idc_bclr or idc_bset)='1') else '0';
2535 
 
2536 
-- SynEDA CoreMultiplier
2537 
-- assignment(s): sreg_c_wr_en
2538 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_lsr, idc_neg, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi, sreg_bop_wr_en
2539 
 
2540 
sreg_c_wr_en <= idc_add_cml_2 or idc_adc_cml_2 or (idc_adiw_cml_2 or adiw_st_cml_2) or idc_sub_cml_2  or idc_subi_cml_2 or
2541 
                idc_sbc_cml_2 or idc_sbci_cml_2 or (idc_sbiw_cml_2 or sbiw_st_cml_2) or idc_com_cml_2 or idc_neg_cml_2 or
2542 
                                idc_cp_cml_2 or idc_cpc_cml_2 or idc_cpi_cml_2 or
2543 
                idc_lsr_cml_2 or idc_ror_cml_2 or idc_asr_cml_2 or sreg_bop_wr_en_cml_2(0);
2544 
 
2545 
-- SynEDA CoreMultiplier
2546 
-- assignment(s): sreg_z_wr_en
2547 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_adiw, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi, sreg_bop_wr_en
2548 
 
2549 
sreg_z_wr_en <= idc_add_cml_2 or idc_adc_cml_2 or (idc_adiw_cml_2 or adiw_st_cml_2) or idc_sub_cml_2  or idc_subi_cml_2 or
2550 
                idc_sbc_cml_2 or idc_sbci_cml_2 or (idc_sbiw_cml_2 or sbiw_st_cml_2) or
2551 
                                idc_cp_cml_2 or idc_cpc_cml_2 or idc_cpi_cml_2 or
2552 
                idc_and_cml_2 or idc_andi_cml_2 or idc_or_cml_2 or idc_ori_cml_2 or idc_eor_cml_2 or idc_com_cml_2 or idc_neg_cml_2 or
2553 
                idc_inc_cml_2 or idc_dec_cml_2 or idc_lsr_cml_2 or idc_ror_cml_2 or idc_asr_cml_2 or sreg_bop_wr_en_cml_2(1);
2554 
 
2555 
 
2556 
-- SynEDA CoreMultiplier
2557 
-- assignment(s): sreg_n_wr_en
2558 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2559 
 
2560 
sreg_n_wr_en <= idc_add_cml_2 or idc_adc_cml_2 or adiw_st_cml_2 or idc_sub_cml_2  or idc_subi_cml_2 or
2561 
                idc_sbc_cml_2 or idc_sbci_cml_2 or sbiw_st_cml_2 or
2562 
                                idc_cp_cml_2 or idc_cpc_cml_2 or idc_cpi_cml_2 or
2563 
                idc_and_cml_2 or idc_andi_cml_2 or idc_or_cml_2 or idc_ori_cml_2 or idc_eor_cml_2 or idc_com_cml_2 or idc_neg_cml_2 or
2564 
                idc_inc_cml_2 or idc_dec_cml_2 or idc_lsr_cml_2 or idc_ror_cml_2 or idc_asr_cml_2 or sreg_bop_wr_en_cml_2(2);
2565 
 
2566 
-- SynEDA CoreMultiplier
2567 
-- assignment(s): sreg_v_wr_en
2568 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2569 
 
2570 
sreg_v_wr_en <= idc_add_cml_2 or idc_adc_cml_2 or adiw_st_cml_2 or idc_sub_cml_2  or idc_subi_cml_2 or -- idc_adiw
2571 
                idc_sbc_cml_2 or idc_sbci_cml_2 or sbiw_st_cml_2 or idc_neg_cml_2 or idc_com_cml_2 or  -- idc_sbiw
2572 
                idc_inc_cml_2 or idc_dec_cml_2 or
2573 
                                idc_cp_cml_2 or idc_cpc_cml_2 or idc_cpi_cml_2 or
2574 
                idc_lsr_cml_2 or idc_ror_cml_2 or idc_asr_cml_2 or sreg_bop_wr_en_cml_2(3) or
2575 
                                idc_and_cml_2 or idc_andi_cml_2 or idc_or_cml_2 or idc_ori_cml_2 or idc_eor_cml_2; -- V-flag bug fixing
2576 
 
2577 
-- SynEDA CoreMultiplier
2578 
-- assignment(s): sreg_s_wr_en
2579 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_add, idc_and, idc_andi, idc_asr, idc_com, idc_cp, idc_cpc, idc_cpi, idc_dec, idc_eor, idc_inc, idc_lsr, idc_neg, idc_or, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2580 
 
2581 
sreg_s_wr_en <= idc_add_cml_2 or idc_adc_cml_2 or adiw_st_cml_2 or idc_sub_cml_2 or idc_subi_cml_2 or
2582 
                idc_sbc_cml_2 or idc_sbci_cml_2 or sbiw_st_cml_2 or
2583 
                                idc_cp_cml_2 or idc_cpc_cml_2 or idc_cpi_cml_2 or
2584 
                                idc_and_cml_2 or idc_andi_cml_2 or idc_or_cml_2 or idc_ori_cml_2 or idc_eor_cml_2 or idc_com_cml_2 or idc_neg_cml_2 or
2585 
                                idc_inc_cml_2 or idc_dec_cml_2 or idc_lsr_cml_2 or idc_ror_cml_2 or idc_asr_cml_2 or sreg_bop_wr_en_cml_2(4);
2586 
 
2587 
-- SynEDA CoreMultiplier
2588 
-- assignment(s): sreg_h_wr_en
2589 
-- replace(s): idc_adc, idc_add, idc_cp, idc_cpc, idc_cpi, idc_neg, idc_sbc, idc_sbci, idc_sub, idc_subi, sreg_bop_wr_en
2590 
 
2591 
sreg_h_wr_en <= idc_add_cml_2 or idc_adc_cml_2 or idc_sub_cml_2  or idc_subi_cml_2 or
2592 
                                idc_cp_cml_2 or idc_cpc_cml_2 or idc_cpi_cml_2 or
2593 
                idc_sbc_cml_2 or idc_sbci_cml_2 or idc_neg_cml_2 or sreg_bop_wr_en_cml_2(5);
2594 
 
2595 
-- SynEDA CoreMultiplier
2596 
-- assignment(s): sreg_t_wr_en
2597 
-- replace(s): sreg_bop_wr_en
2598 
 
2599 
sreg_t_wr_en <=  idc_bst or sreg_bop_wr_en_cml_2(6);
2600 
 
2601 
-- SynEDA CoreMultiplier
2602 
-- assignment(s): sreg_i_wr_en
2603 
-- replace(s): irq_st1, reti_st3, sreg_bop_wr_en
2604 
 
2605 
sreg_i_wr_en <= irq_st1_cml_2 or reti_st3_cml_2 or sreg_bop_wr_en_cml_2(7); -- WAS "irq_start"
2606 
 
2607 
-- SynEDA CoreMultiplier
2608 
-- assignment(s): sreg_fl_in
2609 
-- replace(s): reti_st3, idc_bclr, idc_bset
2610 
 
2611 
sreg_fl_in_cml_out <=  bit_pr_sreg_out when (idc_bst or idc_bclr_cml_2 or idc_bset_cml_2)='1' else                         -- TO THE SREG
2612 
reti_st3_cml_2&'0'&alu_h_flag_out&alu_s_flag_out&alu_v_flag_out&alu_n_flag_out&alu_z_flag_out&alu_c_flag_out;
2613 
 
2614 
-- #################################################################################################################
2615 
 
2616 
-- *********************************************************************************************
2617 
-- ************** INSTRUCTION DECODER OUTPUTS FOR THE OTHER BLOCKS  ****************************
2618 
-- *********************************************************************************************
2619 
 
2620 
-- FOR ALU
2621 
 
2622 
idc_add_out   <= idc_add;
2623 
idc_adc_out   <= idc_adc;
2624 
-- SynEDA CoreMultiplier
2625 
-- assignment(s): idc_adiw_out
2626 
-- replace(s): idc_adiw
2627 
 
2628 
idc_adiw_out_cml_out  <= idc_adiw_cml_1;
2629 
idc_sub_out   <= idc_sub;
2630 
idc_subi_out  <= idc_subi;
2631 
idc_sbc_out   <= idc_sbc;
2632 
idc_sbci_out  <= idc_sbci;
2633 
idc_sbiw_out  <= idc_sbiw;
2634 
adiw_st_out   <= adiw_st;
2635 
sbiw_st_out   <= sbiw_st;
2636 
idc_and_out   <= idc_and;
2637 
-- SynEDA CoreMultiplier
2638 
-- assignment(s): idc_andi_out
2639 
-- replace(s): idc_andi
2640 
 
2641 
idc_andi_out_cml_out  <= idc_andi_cml_1;
2642 
idc_or_out    <= idc_or;
2643 
-- SynEDA CoreMultiplier
2644 
-- assignment(s): idc_ori_out
2645 
-- replace(s): idc_ori
2646 
 
2647 
idc_ori_out_cml_out   <= idc_ori_cml_1;
2648 
idc_eor_out   <= idc_eor;
2649 
idc_com_out   <= idc_com;
2650 
idc_neg_out   <= idc_neg;
2651 
idc_inc_out   <= idc_inc;
2652 
idc_dec_out   <= idc_dec;
2653 
idc_cp_out    <= idc_cp;
2654 
idc_cpc_out   <= idc_cpc;
2655 
idc_cpi_out   <= idc_cpi;
2656 
idc_cpse_out  <= idc_cpse;
2657 
idc_lsr_out   <= idc_lsr;
2658 
idc_ror_out   <= idc_ror;
2659 
idc_asr_out   <= idc_asr;
2660 
idc_swap_out  <= idc_swap;
2661 
 
2662 
-- FOR THE BIT PROCESSOR
2663 
sbi_st_out   <= sbi_st;
2664 
cbi_st_out   <= cbi_st;
2665 
idc_bst_out  <= idc_bst;
2666 
-- SynEDA CoreMultiplier
2667 
-- assignment(s): idc_bset_out
2668 
-- replace(s): idc_bset
2669 
 
2670 
idc_bset_out_cml_out <= idc_bset_cml_2;
2671 
-- SynEDA CoreMultiplier
2672 
-- assignment(s): idc_bclr_out
2673 
-- replace(s): idc_bclr
2674 
 
2675 
idc_bclr_out_cml_out <= idc_bclr_cml_2;
2676 
-- SynEDA CoreMultiplier
2677 
-- assignment(s): idc_sbic_out
2678 
-- replace(s): idc_sbic
2679 
 
2680 
idc_sbic_out_cml_out <= idc_sbic_cml_1;
2681 
-- SynEDA CoreMultiplier
2682 
-- assignment(s): idc_sbis_out
2683 
-- replace(s): idc_sbis
2684 
 
2685 
idc_sbis_out_cml_out <= idc_sbis_cml_1;
2686 
idc_sbrs_out <= idc_sbrs;
2687 
idc_sbrc_out <= idc_sbrc;
2688 
idc_brbs_out <= idc_brbs;
2689 
idc_brbc_out <= idc_brbc;
2690 
-- SynEDA CoreMultiplier
2691 
-- assignment(s): idc_reti_out
2692 
-- replace(s): idc_reti
2693 
 
2694 
idc_reti_out_cml_out <= idc_reti_cml_2;
2695 
 
2696 
-- POST INCREMENT/PRE DECREMENT FOR THE X,Y,Z REGISTERS
2697 
post_inc <= idc_psinc;
2698 
-- SynEDA CoreMultiplier
2699 
-- assignment(s): pre_dec
2700 
-- replace(s): idc_prdec
2701 
 
2702 
pre_dec_cml_out  <= idc_prdec_cml_2;
2703 
-- SynEDA CoreMultiplier
2704 
-- assignment(s): reg_h_wr
2705 
-- replace(s): idc_ld_x, idc_ld_y, idc_ld_z, idc_st_x, idc_st_y, idc_st_z, idc_prdec
2706 
 
2707 
reg_h_wr_cml_out <= (idc_st_x_cml_2 or idc_st_y_cml_2 or idc_st_z_cml_2 or idc_ld_x_cml_2 or idc_ld_y_cml_2 or idc_ld_z_cml_2) and (idc_psinc or idc_prdec_cml_2);
2708 
 
2709 
reg_h_adr_cml_out(0)<= idc_st_x_cml_1 or idc_ld_x;
2710 
reg_h_adr_cml_out(1)<= idc_st_y_cml_1 or idc_std_y_cml_1 or idc_ld_y or idc_ldd_y;
2711 
-- SynEDA CoreMultiplier
2712 
-- assignment(s): reg_h_adr
2713 
-- replace(s): idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
2714 
 
2715 
reg_h_adr_cml_out(2)<= idc_st_z_cml_1 or idc_std_z_cml_1 or idc_ld_z or idc_ldd_z;
2716 
 
2717 
-- SynEDA CoreMultiplier
2718 
-- assignment(s): sp_en
2719 
-- replace(s): cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti
2720 
 
2721 
-- SynEDA CoreMultiplier
2722 
-- assignment(s): sp_ndown_up
2723 
-- replace(s): cpuwait, ret_st1, reti_st1, idc_pop, idc_ret, idc_reti
2724 
 
2725 
-- STACK POINTER CONTROL
2726 
sp_ndown_up_cml_out <= idc_pop_cml_2 or idc_ret_cml_2 or (ret_st1_cml_2 and not cpuwait_cml_2) or idc_reti_cml_2 or (reti_st1_cml_2 and not cpuwait_cml_2); -- ?????????
2727 
sp_en_cml_out <= idc_push_cml_2 or idc_pop_cml_2 or idc_rcall_cml_2 or (rcall_st1_cml_2 and not cpuwait_cml_2) or idc_icall_cml_2 or (icall_st1_cml_2 and not cpuwait_cml_2) or
2728 
idc_ret_cml_2 or (ret_st1_cml_2 and not cpuwait_cml_2) or idc_reti_cml_2 or (reti_st1_cml_2 and not cpuwait_cml_2) or
2729 
call_st1_cml_2 or (call_st2_cml_2 and not cpuwait_cml_2) or irq_st1_cml_2 or (irq_st2_cml_2 and not cpuwait_cml_2); --????????
2730 
 
2731 
 
2732 
branch  <= dex_condition;
2733 
bit_num_r_io <= cbi_sbi_bit_num_tmp when (cbi_st or sbi_st)='1' else dex_bitop_bitnum;
2734 
 
2735 
adr <= adr_int;
2736 
 
2737 
ramre <= ramre_int;
2738 
ramwe <= ramwe_int;
2739 
 
2740 
iore <= iore_int;
2741 
-- SynEDA CoreMultiplier
2742 
-- assignment(s): iowe
2743 
-- replace(s): iowe_int
2744 
 
2745 
iowe_cml_out <= iowe_int_cml_2;
2746 
 
2747 
--dbusout <= dbusout_int;
2748 
 
2749 
-- Sleep Control
2750 
sleepi <= idc_sleep;
2751 
irqok  <= irq_int;
2752 
 
2753 
-- Watchdog
2754 
wdri <= idc_wdr;
2755 
 
2756 
-- ************************** JTAG OCD support ************************************
2757 
 
2758 
-- Change of flow
2759 
change_flow <= '0';
2760 
valid_instr <= '0';
2761 
 
2762 
 
2763 
end RTL;

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