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[/] [avr_hp/] [trunk/] [rtl/] [rtl_v5_cm2/] [pm_fetch_dec.vhd] - Blame information for rev 2

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1 2 tobil 
--************************************************************************************************
2 
--  PM_FETCH_DEC(internal module) for AVR core
3 
--      Version 2.6! (Special version for the JTAG OCD)
4 
--  Designed by Ruslan Lepetenok 14.11.2001
5 
--  Modified 31.05.06
6 
--  Modification:
7 
--  Registered ramre/ramwe outputs
8 
--  cpu_busy logic modified(affects RCALL/ICALL/CALL instruction interract with interrupt)
9 
--  SLEEP and CLRWDT instructions support was added
10 
--  V-flag bug fixed (AND/ANDI/OR/ORI/EOR)
11 
--  V-flag bug fixed (ADIW/SBIW)
12 
--  Unused outputs(sreg_bit_num[2..0],idc_sbi_out,idc_cbi_out,idc_bld_out) were removed.
13 
--  Output alu_data_d_in[7..0] was removed.
14 
--  Gloabal clock enable(cp2en) was added
15 
--  cpu_busy(push/pop) + irq bug was fixed 14.07.05
16 
--  BRXX+IRQ interaction was modified -> cpu_busy
17 
--  LDS/STS now requires only two cycles for execution (13.01.06 -> last modificatioon)
18 
--************************************************************************************************
19 
 
20 
library IEEE;
21 
use IEEE.std_logic_1164.all;
22 
use IEEE.std_logic_unsigned.all;
23 
 
24 
use WORK.AVRuCPackage.all;
25 
 
26 
entity pm_fetch_dec_cm2 is port(
27 
                cp2_cml_1 : in std_logic;
28 
 
29 
                              -- Clock and reset
30 
                              cp2              : in  std_logic;
31 
                                                          cp2en            : in  std_logic;
32 
                              ireset           : in  std_logic;
33 
                                                          -- JTAG OCD support
34 
                                                          valid_instr      : out  std_logic;
35 
                                                      insert_nop       : in   std_logic;
36 
                                                      block_irq        : in   std_logic;
37 
                                                      change_flow      : out  std_logic;
38 
                                                          -- Program memory
39 
                              pc               : out std_logic_vector (15 downto 0);
40 
                              inst             : in  std_logic_vector (15 downto 0);
41 
                              -- I/O control
42 
                              adr              : out std_logic_vector (5 downto 0);
43 
                              iore             : out std_logic;
44 
                              iowe             : out std_logic;
45 
                              -- Data memory control
46 
                              ramadr           : out std_logic_vector (15 downto 0);
47 
                              ramre            : out std_logic;
48 
                              ramwe            : out std_logic;
49 
                              cpuwait          : in  std_logic;
50 
                                                          -- Data paths
51 
                              dbusin           : in  std_logic_vector (7 downto 0);
52 
                              dbusout          : out std_logic_vector (7 downto 0);
53 
                              dbusout_int_route : out std_logic_vector (7 downto 0);
54 
                              -- Interrupt
55 
                              irqlines         : in  std_logic_vector (22 downto 0);
56 
                              irqack           : out std_logic;
57 
                              irqackad         : out std_logic_vector(4 downto 0);
58 
                                                      --Sleep
59 
                              sleepi           : out std_logic;
60 
                              irqok                : out std_logic;
61 
                              --Watchdog
62 
                              wdri                 : out std_logic;
63 
                                                          -- ALU interface(Data inputs)
64 
                              alu_data_r_in    : out std_logic_vector(7 downto 0);
65 
                                                          -- ALU interface(Instruction inputs)
66 
                                                          idc_add_out      : out std_logic;
67 
                              idc_adc_out      : out std_logic;
68 
                              idc_adiw_out     : out std_logic;
69 
                              idc_sub_out      : out std_logic;
70 
                              idc_subi_out     : out std_logic;
71 
                              idc_sbc_out      : out std_logic;
72 
                              idc_sbci_out     : out std_logic;
73 
                              idc_sbiw_out     : out std_logic;
74 
 
75 
                              adiw_st_out      : out std_logic;
76 
                              sbiw_st_out      : out std_logic;
77 
 
78 
                              idc_and_out      : out std_logic;
79 
                              idc_andi_out     : out std_logic;
80 
                              idc_or_out       : out std_logic;
81 
                              idc_ori_out      : out std_logic;
82 
                              idc_eor_out      : out std_logic;
83 
                              idc_com_out      : out std_logic;
84 
                              idc_neg_out      : out std_logic;
85 
 
86 
                              idc_inc_out      : out std_logic;
87 
                              idc_dec_out      : out std_logic;
88 
 
89 
                              idc_cp_out       : out std_logic;
90 
                              idc_cpc_out      : out std_logic;
91 
                              idc_cpi_out      : out std_logic;
92 
                              idc_cpse_out     : out std_logic;
93 
 
94 
                              idc_lsr_out      : out std_logic;
95 
                              idc_ror_out      : out std_logic;
96 
                              idc_asr_out      : out std_logic;
97 
                              idc_swap_out     : out std_logic;
98 
 
99 
                               -- ALU interface(Data output)
100 
                               alu_data_out    : in std_logic_vector(7 downto 0);
101 
 
102 
                               -- ALU interface(Flag outputs)
103 
                               alu_c_flag_out  : in std_logic;
104 
                               alu_z_flag_out  : in std_logic;
105 
                               alu_n_flag_out  : in std_logic;
106 
                               alu_v_flag_out  : in std_logic;
107 
                               alu_s_flag_out  : in std_logic;
108 
                               alu_h_flag_out  : in std_logic;
109 
 
110 
                                                           -- General purpose register file interface
111 
                               reg_rd_in       : out std_logic_vector  (7 downto 0);
112 
                               reg_rd_out      : in  std_logic_vector  (7 downto 0);
113 
                               reg_rd_out_int  : in std_logic_vector(7 downto 0);
114 
                               reg_rd_adr      : out std_logic_vector  (4 downto 0);
115 
                               reg_rd_adr_int      : out std_logic_vector  (4 downto 0);
116 
                               reg_rr_out      : in  std_logic_vector  (7 downto 0);
117 
                               reg_rr_adr      : out std_logic_vector  (4 downto 0);
118 
                               reg_rd_wr       : out std_logic;
119 
 
120 
                               post_inc        : out std_logic;                       -- POST INCREMENT FOR LD/ST INSTRUCTIONS
121 
                               pre_dec         : out std_logic;                        -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
122 
                               reg_h_wr        : out std_logic;
123 
                               reg_h_out       : in  std_logic_vector (15 downto 0);
124 
                               reg_h_adr       : out std_logic_vector (2 downto 0);    -- x,y,z
125 
                                       reg_z_out       : in  std_logic_vector (15 downto 0);  -- OUTPUT OF R31:R30 FOR LPM/ELPM/IJMP INSTRUCTIONS
126 
 
127 
                               -- I/O register file interface
128 
                               sreg_fl_in      : out std_logic_vector(7 downto 0);
129 
                               globint         : in  std_logic; -- SREG I flag
130 
 
131 
                               sreg_fl_wr_en   : out std_logic_vector(7 downto 0);   --FLAGS WRITE ENABLE SIGNALS
132 
 
133 
                               spl_out         : in  std_logic_vector(7 downto 0);
134 
                               sph_out         : in  std_logic_vector(7 downto 0);
135 
                               sp_ndown_up     : out std_logic; -- DIRECTION OF CHANGING OF STACK POINTER SPH:SPL 0->UP(+) 1->DOWN(-)
136 
                               sp_en           : out std_logic; -- WRITE ENABLE(COUNT ENABLE) FOR SPH AND SPL REGISTERS
137 
 
138 
                               rampz_out       : in  std_logic_vector(7 downto 0);
139 
 
140 
                                                           -- Bit processor interface
141 
                               bit_num_r_io    : out std_logic_vector (2 downto 0); -- BIT NUMBER FOR CBI/SBI/BLD/BST/SBRS/SBRC/SBIC/SBIS INSTRUCTIONS
142 
                               bitpr_io_out    : in  std_logic_vector(7 downto 0);  -- SBI/CBI OUT
143 
                               branch          : out std_logic_vector (2 downto 0); -- NUMBER (0..7) OF BRANCH CONDITION FOR BRBS/BRBC INSTRUCTION
144 
                               bit_pr_sreg_out : in  std_logic_vector(7 downto 0);  -- BCLR/BSET/BST(T-FLAG ONLY)
145 
                               bld_op_out      : in  std_logic_vector(7 downto 0);  -- BLD OUT (T FLAG)
146 
                               bit_test_op_out : in  std_logic;                     -- OUTPUT OF SBIC/SBIS/SBRS/SBRC
147 
 
148 
                               sbi_st_out      : out std_logic;
149 
                               cbi_st_out      : out std_logic;
150 
 
151 
                               idc_bst_out     : out std_logic;
152 
                               idc_bset_out    : out std_logic;
153 
                               idc_bclr_out    : out std_logic;
154 
 
155 
                               idc_sbic_out    : out std_logic;
156 
                               idc_sbis_out    : out std_logic;
157 
 
158 
                               idc_sbrs_out    : out std_logic;
159 
                               idc_sbrc_out    : out std_logic;
160 
 
161 
                               idc_brbs_out    : out std_logic;
162 
                               idc_brbc_out    : out std_logic;
163 
 
164 
                               idc_reti_out    : out std_logic);
165 
end pm_fetch_dec_cm2;
166 
 
167 
architecture RTL of pm_fetch_dec_cm2 is
168 
 
169 
-- COPIES OF OUTPUTS
170 
signal ramadr_reg_in  : std_logic_vector(15 downto 0); -- INPUT OF THE ADDRESS REGISTER
171 
signal ramadr_reg_en  : std_logic;                     -- ADRESS REGISTER CLOCK ENABLE SIGNAL
172 
 
173 
signal irqack_int     : std_logic;
174 
signal irqackad_int   : std_logic_vector(irqackad'range);
175 
 
176 
-- ####################################################
177 
-- INTERNAL SIGNALS
178 
-- ####################################################
179 
 
180 
-- NEW SIGNALS
181 
signal   two_word_inst       : std_logic;                    -- CALL/JMP/STS/LDS INSTRUCTION INDICATOR
182 
 
183 
signal   ram_adr_int         : std_logic_vector (15 downto 0);
184 
constant const_ram_to_reg    : std_logic_vector := "00000000000";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL PURPOSE REGISTER (R0-R31) 0x00..0x19
185 
constant const_ram_to_io_a   : std_logic_vector := "00000000001";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
186 
constant const_ram_to_io_b   : std_logic_vector := "00000000010";  -- LD/LDS/LDD/ST/STS/STD ADDRESSING GENERAL I/O PORT 0x20 0x3F
187 
 
188 
-- LD/LDD/ST/STD SIGNALS
189 
signal adiw_sbiw_encoder_out : std_logic_vector (4 downto 0);
190 
signal adiw_sbiw_encoder_mux_out : std_logic_vector (4 downto 0);
191 
 
192 
 
193 
-- PROGRAM COUNTER SIGNALS
194 
signal program_counter_tmp : std_logic_vector (15 downto 0); -- TO STORE PC DURING LPM/ELPM INSTRUCTIONS
195 
signal program_counter     : std_logic_vector (15 downto 0);
196 
signal program_counter_in  : std_logic_vector (15 downto 0);
197 
signal program_counter_high_fr  : std_logic_vector (7 downto 0); -- TO STORE PC FOR CALL,IRQ,RCALL,ICALL
198 
 
199 
signal pc_low       : std_logic_vector (7 downto 0);
200 
signal pc_high      : std_logic_vector (7 downto 0);
201 
 
202 
 
203 
signal pc_low_en       : std_logic;
204 
signal pc_high_en      : std_logic;
205 
 
206 
signal offset_brbx     : std_logic_vector (15 downto 0);    -- OFFSET FOR BRCS/BRCC   INSTRUCTION  !!CHECKED
207 
signal offset_rxx      : std_logic_vector (15 downto 0);    -- OFFSET FOR RJMP/RCALL  INSTRUCTION  !!CHECKED
208 
 
209 
signal pa15_pm         : std_logic; -- ADDRESS LINE 15 FOR LPM/ELPM INSTRUCTIONS ('0' FOR LPM,RAMPZ(0) FOR ELPM)
210 
 
211 
signal alu_reg_wr      : std_logic; -- ALU INSTRUCTIONS PRODUCING WRITE TO THE GENERAL PURPOSE REGISTER FILE
212 
 
213 
-- DATA MEMORY,GENERAL PURPOSE REGISTERS AND I/O REGISTERS LOGIC
214 
 
215 
--! IMPORTANT NOTICE : OPERATIONS WHICH USE STACK POINTER (SPH:SPL) CAN NOT ACCCSESS GENERAL
216 
-- PURPOSE REGISTER FILE AND INPUT/OUTPUT REGISTER FILE !
217 
-- THESE OPERATIONS ARE : RCALL/ICALL/CALL/RET/RETI/PUSH/POP INSTRUCTIONS  AND INTERRUPT
218 
 
219 
signal reg_file_adr_space  : std_logic; -- ACCSESS TO THE REGISTER FILE
220 
signal io_file_adr_space   : std_logic; -- ACCSESS TO THE I/O FILE
221 
 
222 
-- STATE MACHINES SIGNALS
223 
signal irq_start      : std_logic;
224 
 
225 
signal nirq_st0       : std_logic;
226 
signal irq_st1        : std_logic;
227 
signal irq_st2        : std_logic;
228 
signal irq_st3        : std_logic;
229 
 
230 
signal ncall_st0      : std_logic;
231 
signal call_st1       : std_logic;
232 
signal call_st2       : std_logic;
233 
signal call_st3       : std_logic;
234 
 
235 
signal nrcall_st0     : std_logic;
236 
signal rcall_st1      : std_logic;
237 
signal rcall_st2      : std_logic;
238 
 
239 
signal nicall_st0     : std_logic;
240 
signal icall_st1      : std_logic;
241 
signal icall_st2      : std_logic;
242 
 
243 
signal njmp_st0       : std_logic;
244 
signal jmp_st1        : std_logic;
245 
signal jmp_st2        : std_logic;
246 
 
247 
signal ijmp_st        : std_logic;
248 
 
249 
signal rjmp_st        : std_logic;
250 
 
251 
signal nret_st0       : std_logic;
252 
signal ret_st1        : std_logic;
253 
signal ret_st2        : std_logic;
254 
signal ret_st3        : std_logic;
255 
 
256 
signal nreti_st0      : std_logic;
257 
signal reti_st1       : std_logic;
258 
signal reti_st2       : std_logic;
259 
signal reti_st3       : std_logic;
260 
 
261 
signal brxx_st        : std_logic;  -- BRANCHES
262 
 
263 
signal adiw_st        : std_logic;
264 
signal sbiw_st        : std_logic;
265 
 
266 
signal nskip_inst_st0 : std_logic;
267 
signal skip_inst_st1  : std_logic;
268 
signal skip_inst_st2  : std_logic;  -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE
269 
 
270 
signal skip_inst_start  : std_logic;
271 
 
272 
signal nlpm_st0       : std_logic;
273 
signal lpm_st1        : std_logic;
274 
signal lpm_st2        : std_logic;
275 
 
276 
signal nelpm_st0      : std_logic;
277 
signal elpm_st1       : std_logic;
278 
signal elpm_st2       : std_logic;
279 
 
280 
--signal nsts_st0       : std_logic;
281 
--signal sts_st1        : std_logic;
282 
--signal sts_st2        : std_logic;
283 
 
284 
signal sts_st         : std_logic;
285 
 
286 
--signal nlds_st0       : std_logic;
287 
--signal lds_st1        : std_logic;
288 
--signal lds_st2        : std_logic;
289 
 
290 
signal lds_st           : std_logic;
291 
 
292 
signal st_st          : std_logic;
293 
signal ld_st          : std_logic;
294 
 
295 
signal sbi_st         : std_logic;
296 
signal cbi_st         : std_logic;
297 
 
298 
signal push_st        : std_logic;
299 
signal pop_st         : std_logic;
300 
 
301 
-- INTERNAL STATE MACHINES
302 
signal nop_insert_st  : std_logic;
303 
signal cpu_busy       : std_logic;
304 
 
305 
-- INTERNAL COPIES OF OUTPUTS
306 
signal pc_int              : std_logic_vector (15 downto 0);
307 
signal adr_int             : std_logic_vector (5 downto 0);
308 
signal iore_int                    : std_logic;
309 
signal iowe_int            : std_logic;
310 
signal ramadr_int          : std_logic_vector (15 downto 0);
311 
signal ramre_int           : std_logic;
312 
signal ramwe_int           : std_logic;
313 
signal dbusout_int         : std_logic_vector (7 downto 0);
314 
 
315 
-- COMMAND REGISTER
316 
signal instruction_reg      : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER
317 
signal instruction_code_reg : std_logic_vector (15 downto 0); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTION
318 
signal instruction_reg_ena  : std_logic;                               -- CLOCK ENABLE
319 
 
320 
 
321 
-- IRQ INTERNAL LOGIC
322 
signal irq_int              : std_logic;
323 
signal irq_vector_adr       : std_logic_vector(15 downto 0);
324 
 
325 
-- INTERRUPT RELATING REGISTERS
326 
signal pc_for_interrupt : std_logic_vector(15 downto 0);
327 
 
328 
-- DATA EXTRACTOR SIGNALS
329 
signal dex_dat8_immed  : std_logic_vector (7 downto 0);  -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDI
330 
signal dex_dat6_immed  : std_logic_vector (5 downto 0);  -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIW
331 
signal dex_adr12mem_s  : std_logic_vector (11 downto 0); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMP
332 
signal dex_adr6port    : std_logic_vector (5 downto 0);  -- I/O PORT ADDRESS -> IN,OUT
333 
signal dex_adr5port    : std_logic_vector (4 downto 0);  -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBIS
334 
signal dex_adr_disp    : std_logic_vector (5 downto 0);  -- DISPLACEMENT FO ADDDRESS -> STD,LDD
335 
signal dex_condition   : std_logic_vector (2 downto 0);  -- CONDITION -> BRBC,BRBS
336 
signal dex_bitnum_sreg : std_logic_vector (2 downto 0);  -- NUMBER OF BIT IN SREG -> BCLR,BSET
337 
signal dex_adrreg_r    : std_logic_vector (4 downto 0);  -- SOURCE REGISTER ADDRESS -> .......
338 
signal dex_adrreg_d    : std_logic_vector (4 downto 0);  -- DESTINATION REGISTER ADDRESS -> ......
339 
signal dex_bitop_bitnum : std_logic_vector(2 downto 0);  -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKED
340 
signal dex_brxx_offset : std_logic_vector (6 downto 0);  -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKED
341 
signal dex_adiw_sbiw_reg_adr  : std_logic_vector (1 downto 0);  -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
342 
 
343 
signal dex_adrreg_d_latched : std_logic_vector (4 downto 0);   --  STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONS
344 
signal gp_reg_tmp           : std_logic_vector (7 downto 0);   --  STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONS
345 
signal cbi_sbi_io_adr_tmp   : std_logic_vector (4 downto 0);   --  STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
346 
signal cbi_sbi_bit_num_tmp  : std_logic_vector (2 downto 0);   --  STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION
347 
 
348 
-- INSTRUCTIONS DECODER SIGNALS
349 
 
350 
signal idc_adc     : std_logic; -- INSTRUCTION ADC
351 
signal idc_add     : std_logic; -- INSTRUCTION ADD
352 
signal idc_adiw    : std_logic; -- INSTRUCTION ADIW
353 
signal idc_and     : std_logic; -- INSTRUCTION AND
354 
signal idc_andi    : std_logic; -- INSTRUCTION ANDI
355 
signal idc_asr     : std_logic; -- INSTRUCTION ASR
356 
 
357 
signal idc_bclr    : std_logic; -- INSTRUCTION BCLR
358 
signal idc_bld     : std_logic; -- INSTRUCTION BLD
359 
signal idc_brbc    : std_logic; -- INSTRUCTION BRBC
360 
signal idc_brbs    : std_logic; -- INSTRUCTION BRBS
361 
signal idc_bset    : std_logic; -- INSTRUCTION BSET
362 
signal idc_bst     : std_logic; -- INSTRUCTION BST
363 
 
364 
signal idc_call    : std_logic; -- INSTRUCTION CALL
365 
signal idc_cbi     : std_logic; -- INSTRUCTION CBI
366 
signal idc_com     : std_logic; -- INSTRUCTION COM
367 
signal idc_cp      : std_logic; -- INSTRUCTION CP
368 
signal idc_cpc     : std_logic; -- INSTRUCTION CPC
369 
signal idc_cpi     : std_logic; -- INSTRUCTION CPI
370 
signal idc_cpse    : std_logic; -- INSTRUCTION CPSE
371 
 
372 
signal idc_dec     : std_logic; -- INSTRUCTION DEC
373 
 
374 
signal idc_elpm    : std_logic; -- INSTRUCTION ELPM
375 
signal idc_eor     : std_logic; -- INSTRUCTION EOR
376 
 
377 
signal idc_icall   : std_logic; -- INSTRUCTION ICALL
378 
signal idc_ijmp    : std_logic; -- INSTRUCTION IJMP
379 
 
380 
signal idc_in      : std_logic; -- INSTRUCTION IN
381 
signal idc_inc     : std_logic; -- INSTRUCTION INC
382 
 
383 
signal idc_jmp     : std_logic; -- INSTRUCTION JMP
384 
 
385 
signal idc_ld_x    : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-X
386 
signal idc_ld_y    : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Y
387 
signal idc_ldd_y   : std_logic; -- INSTRUCTION LDD Rx,Y+q
388 
signal idc_ld_z    : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Z
389 
signal idc_ldd_z   : std_logic; -- INSTRUCTION LDD Rx,Z+q
390 
 
391 
signal idc_ldi     : std_logic; -- INSTRUCTION LDI
392 
signal idc_lds     : std_logic; -- INSTRUCTION LDS
393 
signal idc_lpm     : std_logic; -- INSTRUCTION LPM
394 
signal idc_lsr     : std_logic; -- INSTRUCTION LSR
395 
 
396 
signal idc_mov     : std_logic; -- INSTRUCTION MOV
397 
signal idc_mul     : std_logic; -- INSTRUCTION MUL
398 
 
399 
signal idc_neg     : std_logic; -- INSTRUCTION NEG
400 
signal idc_nop     : std_logic; -- INSTRUCTION NOP
401 
 
402 
signal idc_or      : std_logic; -- INSTRUCTION OR
403 
signal idc_ori     : std_logic; -- INSTRUCTION ORI
404 
signal idc_out     : std_logic; -- INSTRUCTION OUT
405 
 
406 
signal idc_pop     : std_logic; -- INSTRUCTION POP
407 
signal idc_push    : std_logic; -- INSTRUCTION PUSH
408 
 
409 
signal idc_rcall   : std_logic; -- INSTRUCTION RCALL
410 
signal idc_ret     : std_logic; -- INSTRUCTION RET
411 
signal idc_reti    : std_logic; -- INSTRUCTION RETI
412 
signal idc_rjmp    : std_logic; -- INSTRUCTION RJMP
413 
signal idc_ror     : std_logic; -- INSTRUCTION ROR
414 
 
415 
signal idc_sbc     : std_logic; -- INSTRUCTION SBC
416 
signal idc_sbci    : std_logic; -- INSTRUCTION SBCI
417 
signal idc_sbi     : std_logic; -- INSTRUCTION SBI
418 
signal idc_sbic    : std_logic; -- INSTRUCTION SBIC
419 
signal idc_sbis    : std_logic; -- INSTRUCTION SBIS
420 
signal idc_sbiw    : std_logic; -- INSTRUCTION SBIW
421 
signal idc_sbrc    : std_logic; -- INSTRUCTION SBRC
422 
signal idc_sbrs    : std_logic; -- INSTRUCTION SBRS
423 
signal idc_sleep   : std_logic; -- INSTRUCTION SLEEP
424 
 
425 
signal idc_st_x    : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rx
426 
signal idc_st_y    : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rx
427 
signal idc_std_y   : std_logic; -- INSTRUCTION LDD Y+q,Rx
428 
signal idc_st_z    : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rx
429 
signal idc_std_z   : std_logic; -- INSTRUCTION LDD Z+q,Rx
430 
 
431 
signal idc_sts     : std_logic; -- INSTRUCTION STS
432 
signal idc_sub     : std_logic; -- INSTRUCTION SUB
433 
signal idc_subi    : std_logic; -- INSTRUCTION SUBI
434 
signal idc_swap    : std_logic; -- INSTRUCTION SWAP
435 
 
436 
signal idc_wdr     : std_logic; -- INSTRUCTION WDR
437 
 
438 
-- ADDITIONAL SIGNALS
439 
signal idc_psinc   :  std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONS
440 
signal idc_prdec   :  std_logic; -- PRE DECREMENT  FLAG FOR LD,ST INSTRUCTIONS
441 
 
442 
-- ##################################################
443 
 
444 
-- SREG FLAGS WRITE ENABLE SIGNALS
445 
 
446 
--alias sreg_c_wr_en  : std_logic is sreg_fl_wr_en(0);
447 
--alias sreg_z_wr_en  : std_logic is sreg_fl_wr_en(1);
448 
--alias sreg_n_wr_en  : std_logic is sreg_fl_wr_en(2);
449 
--alias sreg_v_wr_en  : std_logic is sreg_fl_wr_en(3);
450 
--alias sreg_s_wr_en  : std_logic is sreg_fl_wr_en(4);
451 
--alias sreg_h_wr_en  : std_logic is sreg_fl_wr_en(5);
452 
--alias sreg_t_wr_en  : std_logic is sreg_fl_wr_en(6);
453 
--alias sreg_i_wr_en  : std_logic is sreg_fl_wr_en(7);
454 
 
455 
signal sreg_c_wr_en  : std_logic; --  is sreg_fl_wr_en(0);
456 
signal sreg_z_wr_en  : std_logic; --  is sreg_fl_wr_en(1);
457 
signal sreg_n_wr_en  : std_logic; --  is sreg_fl_wr_en(2);
458 
signal sreg_v_wr_en  : std_logic; --  is sreg_fl_wr_en(3);
459 
signal sreg_s_wr_en  : std_logic; --  is sreg_fl_wr_en(4);
460 
signal sreg_h_wr_en  : std_logic; --  is sreg_fl_wr_en(5);
461 
signal sreg_t_wr_en  : std_logic; --  is sreg_fl_wr_en(6);
462 
signal sreg_i_wr_en  : std_logic; --  is sreg_fl_wr_en(7);
463 
 
464 
signal sreg_bop_wr_en : std_logic_vector (7 downto 0);
465 
 
466 
signal sreg_adr_eq  : std_logic;
467 
-- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
468 
 
469 
signal inst_cml_1 :  std_logic_vector ( 15 downto 0 );
470 
signal sp_ndown_up_cml_out :  std_logic;
471 
signal sp_en_cml_out :  std_logic;
472 
signal cpuwait_cml_1 :  std_logic;
473 
signal irqlines_cml_1 :  std_logic_vector ( 22 downto 0 );
474 
signal reg_rd_out_cml_1 :  std_logic_vector ( 7 downto 0 );
475 
signal reg_rd_in_cml_out :  std_logic_vector ( 7 downto 0 );
476 
signal reg_rr_out_cml_1 :  std_logic_vector ( 7 downto 0 );
477 
signal bitpr_io_out_cml_1 :  std_logic_vector ( 7 downto 0 );
478 
signal irqack_cml_out :  std_logic;
479 
signal irqack_int_cml_1 :  std_logic;
480 
signal irqackad_cml_out :  std_logic_vector ( 4 downto 0 );
481 
signal irqackad_int_cml_1 :  std_logic_vector ( irqackad 'range);
482 
signal adiw_sbiw_encoder_out_cml_1 :  std_logic_vector ( 4 downto 0 );
483 
signal adiw_sbiw_encoder_mux_out_cml_1 :  std_logic_vector ( 4 downto 0 );
484 
signal program_counter_tmp_cml_1 :  std_logic_vector ( 15 downto 0 );
485 
signal program_counter_cml_1 :  std_logic_vector ( 15 downto 0 );
486 
signal program_counter_high_fr_cml_1 :  std_logic_vector ( 7 downto 0 );
487 
signal pc_low_cml_1 :  std_logic_vector ( 7 downto 0 );
488 
signal pc_high_cml_1 :  std_logic_vector ( 7 downto 0 );
489 
signal reg_rd_wr_cml_out :  std_logic;
490 
signal reg_file_adr_space_cml_1 :  std_logic;
491 
signal io_file_adr_space_cml_1 :  std_logic;
492 
signal nirq_st0_cml_1 :  std_logic;
493 
signal irq_st1_cml_1 :  std_logic;
494 
signal irq_st2_cml_1 :  std_logic;
495 
signal irq_st3_cml_1 :  std_logic;
496 
signal ncall_st0_cml_1 :  std_logic;
497 
signal call_st1_cml_1 :  std_logic;
498 
signal call_st2_cml_1 :  std_logic;
499 
signal call_st3_cml_1 :  std_logic;
500 
signal nrcall_st0_cml_1 :  std_logic;
501 
signal rcall_st1_cml_1 :  std_logic;
502 
signal rcall_st2_cml_1 :  std_logic;
503 
signal nicall_st0_cml_1 :  std_logic;
504 
signal icall_st1_cml_1 :  std_logic;
505 
signal icall_st2_cml_1 :  std_logic;
506 
signal njmp_st0_cml_1 :  std_logic;
507 
signal jmp_st1_cml_1 :  std_logic;
508 
signal jmp_st2_cml_1 :  std_logic;
509 
signal ijmp_st_cml_1 :  std_logic;
510 
signal rjmp_st_cml_1 :  std_logic;
511 
signal nret_st0_cml_1 :  std_logic;
512 
signal ret_st1_cml_1 :  std_logic;
513 
signal ret_st2_cml_1 :  std_logic;
514 
signal ret_st3_cml_1 :  std_logic;
515 
signal nreti_st0_cml_1 :  std_logic;
516 
signal reti_st1_cml_1 :  std_logic;
517 
signal reti_st2_cml_1 :  std_logic;
518 
signal sreg_fl_in_cml_out :  std_logic_vector ( 7 downto 0 );
519 
signal reti_st3_cml_1 :  std_logic;
520 
signal brxx_st_cml_1 :  std_logic;
521 
signal adiw_st_cml_1 :  std_logic;
522 
signal sbiw_st_cml_1 :  std_logic;
523 
signal nskip_inst_st0_cml_1 :  std_logic;
524 
signal skip_inst_st1_cml_1 :  std_logic;
525 
signal skip_inst_st2_cml_1 :  std_logic;
526 
signal nlpm_st0_cml_1 :  std_logic;
527 
signal lpm_st1_cml_1 :  std_logic;
528 
signal lpm_st2_cml_1 :  std_logic;
529 
signal sts_st_cml_1 :  std_logic;
530 
signal lds_st_cml_1 :  std_logic;
531 
signal st_st_cml_1 :  std_logic;
532 
signal ld_st_cml_1 :  std_logic;
533 
signal sbi_st_cml_1 :  std_logic;
534 
signal cbi_st_cml_1 :  std_logic;
535 
signal push_st_cml_1 :  std_logic;
536 
signal pop_st_cml_1 :  std_logic;
537 
signal adr_cml_out :  std_logic_vector ( 5 downto 0 );
538 
signal adr_int_cml_1 :  std_logic_vector ( 5 downto 0 );
539 
signal iore_cml_out :  std_logic;
540 
signal iore_int_cml_1 :  std_logic;
541 
signal ramadr_int_cml_1 :  std_logic_vector ( 15 downto 0 );
542 
signal ramre_int_cml_1 :  std_logic;
543 
signal ramwe_int_cml_1 :  std_logic;
544 
signal instruction_reg_cml_1 :  std_logic_vector ( 15 downto 0 );
545 
signal instruction_code_reg_cml_1 :  std_logic_vector ( 15 downto 0 );
546 
signal pc_for_interrupt_cml_1 :  std_logic_vector ( 15 downto 0 );
547 
signal dex_dat8_immed_cml_1 :  std_logic_vector ( 7 downto 0 );
548 
signal dex_adr5port_cml_1 :  std_logic_vector ( 4 downto 0 );
549 
signal dex_adrreg_d_cml_1 :  std_logic_vector ( 4 downto 0 );
550 
signal dex_bitop_bitnum_cml_1 :  std_logic_vector ( 2 downto 0 );
551 
signal dex_adrreg_d_latched_cml_1 :  std_logic_vector ( 4 downto 0 );
552 
signal gp_reg_tmp_cml_1 :  std_logic_vector ( 7 downto 0 );
553 
signal cbi_sbi_io_adr_tmp_cml_1 :  std_logic_vector ( 4 downto 0 );
554 
signal cbi_sbi_bit_num_tmp_cml_1 :  std_logic_vector ( 2 downto 0 );
555 
signal idc_adc_cml_1 :  std_logic;
556 
signal idc_adiw_out_cml_out :  std_logic;
557 
signal idc_adiw_cml_1 :  std_logic;
558 
signal idc_andi_out_cml_out :  std_logic;
559 
signal idc_andi_cml_1 :  std_logic;
560 
signal idc_brbc_out_cml_out :  std_logic;
561 
signal idc_brbc_cml_1 :  std_logic;
562 
signal idc_brbs_out_cml_out :  std_logic;
563 
signal idc_brbs_cml_1 :  std_logic;
564 
signal idc_cbi_cml_1 :  std_logic;
565 
signal idc_cp_cml_1 :  std_logic;
566 
signal idc_cpc_cml_1 :  std_logic;
567 
signal idc_cpi_cml_1 :  std_logic;
568 
signal idc_cpse_cml_1 :  std_logic;
569 
signal idc_elpm_cml_1 :  std_logic;
570 
signal idc_icall_cml_1 :  std_logic;
571 
signal idc_ijmp_cml_1 :  std_logic;
572 
signal idc_in_cml_1 :  std_logic;
573 
signal reg_h_wr_cml_out :  std_logic;
574 
signal reg_h_adr_cml_out :  std_logic_vector ( 2 downto 0 );
575 
signal idc_ld_x_cml_1 :  std_logic;
576 
signal idc_ld_y_cml_1 :  std_logic;
577 
signal idc_ldd_y_cml_1 :  std_logic;
578 
signal idc_ld_z_cml_1 :  std_logic;
579 
signal idc_ldd_z_cml_1 :  std_logic;
580 
signal idc_ldi_cml_1 :  std_logic;
581 
signal idc_lds_cml_1 :  std_logic;
582 
signal idc_lpm_cml_1 :  std_logic;
583 
signal idc_ori_out_cml_out :  std_logic;
584 
signal idc_ori_cml_1 :  std_logic;
585 
signal idc_out_cml_1 :  std_logic;
586 
signal idc_pop_cml_1 :  std_logic;
587 
signal idc_push_cml_1 :  std_logic;
588 
signal idc_rcall_cml_1 :  std_logic;
589 
signal idc_ret_cml_1 :  std_logic;
590 
signal idc_reti_out_cml_out :  std_logic;
591 
signal idc_reti_cml_1 :  std_logic;
592 
signal idc_rjmp_cml_1 :  std_logic;
593 
signal idc_ror_cml_1 :  std_logic;
594 
signal idc_sbc_cml_1 :  std_logic;
595 
signal idc_sbci_cml_1 :  std_logic;
596 
signal idc_sbi_cml_1 :  std_logic;
597 
signal idc_sbic_out_cml_out :  std_logic;
598 
signal idc_sbic_cml_1 :  std_logic;
599 
signal idc_sbis_out_cml_out :  std_logic;
600 
signal idc_sbis_cml_1 :  std_logic;
601 
signal idc_sbiw_cml_1 :  std_logic;
602 
signal idc_sbrc_out_cml_out :  std_logic;
603 
signal idc_sbrc_cml_1 :  std_logic;
604 
signal idc_sbrs_out_cml_out :  std_logic;
605 
signal idc_sbrs_cml_1 :  std_logic;
606 
signal idc_st_x_cml_1 :  std_logic;
607 
signal idc_st_y_cml_1 :  std_logic;
608 
signal idc_std_y_cml_1 :  std_logic;
609 
signal idc_st_z_cml_1 :  std_logic;
610 
signal idc_std_z_cml_1 :  std_logic;
611 
signal idc_sts_cml_1 :  std_logic;
612 
signal idc_sub_cml_1 :  std_logic;
613 
signal idc_subi_cml_1 :  std_logic;
614 
signal pre_dec_cml_out :  std_logic;
615 
signal idc_prdec_cml_1 :  std_logic;
616 
 
617 
begin
618 
 
619 
 
620 
 
621 
process(cp2_cml_1) begin
622 
if (cp2_cml_1 = '1' and cp2_cml_1'event) then
623 
        inst_cml_1 <= inst;
624 
        cpuwait_cml_1 <= cpuwait;
625 
        irqlines_cml_1 <= irqlines;
626 
        reg_rd_out_cml_1 <= reg_rd_out;
627 
        reg_rr_out_cml_1 <= reg_rr_out;
628 
        bitpr_io_out_cml_1 <= bitpr_io_out;
629 
        irqack_int_cml_1 <= irqack_int;
630 
        irqackad_int_cml_1 <= irqackad_int;
631 
        adiw_sbiw_encoder_out_cml_1 <= adiw_sbiw_encoder_out;
632 
        adiw_sbiw_encoder_mux_out_cml_1 <= adiw_sbiw_encoder_mux_out;
633 
        program_counter_tmp_cml_1 <= program_counter_tmp;
634 
        program_counter_cml_1 <= program_counter;
635 
        program_counter_high_fr_cml_1 <= program_counter_high_fr;
636 
        pc_low_cml_1 <= pc_low;
637 
        pc_high_cml_1 <= pc_high;
638 
        reg_file_adr_space_cml_1 <= reg_file_adr_space;
639 
        io_file_adr_space_cml_1 <= io_file_adr_space;
640 
        nirq_st0_cml_1 <= nirq_st0;
641 
        irq_st1_cml_1 <= irq_st1;
642 
        irq_st2_cml_1 <= irq_st2;
643 
        irq_st3_cml_1 <= irq_st3;
644 
        ncall_st0_cml_1 <= ncall_st0;
645 
        call_st1_cml_1 <= call_st1;
646 
        call_st2_cml_1 <= call_st2;
647 
        call_st3_cml_1 <= call_st3;
648 
        nrcall_st0_cml_1 <= nrcall_st0;
649 
        rcall_st1_cml_1 <= rcall_st1;
650 
        rcall_st2_cml_1 <= rcall_st2;
651 
        nicall_st0_cml_1 <= nicall_st0;
652 
        icall_st1_cml_1 <= icall_st1;
653 
        icall_st2_cml_1 <= icall_st2;
654 
        njmp_st0_cml_1 <= njmp_st0;
655 
        jmp_st1_cml_1 <= jmp_st1;
656 
        jmp_st2_cml_1 <= jmp_st2;
657 
        ijmp_st_cml_1 <= ijmp_st;
658 
        rjmp_st_cml_1 <= rjmp_st;
659 
        nret_st0_cml_1 <= nret_st0;
660 
        ret_st1_cml_1 <= ret_st1;
661 
        ret_st2_cml_1 <= ret_st2;
662 
        ret_st3_cml_1 <= ret_st3;
663 
        nreti_st0_cml_1 <= nreti_st0;
664 
        reti_st1_cml_1 <= reti_st1;
665 
        reti_st2_cml_1 <= reti_st2;
666 
        reti_st3_cml_1 <= reti_st3;
667 
        brxx_st_cml_1 <= brxx_st;
668 
        adiw_st_cml_1 <= adiw_st;
669 
        sbiw_st_cml_1 <= sbiw_st;
670 
        nskip_inst_st0_cml_1 <= nskip_inst_st0;
671 
        skip_inst_st1_cml_1 <= skip_inst_st1;
672 
        skip_inst_st2_cml_1 <= skip_inst_st2;
673 
        nlpm_st0_cml_1 <= nlpm_st0;
674 
        lpm_st1_cml_1 <= lpm_st1;
675 
        lpm_st2_cml_1 <= lpm_st2;
676 
        sts_st_cml_1 <= sts_st;
677 
        lds_st_cml_1 <= lds_st;
678 
        st_st_cml_1 <= st_st;
679 
        ld_st_cml_1 <= ld_st;
680 
        sbi_st_cml_1 <= sbi_st;
681 
        cbi_st_cml_1 <= cbi_st;
682 
        push_st_cml_1 <= push_st;
683 
        pop_st_cml_1 <= pop_st;
684 
        adr_int_cml_1 <= adr_int;
685 
        iore_int_cml_1 <= iore_int;
686 
        ramadr_int_cml_1 <= ramadr_int;
687 
        ramre_int_cml_1 <= ramre_int;
688 
        ramwe_int_cml_1 <= ramwe_int;
689 
        instruction_reg_cml_1 <= instruction_reg;
690 
        instruction_code_reg_cml_1 <= instruction_code_reg;
691 
        pc_for_interrupt_cml_1 <= pc_for_interrupt;
692 
        dex_dat8_immed_cml_1 <= dex_dat8_immed;
693 
        dex_adr5port_cml_1 <= dex_adr5port;
694 
        dex_adrreg_d_cml_1 <= dex_adrreg_d;
695 
        dex_bitop_bitnum_cml_1 <= dex_bitop_bitnum;
696 
        dex_adrreg_d_latched_cml_1 <= dex_adrreg_d_latched;
697 
        gp_reg_tmp_cml_1 <= gp_reg_tmp;
698 
        cbi_sbi_io_adr_tmp_cml_1 <= cbi_sbi_io_adr_tmp;
699 
        cbi_sbi_bit_num_tmp_cml_1 <= cbi_sbi_bit_num_tmp;
700 
        idc_adc_cml_1 <= idc_adc;
701 
        idc_adiw_cml_1 <= idc_adiw;
702 
        idc_andi_cml_1 <= idc_andi;
703 
        idc_brbc_cml_1 <= idc_brbc;
704 
        idc_brbs_cml_1 <= idc_brbs;
705 
        idc_cbi_cml_1 <= idc_cbi;
706 
        idc_cp_cml_1 <= idc_cp;
707 
        idc_cpc_cml_1 <= idc_cpc;
708 
        idc_cpi_cml_1 <= idc_cpi;
709 
        idc_cpse_cml_1 <= idc_cpse;
710 
        idc_elpm_cml_1 <= idc_elpm;
711 
        idc_icall_cml_1 <= idc_icall;
712 
        idc_ijmp_cml_1 <= idc_ijmp;
713 
        idc_in_cml_1 <= idc_in;
714 
        idc_ld_x_cml_1 <= idc_ld_x;
715 
        idc_ld_y_cml_1 <= idc_ld_y;
716 
        idc_ldd_y_cml_1 <= idc_ldd_y;
717 
        idc_ld_z_cml_1 <= idc_ld_z;
718 
        idc_ldd_z_cml_1 <= idc_ldd_z;
719 
        idc_ldi_cml_1 <= idc_ldi;
720 
        idc_lds_cml_1 <= idc_lds;
721 
        idc_lpm_cml_1 <= idc_lpm;
722 
        idc_ori_cml_1 <= idc_ori;
723 
        idc_out_cml_1 <= idc_out;
724 
        idc_pop_cml_1 <= idc_pop;
725 
        idc_push_cml_1 <= idc_push;
726 
        idc_rcall_cml_1 <= idc_rcall;
727 
        idc_ret_cml_1 <= idc_ret;
728 
        idc_reti_cml_1 <= idc_reti;
729 
        idc_rjmp_cml_1 <= idc_rjmp;
730 
        idc_ror_cml_1 <= idc_ror;
731 
        idc_sbc_cml_1 <= idc_sbc;
732 
        idc_sbci_cml_1 <= idc_sbci;
733 
        idc_sbi_cml_1 <= idc_sbi;
734 
        idc_sbic_cml_1 <= idc_sbic;
735 
        idc_sbis_cml_1 <= idc_sbis;
736 
        idc_sbiw_cml_1 <= idc_sbiw;
737 
        idc_sbrc_cml_1 <= idc_sbrc;
738 
        idc_sbrs_cml_1 <= idc_sbrs;
739 
        idc_st_x_cml_1 <= idc_st_x;
740 
        idc_st_y_cml_1 <= idc_st_y;
741 
        idc_std_y_cml_1 <= idc_std_y;
742 
        idc_st_z_cml_1 <= idc_st_z;
743 
        idc_std_z_cml_1 <= idc_std_z;
744 
        idc_sts_cml_1 <= idc_sts;
745 
        idc_sub_cml_1 <= idc_sub;
746 
        idc_subi_cml_1 <= idc_subi;
747 
        idc_prdec_cml_1 <= idc_prdec;
748 
end if;
749 
end process;
750 
sp_ndown_up <= sp_ndown_up_cml_out;
751 
sp_en <= sp_en_cml_out;
752 
reg_rd_in <= reg_rd_in_cml_out;
753 
irqack <= irqack_cml_out;
754 
irqackad <= irqackad_cml_out;
755 
reg_rd_wr <= reg_rd_wr_cml_out;
756 
sreg_fl_in <= sreg_fl_in_cml_out;
757 
adr <= adr_cml_out;
758 
iore <= iore_cml_out;
759 
idc_adiw_out <= idc_adiw_out_cml_out;
760 
idc_andi_out <= idc_andi_out_cml_out;
761 
idc_brbc_out <= idc_brbc_out_cml_out;
762 
idc_brbs_out <= idc_brbs_out_cml_out;
763 
reg_h_wr <= reg_h_wr_cml_out;
764 
reg_h_adr <= reg_h_adr_cml_out;
765 
idc_ori_out <= idc_ori_out_cml_out;
766 
idc_reti_out <= idc_reti_out_cml_out;
767 
idc_sbic_out <= idc_sbic_out_cml_out;
768 
idc_sbis_out <= idc_sbis_out_cml_out;
769 
idc_sbrc_out <= idc_sbrc_out_cml_out;
770 
idc_sbrs_out <= idc_sbrs_out_cml_out;
771 
pre_dec <= pre_dec_cml_out;
772 
 
773 
 
774 
sreg_fl_wr_en <= sreg_i_wr_en & sreg_t_wr_en & sreg_h_wr_en & sreg_s_wr_en & sreg_v_wr_en & sreg_n_wr_en & sreg_z_wr_en & sreg_c_wr_en;
775 
 
776 
 
777 
-- INSTRUCTION FETCH
778 
instruction_reg_ena <= '1'; -- FOR TEST
779 
 
780 
-- SynEDA CoreMultiplier
781 
-- assignment(s): instruction_reg
782 
-- replace(s): inst, instruction_reg
783 
 
784 
instruction_fetch:process(cp2,ireset)
785 
begin
786 
if ireset='0' then                              -- RESET
787 
instruction_reg <= (others => '0');
788 
elsif (cp2='1' and cp2'event) then instruction_reg <= instruction_reg_cml_1;            -- CLOCK
789 
 if (cp2en='1') then                                                      -- Clock enable
790 
  if instruction_reg_ena='1' then
791 
   instruction_reg <= inst_cml_1;
792 
  end if;
793 
 end if;
794 
end if;
795 
end process;
796 
 
797 
-- SynEDA CoreMultiplier
798 
-- assignment(s): two_word_inst
799 
-- replace(s): instruction_reg
800 
 
801 
-- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
802 
two_word_inst <= '1' when
803 
((instruction_reg_cml_1(15 downto 9)&instruction_reg_cml_1(3 downto 1)="1001010111") or    -- CALL
804 
 (instruction_reg_cml_1(15 downto 9)&instruction_reg_cml_1(3 downto 1)="1001010110")) or   -- JMP
805 
 (instruction_reg_cml_1(15 downto 9)&instruction_reg_cml_1(3 downto 0) = "10010000000") or -- LDS
806 
 (instruction_reg_cml_1(15 downto 9)&instruction_reg_cml_1(3 downto 0) = "10010010000")    -- STS
807 
   else '0';  -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE
808 
 
809 
 
810 
 
811 
-- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)
812 
dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0);
813 
dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0);
814 
-- SynEDA CoreMultiplier
815 
-- assignment(s): dex_adr12mem_s
816 
-- replace(s): instruction_reg
817 
 
818 
dex_adr12mem_s <= instruction_reg_cml_1(11 downto 0);
819 
dex_adr6port <= instruction_reg(10 downto 9) & instruction_reg(3 downto 0);
820 
dex_adr5port <= instruction_reg(7 downto 3);
821 
-- SynEDA CoreMultiplier
822 
-- assignment(s): dex_adr_disp
823 
-- replace(s): instruction_reg
824 
 
825 
dex_adr_disp <= instruction_reg_cml_1(13) & instruction_reg_cml_1(11 downto 10) & instruction_reg_cml_1(2 downto 0);
826 
-- SynEDA CoreMultiplier
827 
-- assignment(s): dex_condition
828 
-- replace(s): instruction_reg
829 
 
830 
dex_condition <= instruction_reg_cml_1(2 downto 0);
831 
-- SynEDA CoreMultiplier
832 
-- assignment(s): dex_bitnum_sreg
833 
-- replace(s): instruction_reg
834 
 
835 
dex_bitop_bitnum <= instruction_reg(2 downto 0);      -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTION
836 
dex_bitnum_sreg <= instruction_reg_cml_1(6 downto 4);
837 
dex_adrreg_r  <=  instruction_reg(9) & instruction_reg(3 downto 0);
838 
dex_adrreg_d  <= instruction_reg(8 downto 4);
839 
-- SynEDA CoreMultiplier
840 
-- assignment(s): dex_brxx_offset
841 
-- replace(s): instruction_reg
842 
 
843 
dex_brxx_offset <= instruction_reg_cml_1(9 downto 3);       -- OFFSET FOR BRBC/BRBS
844 
dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS
845 
--dex_adrindreg <= instruction_reg(3 downto 2);
846 
 
847 
-- SynEDA CoreMultiplier
848 
-- assignment(s): dex_adrreg_d_latched
849 
-- replace(s): dex_adrreg_d, dex_adrreg_d_latched, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
850 
 
851 
-- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONS
852 
latcht_rd_adr:process(cp2,ireset)
853 
begin
854 
if ireset ='0' then
855 
dex_adrreg_d_latched <= (others => '0');
856 
elsif (cp2='1' and cp2'event) then dex_adrreg_d_latched <= dex_adrreg_d_latched_cml_1;
857 
 if (cp2en='1') then                                                      -- Clock enable
858 
  if ((idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1) or idc_sts_cml_1 or
859 
          (idc_st_x_cml_1  or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)or idc_lds_cml_1 or
860 
           idc_pop_cml_1)='1' then
861 
   dex_adrreg_d_latched <= dex_adrreg_d_cml_1;
862 
  end if;
863 
 end if;
864 
end if;
865 
end process;
866 
-- +++++++++++++++++++++++++++++++++++++++++++++++++
867 
 
868 
 
869 
-- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW  ADDRESS CONTROL LOGIC
870 
adiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0';
871 
 
872 
-- SynEDA CoreMultiplier
873 
-- assignment(s): adiw_sbiw_encoder_mux_out
874 
-- replace(s): adiw_sbiw_encoder_out, adiw_sbiw_encoder_mux_out
875 
 
876 
adiw_sbiw_high_reg_adr:process(cp2,ireset)
877 
begin
878 
if ireset ='0' then
879 
adiw_sbiw_encoder_mux_out <= (others=>'0');
880 
elsif(cp2='1' and cp2'event) then adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_mux_out_cml_1;
881 
 if (cp2en='1') then                                                      -- Clock enable
882 
  adiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out_cml_1 +1;
883 
 end if;
884 
end if;
885 
end process;
886 
 
887 
-- ##########################
888 
 
889 
-- NOP INSERTION
890 
 
891 
--instruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0');
892 
instruction_code_reg <= (others => '0') when (nop_insert_st='1') else -- NOP
893 
                        instruction_reg;                                                                                                -- Instruction
894 
 
895 
 
896 
nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or
897 
              brxx_st or ld_st or st_st or ncall_st0 or nirq_st0 or nret_st0 or nreti_st0 or nlpm_st0 or njmp_st0 or
898 
              nrcall_st0 or nicall_st0 or sts_st or lds_st or nskip_inst_st0;
899 
 
900 
 
901 
-- INSTRUCTION DECODER (CONNECTED AFTER NOP INSERTION LOGIC)
902 
 
903 
-- SynEDA CoreMultiplier
904 
-- assignment(s): idc_add
905 
-- replace(s): instruction_code_reg
906 
 
907 
idc_adc  <= '1' when instruction_code_reg(15 downto 10) = "000111" else '0'; -- 000111XXXXXXXXXX
908 
idc_add  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "000011" else '0'; -- 000011XXXXXXXXXX
909 
 
910 
idc_adiw <= '1' when instruction_code_reg(15 downto 8) = "10010110" else '0'; -- 10010110XXXXXXXX
911 
 
912 
-- SynEDA CoreMultiplier
913 
-- assignment(s): idc_and
914 
-- replace(s): instruction_code_reg
915 
 
916 
idc_and  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001000" else '0'; -- 001000XXXXXXXXXX
917 
idc_andi <= '1' when instruction_code_reg(15 downto 12) = "0111" else '0'; -- 0111XXXXXXXXXXXX
918 
 
919 
-- SynEDA CoreMultiplier
920 
-- assignment(s): idc_asr
921 
-- replace(s): instruction_code_reg
922 
 
923 
idc_asr  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100101" else '0'; -- 1001010XXXXX0101
924 
 
925 
-- SynEDA CoreMultiplier
926 
-- assignment(s): idc_bclr
927 
-- replace(s): instruction_code_reg
928 
 
929 
idc_bclr <= '1' when instruction_code_reg_cml_1(15 downto 7)&instruction_code_reg_cml_1(3 downto 0) = "1001010011000" else '0'; -- 100101001XXX1000
930 
 
931 
-- SynEDA CoreMultiplier
932 
-- assignment(s): idc_bld
933 
-- replace(s): instruction_code_reg
934 
 
935 
idc_bld  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3) = "11111000" else '0'; -- 1111100XXXXX0XXX
936 
 
937 
idc_brbc <= '1' when instruction_code_reg(15 downto 10) = "111101" else '0'; -- 111101XXXXXXXXXX
938 
idc_brbs <= '1' when instruction_code_reg(15 downto 10) = "111100" else '0'; -- 111100XXXXXXXXXX
939 
 
940 
-- SynEDA CoreMultiplier
941 
-- assignment(s): idc_bset
942 
-- replace(s): instruction_code_reg
943 
 
944 
idc_bset <= '1' when instruction_code_reg_cml_1(15 downto 7)&instruction_code_reg_cml_1(3 downto 0) = "1001010001000" else '0'; -- 100101000XXX1000
945 
 
946 
-- SynEDA CoreMultiplier
947 
-- assignment(s): idc_bst
948 
-- replace(s): instruction_code_reg
949 
 
950 
idc_bst  <= '1' when instruction_code_reg_cml_1(15 downto 9) = "1111101" else '0'; -- 1111101XXXXXXXXX
951 
 
952 
-- SynEDA CoreMultiplier
953 
-- assignment(s): idc_call
954 
-- replace(s): instruction_code_reg
955 
 
956 
idc_call <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 1) = "1001010111" else '0'; -- 1001010XXXXX111X
957 
 
958 
idc_cbi  <= '1' when instruction_code_reg(15 downto 8) = "10011000" else '0'; -- 10011000XXXXXXXX
959 
 
960 
-- SynEDA CoreMultiplier
961 
-- assignment(s): idc_com
962 
-- replace(s): instruction_code_reg
963 
 
964 
idc_com  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100000" else '0'; -- 1001010XXXXX0000
965 
 
966 
idc_cp   <= '1' when instruction_code_reg(15 downto 10) = "000101" else '0'; -- 000101XXXXXXXXXX
967 
 
968 
idc_cpc  <= '1' when instruction_code_reg(15 downto 10) = "000001" else '0'; -- 000001XXXXXXXXXX
969 
 
970 
idc_cpi  <= '1' when instruction_code_reg(15 downto 12) = "0011" else '0'; -- 0011XXXXXXXXXXXX
971 
 
972 
idc_cpse <= '1' when instruction_code_reg(15 downto 10) = "000100" else '0'; -- 000100XXXXXXXXXX
973 
 
974 
-- SynEDA CoreMultiplier
975 
-- assignment(s): idc_dec
976 
-- replace(s): instruction_code_reg
977 
 
978 
idc_dec  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010101010" else '0'; -- 1001010XXXXX1010
979 
 
980 
idc_elpm <= '1' when instruction_code_reg = "1001010111011000" else '0'; -- 1001010111011000
981 
 
982 
-- SynEDA CoreMultiplier
983 
-- assignment(s): idc_eor
984 
-- replace(s): instruction_code_reg
985 
 
986 
idc_eor  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001001" else '0'; -- 001001XXXXXXXXXX
987 
 
988 
idc_icall<= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101011001" else '0'; -- 10010101XXXX1001
989 
 
990 
idc_ijmp <= '1' when instruction_code_reg(15 downto 8)&instruction_code_reg(3 downto 0) = "100101001001" else '0'; -- 10010100XXXX1001
991 
 
992 
idc_in   <= '1' when instruction_code_reg(15 downto 11) = "10110" else '0'; -- 10110XXXXXXXXXXX
993 
 
994 
-- SynEDA CoreMultiplier
995 
-- assignment(s): idc_inc
996 
-- replace(s): instruction_code_reg
997 
 
998 
idc_inc  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100011" else '0'; -- 1001010XXXXX0011
999 
 
1000 
-- SynEDA CoreMultiplier
1001 
-- assignment(s): idc_jmp
1002 
-- replace(s): instruction_code_reg
1003 
 
1004 
idc_jmp  <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 1) = "1001010110" else '0'; -- 1001010XXXXX110X
1005 
 
1006 
 
1007 
-- LD,LDD
1008 
idc_ld_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001100" or
1009 
                     instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001101"  or
1010 
                                         instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001110" else '0';
1011 
 
1012 
idc_ld_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001001" or
1013 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010001010") else '0';
1014 
 
1015 
idc_ldd_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10001" else '0'; -- 10X0XX0XXXXX1XXX
1016 
 
1017 
idc_ld_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000001" or
1018 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010000010") else '0';
1019 
 
1020 
idc_ldd_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10000" else '0'; -- 10X0XX0XXXXX0XXX
1021 
-- ######
1022 
 
1023 
 
1024 
idc_ldi <= '1' when instruction_code_reg(15 downto 12) = "1110" else '0'; -- 1110XXXXXXXXXXXX
1025 
 
1026 
idc_lds <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010000000" else '0'; -- 1001000XXXXX0000
1027 
 
1028 
idc_lpm <= '1' when instruction_code_reg = "1001010111001000" else '0'; -- 1001010111001000
1029 
 
1030 
-- SynEDA CoreMultiplier
1031 
-- assignment(s): idc_lsr
1032 
-- replace(s): instruction_code_reg
1033 
 
1034 
idc_lsr <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100110" else '0'; -- 1001010XXXXX0110
1035 
 
1036 
-- SynEDA CoreMultiplier
1037 
-- assignment(s): idc_mov
1038 
-- replace(s): instruction_code_reg
1039 
 
1040 
idc_mov <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001011" else '0'; -- 001011XXXXXXXXXX
1041 
 
1042 
idc_mul <= '1' when instruction_code_reg(15 downto 10) = "100111" else '0'; -- 100111XXXXXXXXXX
1043 
 
1044 
-- SynEDA CoreMultiplier
1045 
-- assignment(s): idc_neg
1046 
-- replace(s): instruction_code_reg
1047 
 
1048 
idc_neg <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100001" else '0'; -- 1001010XXXXX0001
1049 
 
1050 
idc_nop <= '1' when instruction_code_reg = "0000000000000000" else '0'; -- 0000000000000000
1051 
 
1052 
-- SynEDA CoreMultiplier
1053 
-- assignment(s): idc_or
1054 
-- replace(s): instruction_code_reg
1055 
 
1056 
idc_or  <= '1' when instruction_code_reg_cml_1(15 downto 10) = "001010" else '0'; -- 001010XXXXXXXXXX
1057 
 
1058 
idc_ori <= '1' when instruction_code_reg(15 downto 12) = "0110" else '0'; -- 0110XXXXXXXXXXXX
1059 
 
1060 
idc_out <= '1' when instruction_code_reg(15 downto 11) = "10111" else '0'; -- 10111XXXXXXXXXXX
1061 
 
1062 
idc_pop <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010001111" else '0'; -- 1001000XXXXX1111
1063 
 
1064 
idc_push<= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011111" else '0'; -- 1001001XXXXX1111
1065 
 
1066 
idc_rcall<= '1' when instruction_code_reg(15 downto 12) = "1101" else '0'; -- 1101XXXXXXXXXXXX
1067 
 
1068 
idc_ret  <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101001000" else '0'; -- 100101010XX01000
1069 
 
1070 
idc_reti <= '1' when instruction_code_reg(15 downto 7)&instruction_code_reg(4 downto 0) = "10010101011000" else '0'; -- 100101010XX11000
1071 
 
1072 
idc_rjmp <= '1' when instruction_code_reg(15 downto 12) = "1100" else '0'; -- 1100XXXXXXXXXXXX
1073 
 
1074 
idc_ror  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010100111" else '0'; -- 1001010XXXXX0111
1075 
 
1076 
idc_sbc  <= '1' when instruction_code_reg(15 downto 10) = "000010" else '0'; -- 000010XXXXXXXXXX
1077 
 
1078 
idc_sbci <= '1' when instruction_code_reg(15 downto 12) = "0100" else '0'; -- 0100XXXXXXXXXXXX
1079 
 
1080 
idc_sbi  <= '1' when instruction_code_reg(15 downto 8) = "10011010" else '0'; -- 10011010XXXXXXXX
1081 
 
1082 
idc_sbic <= '1' when instruction_code_reg(15 downto 8) = "10011001" else '0'; -- 10011001XXXXXXXX
1083 
 
1084 
idc_sbis <= '1' when instruction_code_reg(15 downto 8) = "10011011" else '0'; -- 10011011XXXXXXXX
1085 
 
1086 
idc_sbiw <= '1' when instruction_code_reg(15 downto 8) = "10010111" else '0'; -- 10010111XXXXXXXX
1087 
 
1088 
idc_sbrc <= '1' when instruction_code_reg(15 downto 9) = "1111110" else '0'; -- 1111110XXXXXXXXX
1089 
 
1090 
idc_sbrs <= '1' when instruction_code_reg(15 downto 9) = "1111111" else '0'; -- 1111111XXXXXXXXX
1091 
 
1092 
-- SynEDA CoreMultiplier
1093 
-- assignment(s): idc_sleep
1094 
-- replace(s): instruction_code_reg
1095 
 
1096 
idc_sleep<= '1' when instruction_code_reg_cml_1(15 downto 5)&instruction_code_reg_cml_1(3 downto 0) = "100101011001000" else '0'; -- 10010101100X1000
1097 
 
1098 
 
1099 
-- ST,STD
1100 
idc_st_x <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011100" or
1101 
                     instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011101" or
1102 
                     instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010011110" else '0';
1103 
 
1104 
idc_st_y <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011001" or
1105 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010011010") else '0';
1106 
 
1107 
idc_std_y<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10011" else '0'; -- 10X0XX1XXXXX1XXX
1108 
 
1109 
idc_st_z <= '1' when (instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010001" or
1110 
                                          instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0)="10010010010") else '0';
1111 
 
1112 
idc_std_z<= '1' when instruction_code_reg(15 downto 14)&instruction_code_reg(12)&instruction_code_reg(9)&instruction_code_reg(3) = "10010" else '0'; -- 10X0XX1XXXXX0XXX
1113 
-- ######
1114 
 
1115 
idc_sts  <= '1' when instruction_code_reg(15 downto 9)&instruction_code_reg(3 downto 0) = "10010010000" else '0'; -- 1001001XXXXX0000
1116 
 
1117 
idc_sub  <= '1' when instruction_code_reg(15 downto 10) = "000110" else '0'; -- 000110XXXXXXXXXX
1118 
 
1119 
idc_subi <= '1' when instruction_code_reg(15 downto 12) = "0101" else '0'; -- 0101XXXXXXXXXXXX
1120 
 
1121 
-- SynEDA CoreMultiplier
1122 
-- assignment(s): idc_swap
1123 
-- replace(s): instruction_code_reg
1124 
 
1125 
idc_swap <= '1' when instruction_code_reg_cml_1(15 downto 9)&instruction_code_reg_cml_1(3 downto 0) = "10010100010" else '0'; -- 1001010XXXXX0010
1126 
 
1127 
-- SynEDA CoreMultiplier
1128 
-- assignment(s): idc_wdr
1129 
-- replace(s): instruction_code_reg
1130 
 
1131 
idc_wdr  <= '1' when instruction_code_reg_cml_1(15 downto 5)&instruction_code_reg_cml_1(3 downto 0) = "100101011011000" else '0'; -- 10010101101X1000
1132 
 
1133 
-- SynEDA CoreMultiplier
1134 
-- assignment(s): idc_psinc
1135 
-- replace(s): instruction_code_reg, idc_ld_x, idc_ld_y, idc_ld_z, idc_st_x, idc_st_y, idc_st_z
1136 
 
1137 
-- ADDITIONAL SIGNALS
1138 
idc_psinc <= '1' when (instruction_code_reg_cml_1(1 downto 0) = "01" and
1139 
 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1 or idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1)='1') else '0';  -- POST INCREMENT FOR LD/ST INSTRUCTIONS
1140 
 
1141 
idc_prdec <= '1' when (instruction_code_reg(1 downto 0)  = "10" and
1142 
 (idc_st_x or idc_st_y or idc_st_z or idc_ld_x or idc_ld_y or idc_ld_z)='1') else '0';  -- PRE DECREMENT FOR LD/ST INSTRUCTIONS
1143 
 
1144 
 
1145 
-- ##########################################################################################################
1146 
 
1147 
-- SynEDA CoreMultiplier
1148 
-- assignment(s): ramadr_reg_en
1149 
-- replace(s): cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1150 
 
1151 
-- WRITE ENABLE SIGNALS FOR ramadr_reg
1152 
ramadr_reg_en <= idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1 or idc_lds_cml_1 or    -- LD/LDD/LDS(two cycle execution)
1153 
                 idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1 or idc_sts_cml_1 or    -- ST/STS/STS(two cycle execution)
1154 
                                 idc_push_cml_1 or idc_pop_cml_1 or
1155 
                                 idc_rcall_cml_1 or (rcall_st1_cml_1 and not cpuwait_cml_1) or idc_icall_cml_1 or (icall_st1_cml_1 and not cpuwait_cml_1) or -- RCALL/ICALL
1156 
                                 call_st1_cml_1 or  (call_st2_cml_1 and not cpuwait_cml_1) or irq_st1_cml_1 or (irq_st2_cml_1 and not cpuwait_cml_1) or      -- CALL/IRQ
1157 
                                 idc_ret_cml_1 or (ret_st1_cml_1 and not cpuwait_cml_1 ) or idc_reti_cml_1 or (reti_st1_cml_1 and not cpuwait_cml_1);            -- RET/RETI  -- ??
1158 
 
1159 
 
1160 
-- SynEDA CoreMultiplier
1161 
-- assignment(s): ramadr_reg_in
1162 
-- replace(s): inst, cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_ld_x, idc_ld_y, idc_ld_z, idc_lds, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_st_x, idc_st_y, idc_st_z, idc_sts
1163 
 
1164 
-- RAMADR MUX
1165 
ramadr_reg_in <= sph_out&spl_out when
1166 
  (idc_rcall_cml_1 or (rcall_st1_cml_1 and not cpuwait_cml_1)or idc_icall_cml_1 or (icall_st1_cml_1 and not cpuwait_cml_1)or  -- RCALL/ICALL
1167 
   call_st1_cml_1  or (call_st2_cml_1 and not cpuwait_cml_1) or irq_st1_cml_1   or (irq_st2_cml_1 and not cpuwait_cml_1)  or  -- CALL/IRQ
1168 
   idc_push_cml_1 )='1' else                                                                      -- PUSH
1169 
   (sph_out&spl_out)+1 when (idc_ret_cml_1 or (ret_st1_cml_1 and not cpuwait_cml_1)  or idc_reti_cml_1  or (reti_st1_cml_1 and not cpuwait_cml_1) or idc_pop_cml_1)='1' else  -- RET/RETI/POP
1170 
   inst_cml_1 when (idc_lds_cml_1 or idc_sts_cml_1) ='1' else     -- LDS/STS (two cycle execution)
1171 
   reg_h_out when (idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1 or idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1)='1' else  -- LD/ST
1172 
   (reg_h_out + ("000000000"&dex_adr_disp));                                                       -- LDD/STD
1173 
 
1174 
 
1175 
-- SynEDA CoreMultiplier
1176 
-- assignment(s): ramadr_int
1177 
-- replace(s): ramadr_int
1178 
 
1179 
-- ADDRESS REGISTER
1180 
ramadr_reg:process(cp2,ireset)
1181 
begin
1182 
if ireset='0' then
1183 
ramadr_int <= (others => '0');
1184 
elsif(cp2='1' and cp2'event) then ramadr_int <= ramadr_int_cml_1;
1185 
 if (cp2en='1') then                                                      -- Clock enable
1186 
  if (ramadr_reg_en='1') then
1187 
   ramadr_int <= ramadr_reg_in;
1188 
  end if;
1189 
 end if;
1190 
end if;
1191 
end process;
1192 
 
1193 
ramadr <= ramadr_int;
1194 
 
1195 
-- SynEDA CoreMultiplier
1196 
-- assignment(s): reg_file_adr_space
1197 
-- replace(s): reg_file_adr_space
1198 
 
1199 
-- GENERAL PURPOSE REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
1200 
gp_reg_adr:process(cp2,ireset)
1201 
begin
1202 
if ireset='0' then
1203 
reg_file_adr_space <='0';
1204 
elsif(cp2='1' and cp2'event) then reg_file_adr_space <= reg_file_adr_space_cml_1;
1205 
 if (cp2en='1') then                                                      -- Clock enable
1206 
  if (ramadr_reg_en='1') then
1207 
   if (ramadr_reg_in(15 downto 5)=const_ram_to_reg) then
1208 
    reg_file_adr_space <= '1';                             -- ADRESS RANGE 0x0000-0x001F -> REGISTERS (R0-R31)
1209 
   else
1210 
    reg_file_adr_space <= '0';
1211 
   end if;
1212 
  end if;
1213 
 end if;
1214 
end if;
1215 
end process;
1216 
 
1217 
-- SynEDA CoreMultiplier
1218 
-- assignment(s): io_file_adr_space
1219 
-- replace(s): io_file_adr_space
1220 
 
1221 
-- I/O REGISTERS ADDRESSING FLAG FOR ST/STD/STS INSTRUCTIONS
1222 
io_reg_adr:process(cp2,ireset)
1223 
begin
1224 
if ireset='0' then io_file_adr_space<='0';
1225 
elsif(cp2='1' and cp2'event) then io_file_adr_space <= io_file_adr_space_cml_1;
1226 
 if (cp2en='1') then                                                      -- Clock enable
1227 
  if (ramadr_reg_en='1') then
1228 
   if (ramadr_reg_in(15 downto 5)=const_ram_to_io_a or ramadr_reg_in(15 downto 5)=const_ram_to_io_b) then
1229 
    io_file_adr_space <= '1';                             -- ADRESS RANGE 0x0020-0x005F -> I/O PORTS (0x00-0x3F)
1230 
   else
1231 
    io_file_adr_space <= '0';
1232 
   end if;
1233 
  end if;
1234 
 end if;
1235 
end if;
1236 
end process;
1237 
 
1238 
 
1239 
 
1240 
-- ##########################################################################################################
1241 
 
1242 
 
1243 
-- REGRE/REGWE LOGIC (5 BIT ADDSRESS BUS (INTERNAL ONLY) 32 LOCATIONS (R0-R31))
1244 
 
1245 
-- SynEDA CoreMultiplier
1246 
-- assignment(s): alu_reg_wr
1247 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_adiw, idc_andi, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi
1248 
 
1249 
-- WRITE ENABLE FOR Rd REGISTERS
1250 
alu_reg_wr <= idc_adc_cml_1 or idc_add or idc_adiw_cml_1 or adiw_st_cml_1 or idc_sub_cml_1 or idc_subi_cml_1 or idc_sbc_cml_1 or idc_sbci_cml_1 or
1251 
              idc_sbiw_cml_1 or  sbiw_st_cml_1 or idc_and or idc_andi_cml_1 or idc_or or idc_ori_cml_1 or idc_eor or idc_com or
1252 
                          idc_neg or idc_inc or idc_dec or idc_lsr or idc_ror_cml_1 or idc_asr or idc_swap;
1253 
 
1254 
 
1255 
-- SynEDA CoreMultiplier
1256 
-- assignment(s): reg_rd_wr
1257 
-- replace(s): reg_file_adr_space, lpm_st2, sts_st, lds_st, st_st, ld_st, pop_st, idc_in, idc_ldi
1258 
 
1259 
reg_rd_wr_cml_out <= idc_in_cml_1 or alu_reg_wr or idc_bld or             -- ALU INSTRUCTIONS + IN/BLD INSRTRUCTION
1260 
 (pop_st_cml_1 or ld_st_cml_1 or lds_st_cml_1)or                                            -- POP/LD/LDD/LDS INSTRUCTIONS
1261 
 ((st_st_cml_1 or sts_st_cml_1) and reg_file_adr_space_cml_1)or              -- ST/STD/STS INSTRUCTION
1262 
  lpm_st2_cml_1 or idc_ldi_cml_1 or idc_mov;                            -- LPM/LDI/MOV INSTRUCTION
1263 
 
1264 
 
1265 
  reg_rd_adr <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else
1266 
                           "00000" when lpm_st2='1' else
1267 
               adiw_sbiw_encoder_out     when (idc_adiw or idc_sbiw)='1' else
1268 
               adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else
1269 
                           dex_adrreg_d_latched      when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else
1270 
               ramadr_int(4 downto 0)    when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
1271 
                           dex_adrreg_d;
1272 
 
1273 
  reg_rd_adr_int <= '1'&dex_adrreg_d(3 downto 0) when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi or idc_ldi)='1' else
1274 
                           "00000" when lpm_st2='1' else
1275 
               adiw_sbiw_encoder_out     when (idc_adiw or idc_sbiw)='1' else
1276 
               adiw_sbiw_encoder_mux_out when (adiw_st or sbiw_st)='1' else
1277 
                           dex_adrreg_d_latched      when (((st_st or sts_st) and not reg_file_adr_space) or ld_st or lds_st or pop_st)='1' else
1278 
               ramadr_int(4 downto 0)    when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
1279 
                           dex_adrreg_d;
1280 
 
1281 
reg_rr_adr <= ramadr_int(4 downto 0) when ((ld_st or lds_st) and reg_file_adr_space)='1'else --!!??
1282 
                  dex_adrreg_d_latched   when ((st_st or sts_st) and reg_file_adr_space)='1'else --!!??
1283 
                  dex_adrreg_r;
1284 
 
1285 
-- SynEDA CoreMultiplier
1286 
-- assignment(s): reg_rd_in
1287 
-- replace(s): reg_rr_out, reg_file_adr_space, lpm_st2, sts_st, lds_st, st_st, ld_st, pop_st, instruction_reg, dex_dat8_immed, gp_reg_tmp, idc_in, idc_ldi
1288 
 
1289 
-- MULTIPLEXER FOR REGISTER FILE Rd INPUT
1290 
reg_rd_in_cml_out <= dbusin when (idc_in_cml_1 or ((lds_st_cml_1 or ld_st_cml_1)and not reg_file_adr_space_cml_1) or pop_st_cml_1)='1' else -- FROM INPUT DATA BUS
1291 
                         reg_rr_out_cml_1 when ((lds_st_cml_1 or ld_st_cml_1)  and reg_file_adr_space_cml_1)='1' else
1292 
             gp_reg_tmp_cml_1 when ((st_st_cml_1 or sts_st_cml_1)  and reg_file_adr_space_cml_1)='1' else -- ST/STD/STS &  ADDRESS FROM 0 TO 31 (REGISTER FILE)
1293 
                         bld_op_out when (idc_bld='1')else                                     -- FROM BIT PROCESSOR BLD COMMAND
1294 
             reg_rr_out_cml_1 when (idc_mov='1')else                                     -- FOR MOV INSTRUCTION
1295 
                         instruction_reg_cml_1(15 downto 8) when (lpm_st2_cml_1='1' and reg_z_out(0)='1') else -- LPM/ELPM
1296 
                         instruction_reg_cml_1(7 downto 0) when  (lpm_st2_cml_1='1' and reg_z_out(0)='0') else -- LPM/ELPM
1297 
             dex_dat8_immed_cml_1 when idc_ldi_cml_1='1' else
1298 
                         alu_data_out;                                               -- FROM ALU DATA OUT
1299 
 
1300 
-- SynEDA CoreMultiplier
1301 
-- assignment(s): iowe_int
1302 
-- replace(s): io_file_adr_space, sts_st, st_st, sbi_st, cbi_st, idc_out
1303 
 
1304 
-- IORE/IOWE LOGIC (6 BIT ADDRESS adr[5..0] FOR I/O PORTS(64 LOCATIONS))
1305 
iore_int <= idc_in or idc_sbi or idc_cbi or idc_sbic or idc_sbis or ((ld_st or lds_st) and io_file_adr_space);   -- IN/SBI/CBI
1306 
iowe_int <= '1' when ((idc_out_cml_1 or sbi_st_cml_1 or cbi_st_cml_1) or
1307 
                     ((st_st_cml_1 or sts_st_cml_1) and io_file_adr_space_cml_1))='1' else '0'; -- OUT/SBI/CBI + !! ST/STS/STD
1308 
 
1309 
 
1310 
-- adr[5..0] BUS MULTIPLEXER
1311 
adr_int <= dex_adr6port when (idc_in or idc_out) = '1' else                          -- IN/OUT INSTRUCTIONS
1312 
           '0'&dex_adr5port when (idc_cbi or idc_sbi or idc_sbic or idc_sbis) ='1'    else  -- CBI/SBI (READ PHASE) + SBIS/SBIC
1313 
                   '0'&cbi_sbi_io_adr_tmp when (cbi_st or sbi_st)='1' else       -- CBI/SBI (WRITE PHASE)
1314 
                    ramadr_int(6)&ramadr_int(4 downto 0);                                                   -- LD/LDS/LDD/ST/STS/STD
1315 
 
1316 
-- ramre LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
1317 
--ramre_int <= not(reg_file_adr_space or io_file_adr_space) and
1318 
--            (ld_st or lds_st2 or pop_st or                    -- LD/LDD/LDS/POP/
1319 
--             ret_st1 or ret_st2 or reti_st1 or reti_st2);     -- RET/RETI
1320 
 
1321 
-- SynEDA CoreMultiplier
1322 
-- assignment(s): ramre_int
1323 
-- replace(s): cpuwait, ret_st2, reti_st2, lds_st, ld_st, pop_st, ramre_int, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_pop, idc_ret, idc_reti
1324 
 
1325 
DataMemoryRead:process(cp2,ireset)
1326 
begin
1327 
if ireset='0' then -- Reset
1328 
 ramre_int <= '0';
1329 
elsif (cp2='1' and cp2'event) then ramre_int <= ramre_int_cml_1; -- Clock
1330 
 if (cp2en='1') then                                                      -- Clock enable
1331 
  case ramre_int_cml_1 is
1332 
   when '0' =>
1333 
    if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and
1334 
           ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and
1335 
       ramadr_reg_in(15 downto 5)/=const_ram_to_reg  and
1336 
      (idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1 or  -- LD/LDD instruction
1337 
           idc_lds_cml_1 or                                                     -- LDS instruction(two cycle execution)
1338 
           idc_pop_cml_1 or                                                     -- POP instruction
1339 
       idc_ret_cml_1 or                                                         -- RET instruction
1340 
           idc_reti_cml_1)='1')                                                                                                     -- RETI instruction
1341 
           then ramre_int <='1';
1342 
    end if;
1343 
   when '1' =>
1344 
    if ((ld_st_cml_1 or lds_st_cml_1 or pop_st_cml_1 or ret_st2_cml_1 or reti_st2_cml_1)and not cpuwait_cml_1)='1' then
1345 
     ramre_int <='0';
1346 
    end if;
1347 
   when others  =>      null;
1348 
  end case;
1349 
 end if;
1350 
end if;
1351 
end process;
1352 
 
1353 
-- ramwe LOGIC (16 BIT ADDRESS ramadr[15..0] FOR DATA RAM (64*1024-64-32 LOCATIONS))
1354 
--ramwe_int <= not(reg_file_adr_space or io_file_adr_space) and
1355 
--            (st_st or sts_st2 or push_st or rcall_st1 or rcall_st2 or -- ST/STD/STS/PUSH/RCALL
1356 
--                                                      icall_st1 or icall_st2 or -- ICALL
1357 
--                                                      call_st2 or call_st3 or   -- CALL
1358 
--                                                                                      irq_st2 or irq_st3);      -- INTERRUPT
1359 
 
1360 
-- SynEDA CoreMultiplier
1361 
-- assignment(s): ramwe_int
1362 
-- replace(s): cpuwait, irq_st1, irq_st3, call_st1, call_st3, rcall_st2, icall_st2, sts_st, st_st, push_st, ramwe_int, idc_icall, idc_push, idc_rcall, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1363 
 
1364 
DataMemoryWrite:process(cp2,ireset)
1365 
begin
1366 
if ireset='0' then -- Reset
1367 
 ramwe_int <= '0';
1368 
elsif (cp2='1' and cp2'event) then ramwe_int <= ramwe_int_cml_1; -- Clock
1369 
 if (cp2en='1') then                                                      -- Clock enable
1370 
  case ramwe_int_cml_1 is
1371 
   when '0' =>
1372 
    if(ramadr_reg_in(15 downto 5)/=const_ram_to_io_a and
1373 
           ramadr_reg_in(15 downto 5)/=const_ram_to_io_b and
1374 
       ramadr_reg_in(15 downto 5)/=const_ram_to_reg  and
1375 
      (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1 or  -- ST/STD instruction
1376 
           idc_sts_cml_1 or                                                     -- STS instruction (two cycle execution)
1377 
           idc_push_cml_1 or                                                    -- PUSH instruction
1378 
           idc_rcall_cml_1 or                                                                                                     -- RCALL instruction
1379 
           idc_icall_cml_1 or                                                                                                     -- ICALL instruction
1380 
           call_st1_cml_1 or                                                    -- CALL instruction
1381 
           irq_st1_cml_1)='1')                                                  -- Interrupt
1382 
          then ramwe_int <='1';
1383 
    end if;
1384 
   when '1' =>
1385 
    if ((st_st_cml_1 or sts_st_cml_1 or push_st_cml_1 or rcall_st2_cml_1 or
1386 
             icall_st2_cml_1 or call_st3_cml_1 or irq_st3_cml_1)and not cpuwait_cml_1)='1' then ramwe_int <='0';
1387 
    end if;
1388 
   when others  =>      null;
1389 
  end case;
1390 
end if;
1391 
end if;
1392 
end process;
1393 
 
1394 
-- DBUSOUT MULTIPLEXER
1395 
--dbusout_mux_logic: for i in dbusout_int'range generate
1396 
--dbusout_int(i)<= (reg_rd_out(i) and (idc_push or idc_sts or
1397 
--                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1398 
--                               (gp_reg_tmp(i) and (st_st or sts_st))or                            -- NEW
1399 
--                               (bitpr_io_out(i) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1400 
--                 (program_counter(i)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC                 (program_counter_high_fr(i) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1401 
--                 (pc_for_interrupt(i) and irq_st1) or
1402 
--                               (pc_for_interrupt(8) and irq_st2) or
1403 
--                               (reg_rd_out(i) and  idc_out); -- OUT
1404 
--end generate;
1405 
 
1406 
dbusout_int(0)<= (reg_rd_out_cml_1(0) and (idc_push_cml_1 or idc_sts_cml_1 or
1407 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1408 
                                 (gp_reg_tmp_cml_1(0) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1409 
                                 (bitpr_io_out_cml_1(0) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1410 
                 (program_counter_cml_1(0)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1411 
                 (program_counter_high_fr_cml_1(0) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1412 
                 (pc_for_interrupt_cml_1(0) and irq_st1_cml_1) or
1413 
                                 (pc_for_interrupt_cml_1(8) and irq_st2_cml_1) or
1414 
                                 (reg_rd_out_cml_1(0) and  idc_out_cml_1); -- OUT
1415 
 
1416 
dbusout_int(1)<= (reg_rd_out_cml_1(1) and (idc_push_cml_1 or idc_sts_cml_1 or
1417 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1418 
                                 (gp_reg_tmp_cml_1(1) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1419 
                                 (bitpr_io_out_cml_1(1) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1420 
                 (program_counter_cml_1(1)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1421 
                 (program_counter_high_fr_cml_1(1) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1422 
                 (pc_for_interrupt_cml_1(1) and irq_st1_cml_1) or
1423 
                                 (pc_for_interrupt_cml_1(9) and irq_st2_cml_1) or
1424 
                                 (reg_rd_out_cml_1(1) and  idc_out_cml_1); -- OUT
1425 
 
1426 
dbusout_int(2)<= (reg_rd_out_cml_1(2) and (idc_push_cml_1 or idc_sts_cml_1 or
1427 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1428 
                                 (gp_reg_tmp_cml_1(2) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1429 
                                 (bitpr_io_out_cml_1(2) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1430 
                 (program_counter_cml_1(2)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1431 
                 (program_counter_high_fr_cml_1(2) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1432 
                 (pc_for_interrupt_cml_1(2) and irq_st1_cml_1) or
1433 
                                 (pc_for_interrupt_cml_1(10) and irq_st2_cml_1) or
1434 
                                 (reg_rd_out_cml_1(2) and  idc_out_cml_1); -- OUT
1435 
 
1436 
dbusout_int(3)<= (reg_rd_out_cml_1(3) and (idc_push_cml_1 or idc_sts_cml_1 or
1437 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1438 
                                 (gp_reg_tmp_cml_1(3) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1439 
                                 (bitpr_io_out_cml_1(3) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1440 
                 (program_counter_cml_1(3)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1441 
                 (program_counter_high_fr_cml_1(3) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1442 
                 (pc_for_interrupt_cml_1(3) and irq_st1_cml_1) or
1443 
                                 (pc_for_interrupt_cml_1(11) and irq_st2_cml_1) or
1444 
                                 (reg_rd_out_cml_1(3) and  idc_out_cml_1); -- OUT
1445 
 
1446 
dbusout_int(4)<= (reg_rd_out_cml_1(4) and (idc_push_cml_1 or idc_sts_cml_1 or
1447 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1448 
                                 (gp_reg_tmp_cml_1(4) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1449 
                                 (bitpr_io_out_cml_1(4) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1450 
                 (program_counter_cml_1(4)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1451 
                 (program_counter_high_fr_cml_1(4) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1452 
                 (pc_for_interrupt_cml_1(4) and irq_st1_cml_1) or
1453 
                                 (pc_for_interrupt_cml_1(12) and irq_st2_cml_1) or
1454 
                                 (reg_rd_out_cml_1(4) and  idc_out_cml_1); -- OUT
1455 
 
1456 
dbusout_int(5)<= (reg_rd_out_cml_1(5) and (idc_push_cml_1 or idc_sts_cml_1 or
1457 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1458 
                                 (gp_reg_tmp_cml_1(5) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1459 
                                 (bitpr_io_out_cml_1(5) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1460 
                 (program_counter_cml_1(5)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1461 
                 (program_counter_high_fr_cml_1(5) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1462 
                 (pc_for_interrupt_cml_1(5) and irq_st1_cml_1) or
1463 
                                 (pc_for_interrupt_cml_1(13) and irq_st2_cml_1) or
1464 
                                 (reg_rd_out_cml_1(5) and  idc_out_cml_1); -- OUT
1465 
 
1466 
dbusout_int(6)<= (reg_rd_out_cml_1(6) and (idc_push_cml_1 or idc_sts_cml_1 or
1467 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1468 
                                 (gp_reg_tmp_cml_1(6) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1469 
                                 (bitpr_io_out_cml_1(6) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1470 
                 (program_counter_cml_1(6)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1471 
                 (program_counter_high_fr_cml_1(6) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1472 
                 (pc_for_interrupt_cml_1(6) and irq_st1_cml_1) or
1473 
                                 (pc_for_interrupt_cml_1(14) and irq_st2_cml_1) or
1474 
                                 (reg_rd_out_cml_1(6) and  idc_out_cml_1); -- OUT
1475 
 
1476 
-- SynEDA CoreMultiplier
1477 
-- assignment(s): dbusout_int
1478 
-- replace(s): reg_rd_out, bitpr_io_out, program_counter, program_counter_high_fr, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, sts_st, st_st, sbi_st, cbi_st, pc_for_interrupt, gp_reg_tmp, idc_icall, idc_out, idc_push, idc_rcall, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1479 
 
1480 
dbusout_int(7)<= (reg_rd_out_cml_1(7) and (idc_push_cml_1 or idc_sts_cml_1 or
1481 
                 (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1482 
                                 (gp_reg_tmp_cml_1(7) and (st_st_cml_1 or sts_st_cml_1))or                            -- NEW
1483 
                                 (bitpr_io_out_cml_1(7) and (cbi_st_cml_1 or sbi_st_cml_1))or                          -- CBI/SBI  INSTRUCTIONS
1484 
                 (program_counter_cml_1(7)         and (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1))or                        -- LOW  PART OF PC
1485 
                 (program_counter_high_fr_cml_1(7) and (rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1))or                        -- HIGH PART OF PC
1486 
                 (pc_for_interrupt_cml_1(7) and irq_st1_cml_1) or
1487 
                                 (pc_for_interrupt_cml_1(15) and irq_st2_cml_1) or
1488 
                                 (reg_rd_out_cml_1(7) and  idc_out_cml_1); -- OUT
1489 
 
1490 
dbusout_int_route <= dbusout_int;
1491 
 
1492 
dbusout(0)<= (reg_rd_out_int(0) and (idc_push or idc_sts or
1493 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1494 
                                 (gp_reg_tmp(0) and (st_st or sts_st))or                            -- NEW
1495 
                                 (bitpr_io_out(0) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1496 
                 (program_counter(0)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1497 
                 (program_counter_high_fr(0) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1498 
                 (pc_for_interrupt(0) and irq_st1) or
1499 
                                 (pc_for_interrupt(8) and irq_st2) or
1500 
                                 (reg_rd_out_int(0) and  idc_out); -- OUT
1501 
 
1502 
dbusout(1)<= (reg_rd_out_int(1) and (idc_push or idc_sts or
1503 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1504 
                                 (gp_reg_tmp(1) and (st_st or sts_st))or                            -- NEW
1505 
                                 (bitpr_io_out(1) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1506 
                 (program_counter(1)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1507 
                 (program_counter_high_fr(1) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1508 
                 (pc_for_interrupt(1) and irq_st1) or
1509 
                                 (pc_for_interrupt(9) and irq_st2) or
1510 
                                 (reg_rd_out_int(1) and  idc_out); -- OUT
1511 
 
1512 
dbusout(2)<= (reg_rd_out_int(2) and (idc_push or idc_sts or
1513 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1514 
                                 (gp_reg_tmp(2) and (st_st or sts_st))or                            -- NEW
1515 
                                 (bitpr_io_out(2) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1516 
                 (program_counter(2)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1517 
                 (program_counter_high_fr(2) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1518 
                 (pc_for_interrupt(2) and irq_st1) or
1519 
                                 (pc_for_interrupt(10) and irq_st2) or
1520 
                                 (reg_rd_out_int(2) and  idc_out); -- OUT
1521 
 
1522 
dbusout(3)<= (reg_rd_out_int(3) and (idc_push or idc_sts or
1523 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1524 
                                 (gp_reg_tmp(3) and (st_st or sts_st))or                            -- NEW
1525 
                                 (bitpr_io_out(3) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1526 
                 (program_counter(3)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1527 
                 (program_counter_high_fr(3) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1528 
                 (pc_for_interrupt(3) and irq_st1) or
1529 
                                 (pc_for_interrupt(11) and irq_st2) or
1530 
                                 (reg_rd_out_int(3) and  idc_out); -- OUT
1531 
 
1532 
dbusout(4)<= (reg_rd_out_int(4) and (idc_push or idc_sts or
1533 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1534 
                                 (gp_reg_tmp(4) and (st_st or sts_st))or                            -- NEW
1535 
                                 (bitpr_io_out(4) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1536 
                 (program_counter(4)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1537 
                 (program_counter_high_fr(4) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1538 
                 (pc_for_interrupt(4) and irq_st1) or
1539 
                                 (pc_for_interrupt(12) and irq_st2) or
1540 
                                 (reg_rd_out_int(4) and  idc_out); -- OUT
1541 
 
1542 
dbusout(5)<= (reg_rd_out_int(5) and (idc_push or idc_sts or
1543 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1544 
                                 (gp_reg_tmp(5) and (st_st or sts_st))or                            -- NEW
1545 
                                 (bitpr_io_out(5) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1546 
                 (program_counter(5)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1547 
                 (program_counter_high_fr(5) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1548 
                 (pc_for_interrupt(5) and irq_st1) or
1549 
                                 (pc_for_interrupt(13) and irq_st2) or
1550 
                                 (reg_rd_out_int(5) and  idc_out); -- OUT
1551 
 
1552 
dbusout(6)<= (reg_rd_out_int(6) and (idc_push or idc_sts or
1553 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1554 
                                 (gp_reg_tmp(6) and (st_st or sts_st))or                            -- NEW
1555 
                                 (bitpr_io_out(6) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1556 
                 (program_counter(6)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1557 
                 (program_counter_high_fr(6) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1558 
                 (pc_for_interrupt(6) and irq_st1) or
1559 
                                 (pc_for_interrupt(14) and irq_st2) or
1560 
                                 (reg_rd_out_int(6) and  idc_out); -- OUT
1561 
 
1562 
dbusout(7)<= (reg_rd_out_int(7) and (idc_push or idc_sts or
1563 
                 (idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z)))or      -- PUSH/ST/STD/STS INSTRUCTIONS
1564 
                                 (gp_reg_tmp(7) and (st_st or sts_st))or                            -- NEW
1565 
                                 (bitpr_io_out(7) and (cbi_st or sbi_st))or                          -- CBI/SBI  INSTRUCTIONS
1566 
                 (program_counter(7)         and (idc_rcall or idc_icall or call_st1))or                        -- LOW  PART OF PC
1567 
                 (program_counter_high_fr(7) and (rcall_st1 or icall_st1 or call_st2))or                        -- HIGH PART OF PC
1568 
                 (pc_for_interrupt(7) and irq_st1) or
1569 
                                 (pc_for_interrupt(15) and irq_st2) or
1570 
                                 (reg_rd_out_int(7) and  idc_out); -- OUT
1571 
 
1572 
 
1573 
-- ALU CONNECTION
1574 
 
1575 
-- ALU Rr INPUT MUX
1576 
alu_data_r_in <= dex_dat8_immed       when (idc_subi or idc_sbci or idc_andi or idc_ori or idc_cpi)='1' else
1577 
                 "00"&dex_dat6_immed  when (idc_adiw or idc_sbiw) ='1' else
1578 
                 "00000000"           when (adiw_st or sbiw_st) ='1' else
1579 
                 reg_rr_out;
1580 
 
1581 
 
1582 
-- SynEDA CoreMultiplier
1583 
-- assignment(s): gp_reg_tmp
1584 
-- replace(s): reg_rd_out, gp_reg_tmp, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
1585 
 
1586 
-- gp_reg_tmp STORES TEMPREOARY THE VALUE OF SOURCE REGISTER DURING ST/STD/STS INSTRUCTION
1587 
gp_registers_trig:process(cp2,ireset)
1588 
begin
1589 
if (ireset='0') then
1590 
gp_reg_tmp <= (others=>'0');
1591 
elsif (cp2='1' and cp2'event) then gp_reg_tmp <= gp_reg_tmp_cml_1;
1592 
 if (cp2en='1') then                                                      -- Clock enable
1593 
  -- if ((idc_st_x or idc_st_y or idc_std_y or idc_st_z or idc_std_z) or sts_st1)='1' then  -- CLOCK ENABLE
1594 
  if ((idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1) or idc_sts_cml_1)='1' then  -- CLOCK ENABLE
1595 
     gp_reg_tmp <= reg_rd_out_cml_1;
1596 
  end if;
1597 
 end if;
1598 
end if;
1599 
end process;
1600 
 
1601 
-- **********************************************************************************************************
1602 
 
1603 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1604 
-- +++++++++++++++++++++++++++++++++++++++ PROGRAM COUNTER ++++++++++++++++++++++++++++++++++++++++++++++++++
1605 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1606 
 
1607 
-- SynEDA CoreMultiplier
1608 
-- assignment(s): program_counter_high_fr
1609 
-- replace(s): program_counter, program_counter_high_fr, irq_st1, call_st1, idc_icall, idc_rcall
1610 
 
1611 
program_counter_high_store:process(cp2,ireset)
1612 
begin
1613 
if ireset='0' then                         -- RESET
1614 
program_counter_high_fr <=(others => '0');
1615 
elsif (cp2='1' and cp2'event) then program_counter_high_fr <= program_counter_high_fr_cml_1;       -- CLOCK
1616 
 if (cp2en='1') then                                                      -- Clock enable
1617 
  if (idc_rcall_cml_1 or idc_icall_cml_1 or call_st1_cml_1 or irq_st1_cml_1) ='1' then
1618 
   program_counter_high_fr <= program_counter_cml_1(15 downto 8);       -- STORE HIGH BYTE OF THE PROGRAMM COUNTER FOR RCALL/ICALL/CALL INSTRUCTIONS AND INTERRUPTS
1619 
  end if;
1620 
 end if;
1621 
end if;
1622 
end process;
1623 
 
1624 
 
1625 
-- SynEDA CoreMultiplier
1626 
-- assignment(s): program_counter_tmp
1627 
-- replace(s): program_counter_tmp, program_counter, idc_elpm, idc_lpm
1628 
 
1629 
program_counter_for_lpm_elpm:process(cp2,ireset)
1630 
begin
1631 
if ireset='0' then                         -- RESET
1632 
program_counter_tmp<=(others => '0');
1633 
elsif (cp2='1' and cp2'event) then program_counter_tmp <= program_counter_tmp_cml_1;       -- CLOCK
1634 
 if (cp2en='1') then                                                      -- Clock enable
1635 
  if (idc_lpm_cml_1 or idc_elpm_cml_1) ='1' then
1636 
   program_counter_tmp <= program_counter_cml_1;
1637 
  end if;
1638 
 end if;
1639 
end if;
1640 
end process;
1641 
 
1642 
-- SynEDA CoreMultiplier
1643 
-- assignment(s): pa15_pm
1644 
-- replace(s): idc_elpm
1645 
 
1646 
pa15_pm <= rampz_out(0) and idc_elpm_cml_1; -- '0' WHEN LPM INSTRUCTIONS  RAMPZ(0) WHEN ELPM INSTRUCTION
1647 
 
1648 
-- OFFSET FOR BRBC/BRBS INSTRUCTIONS +63/-64
1649 
offset_brbx <= "0000000000"&dex_brxx_offset(5 downto 0) when (dex_brxx_offset(6)='0') else -- +
1650 
               "1111111111"&dex_brxx_offset(5 downto 0);                                   -- -
1651 
 
1652 
-- OFFSET FOR RJMP/RCALL INSTRUCTIONS +2047/-2048
1653 
offset_rxx <= "00000"&dex_adr12mem_s(10 downto 0) when (dex_adr12mem_s(11)='0') else       -- +
1654 
              "11111"&dex_adr12mem_s(10 downto 0);                                          -- -
1655 
 
1656 
program_counter <= pc_high&pc_low;
1657 
 
1658 
-- SynEDA CoreMultiplier
1659 
-- assignment(s): program_counter_in
1660 
-- replace(s): irqackad_int, program_counter_tmp, program_counter, irq_st1, call_st1, jmp_st1, ret_st1, ret_st2, reti_st1, reti_st2, lpm_st1, instruction_reg, idc_brbc, idc_brbs, idc_elpm, idc_icall, idc_ijmp, idc_lpm, idc_rcall, idc_rjmp
1661 
 
1662 
program_counter_in <= program_counter_cml_1 + offset_brbx when ((idc_brbc_cml_1 or idc_brbs_cml_1) and  bit_test_op_out) ='1'else  -- BRBC/BRBS
1663 
                      program_counter_cml_1 + offset_rxx when (idc_rjmp_cml_1 or idc_rcall_cml_1)='1'else     -- RJMP/RCALL
1664 
                      reg_z_out when (idc_ijmp_cml_1 or idc_icall_cml_1)='1'else                        -- IJMP/ICALL
1665 
                      pa15_pm&reg_z_out(15 downto 1) when (idc_lpm_cml_1 or idc_elpm_cml_1) ='1'else    -- LPM/ELPM
1666 
                      instruction_reg_cml_1  when (jmp_st1_cml_1 or call_st1_cml_1)='1'else                    -- JMP/CALL
1667 
                      "0000000000"&irqackad_int_cml_1&'0' when irq_st1_cml_1 ='1' else                 -- INTERRUPT
1668 
                      dbusin&"00000000"  when (ret_st1_cml_1 or reti_st1_cml_1)='1' else                 -- RET/RETI -> PC HIGH BYTE
1669 
                      "00000000"&dbusin  when (ret_st2_cml_1 or reti_st2_cml_1)='1' else                 -- RET/RETI -> PC LOW BYTE
1670 
                      program_counter_tmp_cml_1 when (lpm_st1_cml_1)='1'                                 -- AFTER LPM/ELPM INSTRUCTION
1671 
                      else program_counter_cml_1+1;      -- THE MOST USUAL CASE
1672 
 
1673 
 
1674 
 
1675 
-- SynEDA CoreMultiplier
1676 
-- assignment(s): pc_low_en
1677 
-- replace(s): cpuwait, irq_st2, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, sts_st, lds_st, idc_adiw, idc_cbi, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_pop, idc_push, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
1678 
 
1679 
pc_low_en  <= not (idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_y_cml_1 or idc_ldd_z_cml_1 or
1680 
                       idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1 or idc_std_y_cml_1 or idc_std_z_cml_1 or
1681 
                                   ((sts_st_cml_1 or lds_st_cml_1) and cpuwait_cml_1)or
1682 
                                   idc_adiw_cml_1 or idc_sbiw_cml_1 or
1683 
                                   idc_push_cml_1 or idc_pop_cml_1 or
1684 
                                   idc_cbi_cml_1 or idc_sbi_cml_1 or
1685 
                                   rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1 or irq_st2_cml_1 or cpuwait_cml_1 or
1686 
                                   ret_st1_cml_1 or reti_st1_cml_1);
1687 
 
1688 
 
1689 
-- SynEDA CoreMultiplier
1690 
-- assignment(s): pc_high_en
1691 
-- replace(s): cpuwait, irq_st2, call_st2, rcall_st1, icall_st1, ret_st2, reti_st2, sts_st, lds_st, idc_adiw, idc_cbi, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_pop, idc_push, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
1692 
 
1693 
pc_high_en <= not (idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_y_cml_1 or idc_ldd_z_cml_1 or
1694 
                       idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1 or idc_std_y_cml_1 or idc_std_z_cml_1 or
1695 
                                   ((sts_st_cml_1 or lds_st_cml_1) and cpuwait_cml_1) or
1696 
                                   idc_adiw_cml_1 or idc_sbiw_cml_1 or
1697 
                                   idc_push_cml_1 or idc_pop_cml_1 or
1698 
                                   idc_cbi_cml_1 or idc_sbi_cml_1 or
1699 
                                   rcall_st1_cml_1 or icall_st1_cml_1 or call_st2_cml_1 or irq_st2_cml_1 or cpuwait_cml_1 or
1700 
                                   ret_st2_cml_1 or reti_st2_cml_1);
1701 
 
1702 
-- SynEDA CoreMultiplier
1703 
-- assignment(s): pc_low
1704 
-- replace(s): pc_low
1705 
 
1706 
program_counter_low:process(cp2,ireset)
1707 
begin
1708 
if ireset='0' then                              -- RESET
1709 
pc_low<=(others => '0');
1710 
elsif (cp2='1' and cp2'event) then pc_low <= pc_low_cml_1;              -- CLOCK
1711 
 if (cp2en='1') then                                                    -- Clock enable
1712 
  if pc_low_en ='1' then
1713 
   pc_low <= program_counter_in(7 downto 0);
1714 
  end if;
1715 
 end if;
1716 
end if;
1717 
end process;
1718 
 
1719 
-- SynEDA CoreMultiplier
1720 
-- assignment(s): pc_high
1721 
-- replace(s): pc_high
1722 
 
1723 
program_counter_high:process(cp2,ireset)
1724 
begin
1725 
if ireset='0' then                               -- RESET
1726 
pc_high<=(others => '0');
1727 
elsif (cp2='1' and cp2'event) then pc_high <= pc_high_cml_1;               -- CLOCK
1728 
 if (cp2en='1') then                                                     -- Clock enable
1729 
  if pc_high_en ='1' then
1730 
   pc_high <= program_counter_in(15 downto 8);
1731 
  end if;
1732 
 end if;
1733 
end if;
1734 
end process;
1735 
 
1736 
pc <= program_counter;
1737 
 
1738 
 
1739 
-- SynEDA CoreMultiplier
1740 
-- assignment(s): pc_for_interrupt
1741 
-- replace(s): program_counter, pc_for_interrupt
1742 
 
1743 
program_counter_for_interrupt:process(cp2,ireset)
1744 
begin
1745 
if ireset='0' then                                 -- RESET
1746 
pc_for_interrupt <=(others => '0');
1747 
elsif (cp2='1' and cp2'event) then pc_for_interrupt <= pc_for_interrupt_cml_1;               -- CLOCK
1748 
 if (cp2en='1') then                                                     -- Clock enable
1749 
  if irq_start ='1' then
1750 
   pc_for_interrupt <= program_counter_cml_1;
1751 
  end if;
1752 
 end if;
1753 
end if;
1754 
end process;
1755 
 
1756 
-- END OF PROGRAM COUNTER
1757 
 
1758 
-- STATE MACHINES
1759 
 
1760 
-- SynEDA CoreMultiplier
1761 
-- assignment(s): skip_inst_start
1762 
-- replace(s): idc_cpse, idc_sbic, idc_sbis, idc_sbrc, idc_sbrs
1763 
 
1764 
skip_inst_start <= ((idc_sbrc_cml_1 or idc_sbrs_cml_1 or idc_sbic_cml_1 or idc_sbis_cml_1) and bit_test_op_out)or
1765 
                   (idc_cpse_cml_1 and alu_z_flag_out);
1766 
 
1767 
-- SynEDA CoreMultiplier
1768 
-- assignment(s): nskip_inst_st0, skip_inst_st1, skip_inst_st2
1769 
-- replace(s): nskip_inst_st0, skip_inst_st1, skip_inst_st2
1770 
 
1771 
skip_instruction_sm:process(cp2,ireset)
1772 
begin
1773 
if ireset='0' then                       -- RESET
1774 
nskip_inst_st0 <= '0';
1775 
skip_inst_st1  <= '0';
1776 
skip_inst_st2  <= '0';
1777 
elsif (cp2='1' and cp2'event) then skip_inst_st2 <= skip_inst_st2_cml_1; skip_inst_st1 <= skip_inst_st1_cml_1; nskip_inst_st0 <= nskip_inst_st0_cml_1;       -- CLOCK
1778 
 if (cp2en='1') then                                 -- Clock enable
1779 
  nskip_inst_st0 <= (not nskip_inst_st0_cml_1 and skip_inst_start) or
1780 
                    (nskip_inst_st0_cml_1 and not((skip_inst_st1_cml_1 and not two_word_inst) or skip_inst_st2_cml_1));
1781 
  skip_inst_st1  <= (not skip_inst_st1_cml_1 and not nskip_inst_st0_cml_1 and skip_inst_start);
1782 
  skip_inst_st2  <=  not skip_inst_st2_cml_1 and skip_inst_st1_cml_1 and two_word_inst;
1783 
 end if;
1784 
end if;
1785 
end process;
1786 
 
1787 
 
1788 
 
1789 
-- SynEDA CoreMultiplier
1790 
-- assignment(s): adiw_st, sbiw_st
1791 
-- replace(s): adiw_st, idc_adiw, sbiw_st, idc_sbiw
1792 
 
1793 
alu_state_machines:process(cp2,ireset)
1794 
begin
1795 
if ireset='0' then                       -- RESET
1796 
adiw_st <= '0';
1797 
sbiw_st <= '0';
1798 
elsif (cp2='1' and cp2'event) then sbiw_st <= sbiw_st_cml_1; adiw_st <= adiw_st_cml_1;       -- CLOCK
1799 
 if (cp2en='1') then                                     -- Clock enable
1800 
  adiw_st <= not adiw_st_cml_1 and idc_adiw_cml_1;
1801 
  sbiw_st <= not sbiw_st_cml_1 and idc_sbiw_cml_1;
1802 
 end if;
1803 
end if;
1804 
end process;
1805 
 
1806 
 
1807 
-- SynEDA CoreMultiplier
1808 
-- assignment(s): nlpm_st0, lpm_st1, lpm_st2
1809 
-- replace(s): nlpm_st0, lpm_st2, idc_elpm, idc_lpm, lpm_st1
1810 
 
1811 
lpm_state_machine:process(cp2,ireset)
1812 
begin
1813 
if ireset='0' then                       -- RESET
1814 
nlpm_st0 <= '0';
1815 
lpm_st1 <= '0';
1816 
lpm_st2 <= '0';
1817 
elsif (cp2='1' and cp2'event) then lpm_st2 <= lpm_st2_cml_1; lpm_st1 <= lpm_st1_cml_1; nlpm_st0 <= nlpm_st0_cml_1;       -- CLOCK
1818 
 if (cp2en='1') then                                                      -- Clock enable
1819 
  nlpm_st0 <= (not nlpm_st0_cml_1 and (idc_lpm_cml_1 or idc_elpm_cml_1)) or (nlpm_st0_cml_1 and not lpm_st2_cml_1);
1820 
  lpm_st1  <= (not lpm_st1_cml_1 and not nlpm_st0_cml_1 and (idc_lpm_cml_1 or idc_elpm_cml_1)); -- ??
1821 
  lpm_st2  <=  not lpm_st2_cml_1 and lpm_st1_cml_1;
1822 
 end if;
1823 
end if;
1824 
end process;
1825 
 
1826 
 
1827 
-- SynEDA CoreMultiplier
1828 
-- assignment(s): lds_st
1829 
-- replace(s): cpuwait, lds_st, idc_lds
1830 
 
1831 
lds_state_machine:process(cp2,ireset)
1832 
begin
1833 
if ireset='0' then                       -- RESET
1834 
 lds_st <= '0';
1835 
elsif (cp2='1' and cp2'event) then lds_st <= lds_st_cml_1;       -- CLOCK
1836 
 if (cp2en='1') then                                                      -- Clock enable
1837 
  lds_st  <= (not lds_st_cml_1 and idc_lds_cml_1) or (lds_st_cml_1 and cpuwait_cml_1);
1838 
 end if;
1839 
end if;
1840 
end process;
1841 
 
1842 
 
1843 
-- SynEDA CoreMultiplier
1844 
-- assignment(s): sts_st
1845 
-- replace(s): cpuwait, sts_st, idc_sts
1846 
 
1847 
sts_state_machine:process(cp2,ireset)
1848 
begin
1849 
if ireset='0' then                       -- RESET
1850 
 sts_st <= '0';
1851 
elsif (cp2='1' and cp2'event) then sts_st <= sts_st_cml_1;       -- CLOCK
1852 
 if (cp2en='1') then                                                      -- Clock enable
1853 
  sts_st  <= (not sts_st_cml_1 and idc_sts_cml_1) or (sts_st_cml_1 and cpuwait_cml_1);
1854 
 end if;
1855 
end if;
1856 
end process;
1857 
 
1858 
-- SynEDA CoreMultiplier
1859 
-- assignment(s): njmp_st0, jmp_st1, jmp_st2
1860 
-- replace(s): njmp_st0, jmp_st2, jmp_st1
1861 
 
1862 
jmp_state_machine:process(cp2,ireset)
1863 
begin
1864 
if ireset='0' then                       -- RESET
1865 
njmp_st0 <= '0';
1866 
jmp_st1 <= '0';
1867 
jmp_st2 <= '0';
1868 
elsif (cp2='1' and cp2'event) then jmp_st2 <= jmp_st2_cml_1; jmp_st1 <= jmp_st1_cml_1; njmp_st0 <= njmp_st0_cml_1;       -- CLOCK
1869 
 if (cp2en='1') then                                                      -- Clock enable
1870 
  njmp_st0 <= (not njmp_st0_cml_1 and idc_jmp) or (njmp_st0_cml_1 and not jmp_st2_cml_1);
1871 
  jmp_st1  <= not jmp_st1_cml_1 and not njmp_st0_cml_1 and idc_jmp; -- ??
1872 
  jmp_st2  <= not jmp_st2_cml_1 and jmp_st1_cml_1;
1873 
 end if;
1874 
end if;
1875 
end process;
1876 
 
1877 
-- SynEDA CoreMultiplier
1878 
-- assignment(s): nrcall_st0, rcall_st1, rcall_st2
1879 
-- replace(s): cpuwait, nrcall_st0, rcall_st2, idc_rcall, rcall_st1
1880 
 
1881 
rcall_state_machine:process(cp2,ireset)
1882 
begin
1883 
if ireset='0' then                       -- RESET
1884 
nrcall_st0 <= '0';
1885 
rcall_st1 <= '0';
1886 
rcall_st2 <= '0';
1887 
elsif (cp2='1' and cp2'event) then rcall_st2 <= rcall_st2_cml_1; rcall_st1 <= rcall_st1_cml_1; nrcall_st0 <= nrcall_st0_cml_1;       -- CLOCK
1888 
 if (cp2en='1') then                                                      -- Clock enable
1889 
  nrcall_st0 <= (not nrcall_st0_cml_1 and idc_rcall_cml_1) or (nrcall_st0_cml_1 and not (rcall_st2_cml_1 and not cpuwait_cml_1));
1890 
  rcall_st1  <= (not rcall_st1_cml_1 and not nrcall_st0_cml_1 and idc_rcall_cml_1) or (rcall_st1_cml_1 and cpuwait_cml_1);
1891 
  rcall_st2  <= (not rcall_st2_cml_1 and rcall_st1_cml_1 and not cpuwait_cml_1) or (rcall_st2_cml_1 and cpuwait_cml_1);
1892 
 end if;
1893 
end if;
1894 
end process;
1895 
 
1896 
-- SynEDA CoreMultiplier
1897 
-- assignment(s): nicall_st0, icall_st1, icall_st2
1898 
-- replace(s): cpuwait, nicall_st0, icall_st2, idc_icall, icall_st1
1899 
 
1900 
icall_state_machine:process(cp2,ireset)
1901 
begin
1902 
if ireset='0' then                       -- RESET
1903 
nicall_st0 <= '0';
1904 
icall_st1 <= '0';
1905 
icall_st2 <= '0';
1906 
elsif (cp2='1' and cp2'event) then icall_st2 <= icall_st2_cml_1; icall_st1 <= icall_st1_cml_1; nicall_st0 <= nicall_st0_cml_1;       -- CLOCK
1907 
 if (cp2en='1') then                                                      -- Clock enable
1908 
  nicall_st0 <= (not nicall_st0_cml_1 and idc_icall_cml_1) or (nicall_st0_cml_1 and not (icall_st2_cml_1 and not cpuwait_cml_1));
1909 
  icall_st1  <= (not icall_st1_cml_1 and not nicall_st0_cml_1 and idc_icall_cml_1) or (icall_st1_cml_1 and cpuwait_cml_1);
1910 
  icall_st2  <= (not icall_st2_cml_1 and icall_st1_cml_1 and not cpuwait_cml_1) or (icall_st2_cml_1 and cpuwait_cml_1);
1911 
 end if;
1912 
end if;
1913 
end process;
1914 
 
1915 
-- SynEDA CoreMultiplier
1916 
-- assignment(s): ncall_st0, call_st1, call_st2, call_st3
1917 
-- replace(s): cpuwait, ncall_st0, call_st3, call_st1, call_st2
1918 
 
1919 
call_state_machine:process(cp2,ireset)
1920 
begin
1921 
if ireset='0' then                       -- RESET
1922 
ncall_st0 <= '0';
1923 
call_st1 <= '0';
1924 
call_st2 <= '0';
1925 
call_st3  <= '0';
1926 
elsif (cp2='1' and cp2'event) then call_st3 <= call_st3_cml_1; call_st2 <= call_st2_cml_1; call_st1 <= call_st1_cml_1; ncall_st0 <= ncall_st0_cml_1;       -- CLOCK
1927 
 if (cp2en='1') then                                                      -- Clock enable
1928 
  ncall_st0 <= (not ncall_st0_cml_1 and idc_call) or (ncall_st0_cml_1 and not( call_st3_cml_1 and not cpuwait_cml_1));
1929 
  call_st1  <= not call_st1_cml_1 and not ncall_st0_cml_1 and idc_call;
1930 
  call_st2  <= (not call_st2_cml_1 and call_st1_cml_1) or (call_st2_cml_1 and cpuwait_cml_1);
1931 
  call_st3  <= (not call_st3_cml_1 and call_st2_cml_1 and not cpuwait_cml_1) or (call_st3_cml_1 and cpuwait_cml_1);
1932 
 end if;
1933 
end if;
1934 
end process;
1935 
 
1936 
-- SynEDA CoreMultiplier
1937 
-- assignment(s): nret_st0, ret_st1, ret_st2, ret_st3
1938 
-- replace(s): nret_st0, ret_st3, idc_ret, cpuwait, ret_st1, ret_st2
1939 
 
1940 
ret_state_machine:process(cp2,ireset)
1941 
begin
1942 
if ireset='0' then                       -- RESET
1943 
nret_st0 <= '0';
1944 
ret_st1 <= '0';
1945 
ret_st2 <= '0';
1946 
ret_st3  <= '0';
1947 
elsif (cp2='1' and cp2'event) then ret_st3 <= ret_st3_cml_1; ret_st2 <= ret_st2_cml_1; ret_st1 <= ret_st1_cml_1; nret_st0 <= nret_st0_cml_1;       -- CLOCK
1948 
 if (cp2en='1') then                                                      -- Clock enable
1949 
  nret_st0 <= (not nret_st0_cml_1 and idc_ret_cml_1) or (nret_st0_cml_1 and not ret_st3_cml_1);
1950 
  ret_st1  <= (not ret_st1_cml_1 and not nret_st0_cml_1 and idc_ret_cml_1) or (ret_st1_cml_1 and cpuwait_cml_1);
1951 
  ret_st2  <= (not ret_st2_cml_1 and ret_st1_cml_1 and not cpuwait_cml_1) or (ret_st2_cml_1 and cpuwait_cml_1) ;
1952 
  ret_st3  <= not ret_st3_cml_1 and ret_st2_cml_1 and not cpuwait_cml_1;
1953 
 end if;
1954 
end if;
1955 
end process;
1956 
 
1957 
-- SynEDA CoreMultiplier
1958 
-- assignment(s): nreti_st0, reti_st1, reti_st2, reti_st3
1959 
-- replace(s): nreti_st0, reti_st3, idc_reti, cpuwait, reti_st1, reti_st2
1960 
 
1961 
reti_state_machine:process(cp2,ireset)
1962 
begin
1963 
if ireset='0' then                       -- RESET
1964 
nreti_st0 <= '0';
1965 
reti_st1 <= '0';
1966 
reti_st2 <= '0';
1967 
reti_st3  <= '0';
1968 
elsif (cp2='1' and cp2'event) then reti_st3 <= reti_st3_cml_1; reti_st2 <= reti_st2_cml_1; reti_st1 <= reti_st1_cml_1; nreti_st0 <= nreti_st0_cml_1;       -- CLOCK
1969 
 if (cp2en='1') then                                                      -- Clock enable
1970 
  nreti_st0 <= (not nreti_st0_cml_1 and idc_reti_cml_1) or (nreti_st0_cml_1 and not reti_st3_cml_1);
1971 
  reti_st1  <= (not reti_st1_cml_1 and not nreti_st0_cml_1 and idc_reti_cml_1) or (reti_st1_cml_1 and cpuwait_cml_1);
1972 
  reti_st2  <= (not reti_st2_cml_1 and reti_st1_cml_1 and not cpuwait_cml_1) or (reti_st2_cml_1 and cpuwait_cml_1) ;
1973 
  reti_st3  <= not reti_st3_cml_1 and reti_st2_cml_1 and not cpuwait_cml_1;
1974 
 end if;
1975 
end if;
1976 
end process;
1977 
 
1978 
 
1979 
-- INTERRUPT LOGIC AND STATE MACHINE
1980 
 
1981 
-- SynEDA CoreMultiplier
1982 
-- assignment(s): irq_int
1983 
-- replace(s): irqlines
1984 
 
1985 
irq_int <= '0' when      irqlines_cml_1="00000000000000000000000" else '1';
1986 
 
1987 
irq_vector_adr(15 downto 6)<=(others => '0');
1988 
irq_vector_adr(0) <= '0';
1989 
-- SynEDA CoreMultiplier
1990 
-- assignment(s): irq_vector_adr
1991 
-- replace(s): irqlines
1992 
 
1993 
-- PRIORITY ENCODER
1994 
irq_vector_adr(5 downto 1) <= "00001" when irqlines_cml_1(0)='1'  else -- 0x0002
1995 
                              "00010" when irqlines_cml_1(1)='1'  else -- 0x0004
1996 
                              "00011" when irqlines_cml_1(2)='1'  else -- 0x0006
1997 
                              "00100" when irqlines_cml_1(3)='1'  else -- 0x0008
1998 
                              "00101" when irqlines_cml_1(4)='1'  else -- 0x000A
1999 
                              "00110" when irqlines_cml_1(5)='1'  else -- 0x000C
2000 
                              "00111" when irqlines_cml_1(6)='1'  else -- 0x000E
2001 
                              "01000" when irqlines_cml_1(7)='1'  else -- 0x0010
2002 
                              "01001" when irqlines_cml_1(8)='1'  else -- 0x0012
2003 
                              "01010" when irqlines_cml_1(9)='1'  else -- 0x0014
2004 
                              "01011" when irqlines_cml_1(10)='1' else -- 0x0016
2005 
                              "01100" when irqlines_cml_1(11)='1' else -- 0x0018
2006 
                              "01101" when irqlines_cml_1(12)='1' else -- 0x001A
2007 
                              "01110" when irqlines_cml_1(13)='1' else -- 0x001C
2008 
                              "01111" when irqlines_cml_1(14)='1' else -- 0x001E
2009 
                              "10000" when irqlines_cml_1(15)='1' else -- 0x0020
2010 
                              "10001" when irqlines_cml_1(16)='1' else -- 0x0022
2011 
                              "10010" when irqlines_cml_1(17)='1' else -- 0x0024
2012 
                              "10011" when irqlines_cml_1(18)='1' else -- 0x0026
2013 
                              "10100" when irqlines_cml_1(19)='1' else -- 0x0028
2014 
                              "10101" when irqlines_cml_1(20)='1' else -- 0x002A
2015 
                              "10110" when irqlines_cml_1(21)='1' else -- 0x002C
2016 
                              "10111" when irqlines_cml_1(22)='1' else -- 0x002E
2017 
                                                          "00000";
2018 
 
2019 
-- SynEDA CoreMultiplier
2020 
-- assignment(s): cpu_busy
2021 
-- replace(s): cpuwait, nirq_st0, call_st1, call_st2, call_st3, rcall_st1, rcall_st2, icall_st1, icall_st2, jmp_st1, ret_st1, ret_st2, reti_st1, reti_st2, skip_inst_st1, lpm_st1, sts_st, lds_st, st_st, ld_st, push_st, pop_st, idc_adiw, idc_brbc, idc_brbs, idc_cbi, idc_icall, idc_ijmp, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_lds, idc_lpm, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti, idc_rjmp, idc_sbi, idc_sbiw, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, idc_sts
2022 
 
2023 
-- MULTI CYCLE INSTRUCTION FLAG FOR IRQ
2024 
cpu_busy <= idc_adiw_cml_1 or idc_sbiw_cml_1 or idc_cbi_cml_1 or idc_sbi_cml_1 or
2025 
            idc_rjmp_cml_1 or idc_ijmp_cml_1 or
2026 
                        idc_jmp or jmp_st1_cml_1 or
2027 
--                      idc_brbs or idc_brbc or -- Old variant
2028 
            ((idc_brbc_cml_1 or idc_brbs_cml_1) and  bit_test_op_out) or
2029 
                        idc_lpm_cml_1 or lpm_st1_cml_1 or
2030 
                        skip_inst_start or (skip_inst_st1_cml_1 and two_word_inst) or
2031 
                        idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1 or (ld_st_cml_1 and cpuwait_cml_1) or
2032 
                        idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1 or (st_st_cml_1 and cpuwait_cml_1) or
2033 
                        idc_lds_cml_1 or (lds_st_cml_1 and cpuwait_cml_1) or
2034 
                        idc_sts_cml_1 or (sts_st_cml_1 and cpuwait_cml_1) or
2035 
                        idc_rcall_cml_1 or rcall_st1_cml_1 or (rcall_st2_cml_1 and cpuwait_cml_1) or           -- RCALL
2036 
                        idc_icall_cml_1 or icall_st1_cml_1 or (icall_st2_cml_1 and cpuwait_cml_1) or               -- ICALL
2037 
                        idc_call or call_st1_cml_1 or call_st2_cml_1 or (call_st3_cml_1 and cpuwait_cml_1) or  -- CALL
2038 
                        idc_push_cml_1 or (push_st_cml_1 and cpuwait_cml_1) or                           -- PUSH (added 14.07.05)
2039 
                        idc_pop_cml_1 or (pop_st_cml_1 and cpuwait_cml_1) or                             -- POP  (added 14.07.05)
2040 
                    (idc_bclr and sreg_bop_wr_en(7)) or                 -- ??? CLI
2041 
                    (iowe_int and sreg_adr_eq and not dbusout_int(7))or -- ??? Writing '0' to I flag (OUT/STD/ST/STD)
2042 
                        nirq_st0_cml_1 or
2043 
--                      idc_ret  or nret_st0 or                             -- Old variant
2044 
                        idc_ret_cml_1 or ret_st1_cml_1 or ret_st2_cml_1 or
2045 
--                      idc_reti or nreti_st0;                              -- At least one instruction must be executed after RETI and before the new interrupt.
2046 
                        idc_reti_cml_1 or reti_st1_cml_1 or reti_st2_cml_1;
2047 
 
2048 
-- SynEDA CoreMultiplier
2049 
-- assignment(s): sreg_adr_eq
2050 
-- replace(s): adr_int
2051 
 
2052 
sreg_adr_eq <= '1' when adr_int_cml_1=SREG_Address else '0';
2053 
 
2054 
--irq_start <= irq_int and not cpu_busy and globint;
2055 
irq_start <= irq_int and not cpu_busy and globint;
2056 
 
2057 
-- SynEDA CoreMultiplier
2058 
-- assignment(s): nirq_st0, irq_st1, irq_st2, irq_st3
2059 
-- replace(s): cpuwait, nirq_st0, irq_st3, irq_st1, irq_st2
2060 
 
2061 
irq_state_machine:process(cp2,ireset)
2062 
begin
2063 
if ireset='0' then                       -- RESET
2064 
nirq_st0 <= '0';
2065 
irq_st1 <= '0';
2066 
irq_st2 <= '0';
2067 
irq_st3 <= '0';
2068 
elsif (cp2='1' and cp2'event) then irq_st3 <= irq_st3_cml_1; irq_st2 <= irq_st2_cml_1; irq_st1 <= irq_st1_cml_1; nirq_st0 <= nirq_st0_cml_1;       -- CLOCK
2069 
 if (cp2en='1') then                                                      -- Clock enable
2070 
  nirq_st0 <= (not nirq_st0_cml_1 and irq_start) or (nirq_st0_cml_1 and not (irq_st3_cml_1 and not cpuwait_cml_1));
2071 
  irq_st1  <= (not irq_st1_cml_1 and not nirq_st0_cml_1 and irq_start);
2072 
  irq_st2  <= (not irq_st2_cml_1 and irq_st1_cml_1) or (irq_st2_cml_1 and cpuwait_cml_1);
2073 
  irq_st3  <= (not irq_st3_cml_1 and irq_st2_cml_1 and not cpuwait_cml_1) or (irq_st3_cml_1 and cpuwait_cml_1);
2074 
 end if;
2075 
end if;
2076 
end process;
2077 
 
2078 
-- SynEDA CoreMultiplier
2079 
-- assignment(s): irqack_int
2080 
-- replace(s): irqack_int
2081 
 
2082 
irqack_reg:process(cp2,ireset)
2083 
begin
2084 
if ireset='0' then                       -- RESET
2085 
irqack_int<='0';
2086 
elsif (cp2='1' and cp2'event) then irqack_int <= irqack_int_cml_1;       -- CLOCK
2087 
 if (cp2en='1') then                                                      -- Clock enable
2088 
  irqack_int<= not irqack_int_cml_1 and irq_start;
2089 
 end if;
2090 
end if;
2091 
end process;
2092 
-- SynEDA CoreMultiplier
2093 
-- assignment(s): irqack
2094 
-- replace(s): irqack_int
2095 
 
2096 
irqack_cml_out <= irqack_int_cml_1;
2097 
 
2098 
-- SynEDA CoreMultiplier
2099 
-- assignment(s): irqackad_int
2100 
-- replace(s): irqackad_int
2101 
 
2102 
irqackad_reg:process(cp2,ireset)
2103 
begin
2104 
if ireset='0' then                                -- RESET
2105 
irqackad_int<=(others=>'0');
2106 
elsif (cp2='1' and cp2'event) then irqackad_int <= irqackad_int_cml_1;              -- CLOCK
2107 
 if (cp2en='1') then                                                      -- Clock enable
2108 
  irqackad_int <= irq_vector_adr(5 downto 1);
2109 
 end if;
2110 
end if;
2111 
end process;
2112 
-- SynEDA CoreMultiplier
2113 
-- assignment(s): irqackad
2114 
-- replace(s): irqackad_int
2115 
 
2116 
irqackad_cml_out <= irqackad_int_cml_1;
2117 
 
2118 
-- *******************************************************************************************
2119 
 
2120 
-- SynEDA CoreMultiplier
2121 
-- assignment(s): ijmp_st, rjmp_st, brxx_st, push_st, pop_st
2122 
-- replace(s): ijmp_st, idc_ijmp, rjmp_st, idc_rjmp, brxx_st, idc_brbc, idc_brbs, cpuwait, push_st, idc_push, pop_st, idc_pop
2123 
 
2124 
rjmp_push_pop_ijmp_state_brxx_machine:process(cp2,ireset)
2125 
begin
2126 
if ireset='0' then                       -- RESET
2127 
rjmp_st <= '0';
2128 
ijmp_st <= '0';
2129 
push_st <= '0';
2130 
pop_st <= '0';
2131 
brxx_st <= '0';
2132 
elsif (cp2='1' and cp2'event) then pop_st <= pop_st_cml_1; push_st <= push_st_cml_1; brxx_st <= brxx_st_cml_1; rjmp_st <= rjmp_st_cml_1; ijmp_st <= ijmp_st_cml_1;       -- CLOCK
2133 
 if (cp2en='1') then                                                      -- Clock enable
2134 
  rjmp_st <= idc_rjmp_cml_1;    -- ??
2135 
  ijmp_st <= idc_ijmp_cml_1;
2136 
  push_st <= (not push_st_cml_1 and idc_push_cml_1) or (push_st_cml_1 and cpuwait_cml_1);
2137 
  pop_st  <= (not pop_st_cml_1  and idc_pop_cml_1) or (pop_st_cml_1 and cpuwait_cml_1);
2138 
  brxx_st <= not brxx_st_cml_1 and (idc_brbc_cml_1 or idc_brbs_cml_1) and bit_test_op_out;
2139 
 end if;
2140 
end if;
2141 
end process;
2142 
 
2143 
-- SynEDA CoreMultiplier
2144 
-- assignment(s): st_st, ld_st
2145 
-- replace(s): cpuwait, st_st, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z, ld_st, idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z
2146 
 
2147 
-- LD/LDD/ST/STD
2148 
ld_st_state_machine:process(cp2,ireset)
2149 
begin
2150 
if ireset='0' then                       -- RESET
2151 
ld_st <= '0';
2152 
st_st <= '0';
2153 
elsif (cp2='1' and cp2'event) then ld_st <= ld_st_cml_1; st_st <= st_st_cml_1;       -- CLOCK
2154 
 if (cp2en='1') then                                                      -- Clock enable
2155 
  ld_st <= (not ld_st_cml_1 and (idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1)) or (ld_st_cml_1 and cpuwait_cml_1);
2156 
  st_st <= (not st_st_cml_1 and (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_std_y_cml_1 or idc_st_z_cml_1 or idc_std_z_cml_1)) or (st_st_cml_1 and cpuwait_cml_1);
2157 
 end if;
2158 
end if;
2159 
end process;
2160 
 
2161 
-- SynEDA CoreMultiplier
2162 
-- assignment(s): sbi_st, cbi_st, cbi_sbi_io_adr_tmp, cbi_sbi_bit_num_tmp
2163 
-- replace(s): sbi_st, idc_sbi, cbi_st, idc_cbi, dex_adr5port, cbi_sbi_io_adr_tmp, dex_bitop_bitnum, cbi_sbi_bit_num_tmp
2164 
 
2165 
-- SBI/CBI
2166 
sbi_cbi_machine:process(cp2,ireset)
2167 
begin
2168 
if ireset='0' then                       -- RESET
2169 
sbi_st <= '0';
2170 
cbi_st <= '0';
2171 
cbi_sbi_io_adr_tmp  <= (others => '0');
2172 
cbi_sbi_bit_num_tmp     <= (others => '0');
2173 
elsif (cp2='1' and cp2'event) then cbi_sbi_bit_num_tmp <= cbi_sbi_bit_num_tmp_cml_1; cbi_sbi_io_adr_tmp <= cbi_sbi_io_adr_tmp_cml_1; cbi_st <= cbi_st_cml_1; sbi_st <= sbi_st_cml_1;       -- CLOCK
2174 
 if (cp2en='1') then                                                      -- Clock enable
2175 
  sbi_st <= not sbi_st_cml_1 and idc_sbi_cml_1;
2176 
  cbi_st <= not cbi_st_cml_1 and idc_cbi_cml_1;
2177 
  cbi_sbi_io_adr_tmp <= dex_adr5port_cml_1;
2178 
  cbi_sbi_bit_num_tmp <= dex_bitop_bitnum_cml_1;
2179 
 end if;
2180 
end if;
2181 
end process;
2182 
 
2183 
-- ########################################################################################
2184 
 
2185 
-- SREG FLAGS WRITE ENABLE LOGIC
2186 
 
2187 
--bclr_bset_op_en_logic:for i in sreg_bop_wr_en'range generate
2188 
--sreg_bop_wr_en(i) <= '1' when (dex_bitnum_sreg=i and (idc_bclr or idc_bset)='1') else '0';
2189 
--end generate;
2190 
 
2191 
sreg_bop_wr_en(0) <= '1' when (dex_bitnum_sreg=0 and (idc_bclr or idc_bset)='1') else '0';
2192 
sreg_bop_wr_en(1) <= '1' when (dex_bitnum_sreg=1 and (idc_bclr or idc_bset)='1') else '0';
2193 
sreg_bop_wr_en(2) <= '1' when (dex_bitnum_sreg=2 and (idc_bclr or idc_bset)='1') else '0';
2194 
sreg_bop_wr_en(3) <= '1' when (dex_bitnum_sreg=3 and (idc_bclr or idc_bset)='1') else '0';
2195 
sreg_bop_wr_en(4) <= '1' when (dex_bitnum_sreg=4 and (idc_bclr or idc_bset)='1') else '0';
2196 
sreg_bop_wr_en(5) <= '1' when (dex_bitnum_sreg=5 and (idc_bclr or idc_bset)='1') else '0';
2197 
sreg_bop_wr_en(6) <= '1' when (dex_bitnum_sreg=6 and (idc_bclr or idc_bset)='1') else '0';
2198 
sreg_bop_wr_en(7) <= '1' when (dex_bitnum_sreg=7 and (idc_bclr or idc_bset)='1') else '0';
2199 
 
2200 
-- SynEDA CoreMultiplier
2201 
-- assignment(s): sreg_c_wr_en
2202 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_adiw, idc_cp, idc_cpc, idc_cpi, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi
2203 
 
2204 
sreg_c_wr_en <= idc_add or idc_adc_cml_1 or (idc_adiw_cml_1 or adiw_st_cml_1) or idc_sub_cml_1  or idc_subi_cml_1 or
2205 
                idc_sbc_cml_1 or idc_sbci_cml_1 or (idc_sbiw_cml_1 or sbiw_st_cml_1) or idc_com or idc_neg or
2206 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2207 
                idc_lsr or idc_ror_cml_1 or idc_asr or sreg_bop_wr_en(0);
2208 
 
2209 
-- SynEDA CoreMultiplier
2210 
-- assignment(s): sreg_z_wr_en
2211 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_adiw, idc_andi, idc_cp, idc_cpc, idc_cpi, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sbiw, idc_sub, idc_subi
2212 
 
2213 
sreg_z_wr_en <= idc_add or idc_adc_cml_1 or (idc_adiw_cml_1 or adiw_st_cml_1) or idc_sub_cml_1  or idc_subi_cml_1 or
2214 
                idc_sbc_cml_1 or idc_sbci_cml_1 or (idc_sbiw_cml_1 or sbiw_st_cml_1) or
2215 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2216 
                idc_and or idc_andi_cml_1 or idc_or or idc_ori_cml_1 or idc_eor or idc_com or idc_neg or
2217 
                idc_inc or idc_dec or idc_lsr or idc_ror_cml_1 or idc_asr or sreg_bop_wr_en(1);
2218 
 
2219 
 
2220 
-- SynEDA CoreMultiplier
2221 
-- assignment(s): sreg_n_wr_en
2222 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_andi, idc_cp, idc_cpc, idc_cpi, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi
2223 
 
2224 
sreg_n_wr_en <= idc_add or idc_adc_cml_1 or adiw_st_cml_1 or idc_sub_cml_1  or idc_subi_cml_1 or
2225 
                idc_sbc_cml_1 or idc_sbci_cml_1 or sbiw_st_cml_1 or
2226 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2227 
                idc_and or idc_andi_cml_1 or idc_or or idc_ori_cml_1 or idc_eor or idc_com or idc_neg or
2228 
                idc_inc or idc_dec or idc_lsr or idc_ror_cml_1 or idc_asr or sreg_bop_wr_en(2);
2229 
 
2230 
-- SynEDA CoreMultiplier
2231 
-- assignment(s): sreg_v_wr_en
2232 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_andi, idc_cp, idc_cpc, idc_cpi, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi
2233 
 
2234 
sreg_v_wr_en <= idc_add or idc_adc_cml_1 or adiw_st_cml_1 or idc_sub_cml_1  or idc_subi_cml_1 or -- idc_adiw
2235 
                idc_sbc_cml_1 or idc_sbci_cml_1 or sbiw_st_cml_1 or idc_neg or idc_com or  -- idc_sbiw
2236 
                idc_inc or idc_dec or
2237 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2238 
                idc_lsr or idc_ror_cml_1 or idc_asr or sreg_bop_wr_en(3) or
2239 
                                idc_and or idc_andi_cml_1 or idc_or or idc_ori_cml_1 or idc_eor; -- V-flag bug fixing
2240 
 
2241 
-- SynEDA CoreMultiplier
2242 
-- assignment(s): sreg_s_wr_en
2243 
-- replace(s): adiw_st, sbiw_st, idc_adc, idc_andi, idc_cp, idc_cpc, idc_cpi, idc_ori, idc_ror, idc_sbc, idc_sbci, idc_sub, idc_subi
2244 
 
2245 
sreg_s_wr_en <= idc_add or idc_adc_cml_1 or adiw_st_cml_1 or idc_sub_cml_1 or idc_subi_cml_1 or
2246 
                idc_sbc_cml_1 or idc_sbci_cml_1 or sbiw_st_cml_1 or
2247 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2248 
                                idc_and or idc_andi_cml_1 or idc_or or idc_ori_cml_1 or idc_eor or idc_com or idc_neg or
2249 
                                idc_inc or idc_dec or idc_lsr or idc_ror_cml_1 or idc_asr or sreg_bop_wr_en(4);
2250 
 
2251 
-- SynEDA CoreMultiplier
2252 
-- assignment(s): sreg_h_wr_en
2253 
-- replace(s): idc_adc, idc_cp, idc_cpc, idc_cpi, idc_sbc, idc_sbci, idc_sub, idc_subi
2254 
 
2255 
sreg_h_wr_en <= idc_add or idc_adc_cml_1 or idc_sub_cml_1  or idc_subi_cml_1 or
2256 
                                idc_cp_cml_1 or idc_cpc_cml_1 or idc_cpi_cml_1 or
2257 
                idc_sbc_cml_1 or idc_sbci_cml_1 or idc_neg or sreg_bop_wr_en(5);
2258 
 
2259 
sreg_t_wr_en <=  idc_bst or sreg_bop_wr_en(6);
2260 
 
2261 
-- SynEDA CoreMultiplier
2262 
-- assignment(s): sreg_i_wr_en
2263 
-- replace(s): irq_st1, reti_st3
2264 
 
2265 
sreg_i_wr_en <= irq_st1_cml_1 or reti_st3_cml_1 or sreg_bop_wr_en(7); -- WAS "irq_start"
2266 
 
2267 
-- SynEDA CoreMultiplier
2268 
-- assignment(s): sreg_fl_in
2269 
-- replace(s): reti_st3
2270 
 
2271 
sreg_fl_in_cml_out <=  bit_pr_sreg_out when (idc_bst or idc_bclr or idc_bset)='1' else                     -- TO THE SREG
2272 
reti_st3_cml_1&'0'&alu_h_flag_out&alu_s_flag_out&alu_v_flag_out&alu_n_flag_out&alu_z_flag_out&alu_c_flag_out;
2273 
 
2274 
-- #################################################################################################################
2275 
 
2276 
-- *********************************************************************************************
2277 
-- ************** INSTRUCTION DECODER OUTPUTS FOR THE OTHER BLOCKS  ****************************
2278 
-- *********************************************************************************************
2279 
 
2280 
-- FOR ALU
2281 
 
2282 
idc_add_out   <= idc_add;
2283 
idc_adc_out   <= idc_adc;
2284 
-- SynEDA CoreMultiplier
2285 
-- assignment(s): idc_adiw_out
2286 
-- replace(s): idc_adiw
2287 
 
2288 
idc_adiw_out_cml_out  <= idc_adiw_cml_1;
2289 
idc_sub_out   <= idc_sub;
2290 
idc_subi_out  <= idc_subi;
2291 
idc_sbc_out   <= idc_sbc;
2292 
idc_sbci_out  <= idc_sbci;
2293 
idc_sbiw_out  <= idc_sbiw;
2294 
adiw_st_out   <= adiw_st;
2295 
sbiw_st_out   <= sbiw_st;
2296 
idc_and_out   <= idc_and;
2297 
-- SynEDA CoreMultiplier
2298 
-- assignment(s): idc_andi_out
2299 
-- replace(s): idc_andi
2300 
 
2301 
idc_andi_out_cml_out  <= idc_andi_cml_1;
2302 
idc_or_out    <= idc_or;
2303 
-- SynEDA CoreMultiplier
2304 
-- assignment(s): idc_ori_out
2305 
-- replace(s): idc_ori
2306 
 
2307 
idc_ori_out_cml_out   <= idc_ori_cml_1;
2308 
idc_eor_out   <= idc_eor;
2309 
idc_com_out   <= idc_com;
2310 
idc_neg_out   <= idc_neg;
2311 
idc_inc_out   <= idc_inc;
2312 
idc_dec_out   <= idc_dec;
2313 
idc_cp_out    <= idc_cp;
2314 
idc_cpc_out   <= idc_cpc;
2315 
idc_cpi_out   <= idc_cpi;
2316 
idc_cpse_out  <= idc_cpse;
2317 
idc_lsr_out   <= idc_lsr;
2318 
idc_ror_out   <= idc_ror;
2319 
idc_asr_out   <= idc_asr;
2320 
idc_swap_out  <= idc_swap;
2321 
 
2322 
-- FOR THE BIT PROCESSOR
2323 
sbi_st_out   <= sbi_st;
2324 
cbi_st_out   <= cbi_st;
2325 
idc_bst_out  <= idc_bst;
2326 
idc_bset_out <= idc_bset;
2327 
idc_bclr_out <= idc_bclr;
2328 
-- SynEDA CoreMultiplier
2329 
-- assignment(s): idc_sbic_out
2330 
-- replace(s): idc_sbic
2331 
 
2332 
idc_sbic_out_cml_out <= idc_sbic_cml_1;
2333 
-- SynEDA CoreMultiplier
2334 
-- assignment(s): idc_sbis_out
2335 
-- replace(s): idc_sbis
2336 
 
2337 
idc_sbis_out_cml_out <= idc_sbis_cml_1;
2338 
-- SynEDA CoreMultiplier
2339 
-- assignment(s): idc_sbrs_out
2340 
-- replace(s): idc_sbrs
2341 
 
2342 
idc_sbrs_out_cml_out <= idc_sbrs_cml_1;
2343 
-- SynEDA CoreMultiplier
2344 
-- assignment(s): idc_sbrc_out
2345 
-- replace(s): idc_sbrc
2346 
 
2347 
idc_sbrc_out_cml_out <= idc_sbrc_cml_1;
2348 
-- SynEDA CoreMultiplier
2349 
-- assignment(s): idc_brbs_out
2350 
-- replace(s): idc_brbs
2351 
 
2352 
idc_brbs_out_cml_out <= idc_brbs_cml_1;
2353 
-- SynEDA CoreMultiplier
2354 
-- assignment(s): idc_brbc_out
2355 
-- replace(s): idc_brbc
2356 
 
2357 
idc_brbc_out_cml_out <= idc_brbc_cml_1;
2358 
-- SynEDA CoreMultiplier
2359 
-- assignment(s): idc_reti_out
2360 
-- replace(s): idc_reti
2361 
 
2362 
idc_reti_out_cml_out <= idc_reti_cml_1;
2363 
 
2364 
-- POST INCREMENT/PRE DECREMENT FOR THE X,Y,Z REGISTERS
2365 
post_inc <= idc_psinc;
2366 
-- SynEDA CoreMultiplier
2367 
-- assignment(s): pre_dec
2368 
-- replace(s): idc_prdec
2369 
 
2370 
pre_dec_cml_out  <= idc_prdec_cml_1;
2371 
-- SynEDA CoreMultiplier
2372 
-- assignment(s): reg_h_wr
2373 
-- replace(s): idc_ld_x, idc_ld_y, idc_ld_z, idc_st_x, idc_st_y, idc_st_z, idc_prdec
2374 
 
2375 
reg_h_wr_cml_out <= (idc_st_x_cml_1 or idc_st_y_cml_1 or idc_st_z_cml_1 or idc_ld_x_cml_1 or idc_ld_y_cml_1 or idc_ld_z_cml_1) and (idc_psinc or idc_prdec_cml_1);
2376 
 
2377 
reg_h_adr_cml_out(0)<= idc_st_x_cml_1 or idc_ld_x_cml_1;
2378 
reg_h_adr_cml_out(1)<= idc_st_y_cml_1 or idc_std_y_cml_1 or idc_ld_y_cml_1 or idc_ldd_y_cml_1;
2379 
-- SynEDA CoreMultiplier
2380 
-- assignment(s): reg_h_adr
2381 
-- replace(s): idc_ld_x, idc_ld_y, idc_ldd_y, idc_ld_z, idc_ldd_z, idc_st_x, idc_st_y, idc_std_y, idc_st_z, idc_std_z
2382 
 
2383 
reg_h_adr_cml_out(2)<= idc_st_z_cml_1 or idc_std_z_cml_1 or idc_ld_z_cml_1 or idc_ldd_z_cml_1;
2384 
 
2385 
-- SynEDA CoreMultiplier
2386 
-- assignment(s): sp_en
2387 
-- replace(s): cpuwait, irq_st1, irq_st2, call_st1, call_st2, rcall_st1, icall_st1, ret_st1, reti_st1, idc_icall, idc_pop, idc_push, idc_rcall, idc_ret, idc_reti
2388 
 
2389 
-- SynEDA CoreMultiplier
2390 
-- assignment(s): sp_ndown_up
2391 
-- replace(s): cpuwait, ret_st1, reti_st1, idc_pop, idc_ret, idc_reti
2392 
 
2393 
-- STACK POINTER CONTROL
2394 
sp_ndown_up_cml_out <= idc_pop_cml_1 or idc_ret_cml_1 or (ret_st1_cml_1 and not cpuwait_cml_1) or idc_reti_cml_1 or (reti_st1_cml_1 and not cpuwait_cml_1); -- ?????????
2395 
sp_en_cml_out <= idc_push_cml_1 or idc_pop_cml_1 or idc_rcall_cml_1 or (rcall_st1_cml_1 and not cpuwait_cml_1) or idc_icall_cml_1 or (icall_st1_cml_1 and not cpuwait_cml_1) or
2396 
idc_ret_cml_1 or (ret_st1_cml_1 and not cpuwait_cml_1) or idc_reti_cml_1 or (reti_st1_cml_1 and not cpuwait_cml_1) or
2397 
call_st1_cml_1 or (call_st2_cml_1 and not cpuwait_cml_1) or irq_st1_cml_1 or (irq_st2_cml_1 and not cpuwait_cml_1); --????????
2398 
 
2399 
 
2400 
branch  <= dex_condition;
2401 
bit_num_r_io <= cbi_sbi_bit_num_tmp when (cbi_st or sbi_st)='1' else dex_bitop_bitnum;
2402 
 
2403 
-- SynEDA CoreMultiplier
2404 
-- assignment(s): adr
2405 
-- replace(s): adr_int
2406 
 
2407 
adr_cml_out <= adr_int_cml_1;
2408 
 
2409 
ramre <= ramre_int;
2410 
ramwe <= ramwe_int;
2411 
 
2412 
-- SynEDA CoreMultiplier
2413 
-- assignment(s): iore
2414 
-- replace(s): iore_int
2415 
 
2416 
iore_cml_out <= iore_int_cml_1;
2417 
iowe <= iowe_int;
2418 
 
2419 
--dbusout <= dbusout_int;
2420 
 
2421 
-- Sleep Control
2422 
sleepi <= idc_sleep;
2423 
irqok  <= irq_int;
2424 
 
2425 
-- Watchdog
2426 
wdri <= idc_wdr;
2427 
 
2428 
-- ************************** JTAG OCD support ************************************
2429 
 
2430 
-- Change of flow
2431 
change_flow <= '0';
2432 
valid_instr <= '0';
2433 
 
2434 
 
2435 
end RTL;

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