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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [prbs-31.vhdl] - Blame information for rev 18

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1 18 daniel.kho
/*
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        This file is part of the Galois Linear Feedback Shift Register
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        (galois_lfsr) project:
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                http://www.opencores.org/project,galois_lfsr
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        Description
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        Synthesisable use case for Galois LFSR.
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        This example is a CRC generator that uses a Galois LFSR.
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        ToDo:
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        Author(s):
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        - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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        Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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        This source file may be used and distributed without
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        restriction provided that this copyright statement is not
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        removed from the file and that any derivative work contains
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        the original copyright notice and the associated disclaimer.
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        This source file is free software; you can redistribute it
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        and/or modify it under the terms of the GNU Lesser General
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        Public License as published by the Free Software Foundation;
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        either version 2.1 of the License, or (at your option) any
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        later version.
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        This source is distributed in the hope that it will be
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        useful, but WITHOUT ANY WARRANTY; without even the implied
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        warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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        PURPOSE. See the GNU Lesser General Public License for more
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        details.
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        You should have received a copy of the GNU Lesser General
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        Public License along with this source; if not, download it
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        from http://www.opencores.org/lgpl.shtml.
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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/* Enable for synthesis; comment out for simulation.
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        For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
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        but Quartus doesn't yet support this.
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*/
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--library tauhop; use tauhop.types.all, tauhop.axiTransactor.all;
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/* TODO remove once generic packages are supported. */
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library tauhop; use tauhop.types.all, tauhop.tlm.all, tauhop.axiTLM.all;
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entity prbs31 is
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        generic(
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                isParallelLoad:boolean:=false;
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                tapVector:boolean_vector:=(
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                        /* Example polynomial from Wikipedia:
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                                http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
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                        */
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                        --0|1|2|8=>true, 7 downto 3=>false
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                        0|3|31=>true, 1|2|30 downto 4=>false
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                )
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        );
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        port(
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                /* Comment-out for simulation. */
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                clk,reset:in std_ulogic;
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                en:in boolean;
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--              seed:in unsigned(tapVector'high downto 0);
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--              prbs:out unsigned(31 downto 0):=(others=>'0')
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                seed:in t_msg;
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                prbs:out t_msg
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        );
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end entity prbs31;
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architecture rtl of prbs31 is
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        signal n,c:natural;
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        /* Tester signals. */
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        signal d:std_ulogic;
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        /* synthesis translate_off */
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--      signal clk,reset:std_ulogic:='0';
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        /* synthesis translate_on */
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        signal loadEn:std_ulogic;               -- clock gating.
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        signal load:boolean;
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--      signal loadEn,computeClk:std_ulogic;            -- clock gating.
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        signal loaded,i_loaded:boolean;
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--      signal computed,i_computed:boolean;
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begin
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--      loadEn<=clk when reset='0' and not i_computed else '0';
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        loadEn<=clk when reset='0' and en else '0';
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        /* Galois LFSR instance. */
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        i_lfsr: entity tauhop.lfsr(rtl)
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                generic map(taps=>tapVector)
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                /*generic map(taps => (
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                        0|1|2|8=>true,
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                        7 downto 3=>false
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                ))*/
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                port map(nReset=>not reset, clk=>loadEn,
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--                      load=>isParallelLoad,
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                        load=>load,
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                        seed=>seed,
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                        d=>d,
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                        q=>prbs(prbs'range)
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        );
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        /* Load message into LFSR. */
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        process(reset,loadEn) is begin
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                if reset then loaded<=false; n<=seed'length-1; d<='0';
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--              if reset then loaded<=false; n<=seed'length-1;
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                elsif rising_edge(loadEn) then
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                        d<='0';
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                        /* for parallel mode, LFSR automatically loads the seed in parallel. */
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                        if isParallelLoad then loaded<=true;
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                        else
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                                if not loaded then d<=seed(n); end if;
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                                if n>0 then n<=n-1;
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                                else loaded<=true;
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                                end if;
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                        end if;
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                end if;
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        end process;
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        load<=(loaded xor i_loaded) and isParallelLoad and reset='0';
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        /* Register pipelines. */
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    process(clk) is begin
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        if rising_edge(clk) then
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            i_loaded<=loaded;
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        end if;
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    end process;
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end architecture rtl;

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